1 /******************************************************************************* 2 * Copyright 2020 Microchip Corporation. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Register bit definitions for MII STA (station management entity) standard 7 * interface. All basic MII register bits and enhanced capability register bits 8 * are defined. 9 * Complies with Clauses 22, 28, 37, 40 of IEEE RFC 802.3 10 * 11 */ 12 #ifndef PSE_PHY_H 13 #define PSE_PHY_H 14 #include "../mss_ethernet_mac/mss_ethernet_mac_types.h" 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /**************************************************************************/ 21 /* Public definitions */ 22 /**************************************************************************/ 23 /*------------------------------------------------------------------------------ 24 * MII register definitions. 25 */ 26 /* Generic MII registers. */ 27 #define MII_BMCR (0X00U) /* Basic mode control register */ 28 #define MII_BMSR (0X01U) /* Basic mode status register */ 29 #define MII_PHYSID1 (0X02U) /* PHYS ID 1 */ 30 #define MII_PHYSID2 (0X03U) /* PHYS ID 2 */ 31 #define MII_ADVERTISE (0X04U) /* Advertisement control reg */ 32 #define MII_LPA (0X05U) /* Link partner ability reg */ 33 #define MII_EXPANSION (0X06U) /* Expansion register */ 34 #define MII_NPAR (0X07U) 35 #define MII_LPNPA (0X08U) 36 #define MII_CTRL1000 (0X09U) /* 1000BASE-T control */ 37 #define MII_STAT1000 (0X0AU) /* 1000BASE-T status */ 38 #define MII_ESTATUS (0X0FU) /* Extended Status */ 39 #define MII_DCOUNTER (0X12U) /* Disconnect counter */ 40 #define MII_FCSCOUNTER (0X13U) /* False carrier counter */ 41 #define MII_EXTEND (0X14U) /* extended PHY specific ctrl */ 42 #define MII_RERRCOUNTER (0X15U) /* Receive error counter */ 43 #define MII_SREVISION (0X16U) /* Silicon revision */ 44 #define MII_RESV1 (0X17U) /* Reserved... */ 45 #define MII_LBRERROR (0X18U) /* Lpback, rx, bypass error */ 46 #define MII_PHYADDR (0X19U) /* PHY address */ 47 #define MII_RESV2 (0X1AU) /* Reserved... */ 48 #define MII_TPISTATUS (0X1BU) /* TPI status for 10mbps */ 49 #define MII_NCONFIG (0X1CU) /* Network interface config */ 50 #define MII_LMCS (0X1DU) 51 #define MII_PHYCTRL1 (0X1EU) 52 #define MII_PHYCTRL2 (0X1FU) 53 54 #define MII_TI_REGCR (0X0DU) 55 #define MII_TI_ADDAR (0X0EU) 56 #define MII_TI_PHYCR (0X10U) 57 #define MII_TI_CTRL (0X1FU) 58 #define MII_TI_SGMIICTL1 (0XD3U) 59 60 /* Basic mode control register. */ 61 #define BMCR_RESV (0x003FU) /* Unused... */ 62 #define BMCR_SPEED1000 (0x0040U) /* MSB of Speed (1000) */ 63 #define BMCR_CTST (0x0080U) /* Collision test */ 64 #define BMCR_FULLDPLX (0x0100U) /* Full duplex */ 65 #define BMCR_ANRESTART (0x0200U) /* Auto negotiation restart */ 66 #define BMCR_ISOLATE (0x0400U) /* Disconnect DP83840 from MII */ 67 #define BMCR_PDOWN (0x0800U) /* Powerdown the DP83840 */ 68 #define BMCR_ANENABLE (0x1000U) /* Enable auto negotiation */ 69 #define BMCR_SPEED100 (0x2000U) /* Select 100Mbps */ 70 #define BMCR_LOOPBACK (0x4000U) /* TXD loopback bits */ 71 #define BMCR_RESET (0x8000U) /* Reset the DP83840 */ 72 73 /* Basic mode status register. */ 74 #define BMSR_ERCAP (0x0001U) /* Ext-reg capability */ 75 #define BMSR_JCD (0x0002U) /* Jabber detected */ 76 #define BMSR_LSTATUS (0x0004U) /* Link status */ 77 #define BMSR_ANEGCAPABLE (0x0008U) /* Able to do auto-negotiation */ 78 #define BMSR_RFAULT (0x0010U) /* Remote fault detected */ 79 #define BMSR_ANEGCOMPLETE (0x0020U) /* Auto-negotiation complete */ 80 #define BMSR_RESV (0x00c0U) /* Unused... */ 81 #define BMSR_ESTATEN (0x0100U) /* Extended Status in R15 */ 82 #define BMSR_100HALF2 (0x0200U) /* Can do 100BASE-T2 HDX */ 83 #define BMSR_100FULL2 (0x0400U) /* Can do 100BASE-T2 FDX */ 84 #define BMSR_10HALF (0x0800U) /* Can do 10mbps, half-duplex */ 85 #define BMSR_10FULL (0x1000U) /* Can do 10mbps, full-duplex */ 86 #define BMSR_100HALF (0x2000U) /* Can do 100mbps, half-duplex */ 87 #define BMSR_100FULL (0x4000U) /* Can do 100mbps, full-duplex */ 88 #define BMSR_100BASE4 (0x8000U) /* Can do 100mbps, 4k packets */ 89 90 /* Advertisement control register. */ 91 #define ADVERTISE_SLCT (0x001FU) /* Selector bits */ 92 #define ADVERTISE_CSMA (0x0001U) /* Only selector supported */ 93 #define ADVERTISE_10HALF (0x0020U) /* Try for 10mbps half-duplex */ 94 #define ADVERTISE_1000XFULL (0x0020U) /* Try for 1000BASE-X full-duplex */ 95 #define ADVERTISE_10FULL (0x0040U) /* Try for 10mbps full-duplex */ 96 #define ADVERTISE_1000XHALF (0x0040U) /* Try for 1000BASE-X half-duplex */ 97 #define ADVERTISE_100HALF (0x0080U) /* Try for 100mbps half-duplex */ 98 #define ADVERTISE_1000XPAUSE (0x0080U) /* Try for 1000BASE-X pause */ 99 #define ADVERTISE_100FULL (0x0100U) /* Try for 100mbps full-duplex */ 100 #define ADVERTISE_1000XPSE_ASYM (0x0100U) /* Try for 1000BASE-X asym pause */ 101 #define ADVERTISE_100BASE4 (0x0200U) /* Try for 100mbps 4k packets */ 102 #define ADVERTISE_PAUSE_CAP (0x0400U) /* Try for pause */ 103 #define ADVERTISE_PAUSE_ASYM (0x0800U) /* Try for asymetric pause */ 104 #define ADVERTISE_RESV (0x1000U) /* Unused... */ 105 #define ADVERTISE_RFAULT (0x2000U) /* Say we can detect faults */ 106 #define ADVERTISE_LPACK (0x4000U) /* Ack link partners response */ 107 #define ADVERTISE_NPAGE (0x8000U) /* Next page bit */ 108 109 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 110 ADVERTISE_CSMA) 111 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 112 ADVERTISE_100HALF | ADVERTISE_100FULL) 113 114 /* Link partner ability register. */ 115 #define LPA_SLCT (0x001FU) /* Same as advertise selector */ 116 #define LPA_10HALF (0x0020U) /* Can do 10mbps half-duplex */ 117 #define LPA_1000XFULL (0x0020U) /* Can do 1000BASE-X full-duplex */ 118 #define LPA_10FULL (0x0040U) /* Can do 10mbps full-duplex */ 119 #define LPA_1000XHALF (0x0040U) /* Can do 1000BASE-X half-duplex */ 120 #define LPA_100HALF (0x0080U) /* Can do 100mbps half-duplex */ 121 #define LPA_1000XPAUSE (0x0080U) /* Can do 1000BASE-X pause */ 122 #define LPA_100FULL (0x0100U) /* Can do 100mbps full-duplex */ 123 #define LPA_1000XPAUSE_ASYM (0x0100U) /* Can do 1000BASE-X pause asym*/ 124 #define LPA_100BASE4 (0x0200U) /* Can do 100mbps 4k packets */ 125 #define LPA_PAUSE_CAP (0x0400U) /* Can pause */ 126 #define LPA_PAUSE_ASYM (0x0800U) /* Can pause asymetrically */ 127 #define LPA_RESV (0x1000U) /* Unused... */ 128 #define LPA_RFAULT (0x2000U) /* Link partner faulted */ 129 #define LPA_LPACK (0x4000U) /* Link partner acked us */ 130 #define LPA_NPAGE (0x8000U) /* Next page bit */ 131 132 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 133 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 134 135 /* Expansion register for auto-negotiation. */ 136 #define EXPANSION_NWAY (0X0001U) /* Can do N-way auto-nego */ 137 #define EXPANSION_LCWP (0X0002U) /* Got new RX page code word */ 138 #define EXPANSION_ENABLENPAGE (0X0004U) /* This enables npage words */ 139 #define EXPANSION_NPCAPABLE (0X0008U) /* Link partner supports npage */ 140 #define EXPANSION_MFAULTS (0X0010U) /* Multiple faults detected */ 141 #define EXPANSION_RESV (0XFFE0U) /* Unused... */ 142 143 #define ESTATUS_1000_TFULL (0x2000U) /* Can do 1000BT Full */ 144 #define ESTATUS_1000_THALF (0x1000U) /* Can do 1000BT Half */ 145 146 /* N-way test register. */ 147 #define NWAYTEST_RESV1 (0X00FFU) /* Unused... */ 148 #define NWAYTEST_LOOPBACK (0X0100U) /* Enable loopback for N-way */ 149 #define NWAYTEST_RESV2 (0XFE00U) /* Unused... */ 150 151 /* 1000BASE-T Control register */ 152 #define ADVERTISE_1000FULL (0x0200U) /* Advertise 1000BASE-T full duplex */ 153 #define ADVERTISE_1000HALF (0x0100U) /* Advertise 1000BASE-T half duplex */ 154 155 /* 1000BASE-T Status register */ 156 #define LPA_1000LOCALRXOK (0x2000U) /* Link partner local receiver status */ 157 #define LPA_1000REMRXOK (0x1000U) /* Link partner remote receiver status */ 158 #define LPA_1000FULL (0x0800U) /* Link partner 1000BASE-T full duplex */ 159 #define LPA_1000HALF (0x0400U) /* Link partner 1000BASE-T half duplex */ 160 161 /* Indicates what features are supported by the interface. */ 162 #define SUPPORTED_10baseT_Half (1U << 0) 163 #define SUPPORTED_10baseT_Full (1U << 1) 164 #define SUPPORTED_100baseT_Half (1U << 2) 165 #define SUPPORTED_100baseT_Full (1U << 3) 166 #define SUPPORTED_1000baseT_Half (1U << 4) 167 #define SUPPORTED_1000baseT_Full (1U << 5) 168 #define SUPPORTED_Autoneg (1U << 6) 169 #define SUPPORTED_TP (1U << 7) 170 #define SUPPORTED_AUI (1U << 8) 171 #define SUPPORTED_MII (1U << 9) 172 #define SUPPORTED_FIBRE (1U << 10) 173 #define SUPPORTED_BNC (1U << 11) 174 #define SUPPORTED_10000baseT_Full (1U << 12) 175 #define SUPPORTED_Pause (1U << 13) 176 #define SUPPORTED_Asym_Pause (1U << 14) 177 #define SUPPORTED_2500baseX_Full (1U << 15) 178 #define SUPPORTED_Backplane (1U << 16) 179 #define SUPPORTED_1000baseKX_Full (1U << 17) 180 #define SUPPORTED_10000baseKX4_Full (1U << 18) 181 #define SUPPORTED_10000baseKR_Full (1U << 19) 182 #define SUPPORTED_10000baseR_FEC (1U << 20) 183 184 /* Indicates what features are advertised by the interface. */ 185 #define ADVERTISED_10baseT_Half (1U << 0) 186 #define ADVERTISED_10baseT_Full (1U << 1) 187 #define ADVERTISED_100baseT_Half (1U << 2) 188 #define ADVERTISED_100baseT_Full (1U << 3) 189 #define ADVERTISED_1000baseT_Half (1U << 4) 190 #define ADVERTISED_1000baseT_Full (1U << 5) 191 #define ADVERTISED_Autoneg (1U << 6) 192 #define ADVERTISED_TP (1U << 7) 193 #define ADVERTISED_AUI (1U << 8) 194 #define ADVERTISED_MII (1U << 9) 195 #define ADVERTISED_FIBRE (1U << 10) 196 #define ADVERTISED_BNC (1U << 11) 197 #define ADVERTISED_10000baseT_Full (1U << 12) 198 #define ADVERTISED_Pause (1U << 13) 199 #define ADVERTISED_Asym_Pause (1U << 14) 200 #define ADVERTISED_2500baseX_Full (1U << 15) 201 #define ADVERTISED_Backplane (1U << 16) 202 #define ADVERTISED_1000baseKX_Full (1U << 17) 203 #define ADVERTISED_10000baseKX4_Full (1U << 18) 204 #define ADVERTISED_10000baseKR_Full (1U << 19) 205 #define ADVERTISED_10000baseR_FEC (1U << 20) 206 207 /* TI DP83867 PHY Control Register */ 208 209 #define PHYCR_TX_FIFO_DEPTH (0xC000U) 210 #define PHYCR_RX_FIFO_DEPTH (0x3000U) 211 #define PHYCR_SGMII_EN (0x0800U) 212 #define PHYCR_FORCE_LINK_GOOD (0x0400U) 213 #define PHYCR_POWER_SAVE_MODE (0x0300U) 214 #define PHYCR_DEEP_POWER_DOWN_EN (0x0080U) 215 #define PHYCR_MDI_CROSSOVER (0x0060U) 216 #define PHYCR_DISABLE_CLK_125 (0x0010U) 217 #define PHYCR_STANDBY_MODE (0x0004U) 218 #define PHYCR_LINE_DRIVER_INV_EN (0x0002U) 219 #define PHYCR_DISABLE_JABBER (0x0001U) 220 221 /* TI DP83867 Control Register */ 222 223 #define CTRL_SW_RESET (0x8000U) 224 #define CTRL_SW_RESTART (0x4000U) 225 226 /* TI DP83867 SGMII Control Register 1 */ 227 228 #define SGMII_TYPE_6_WIRE (0x4000U) 229 230 /* Different PHY MDIO addresses for our current designs */ 231 232 #if defined(TARGET_ALOE) 233 #define PHY_VSC8541_MDIO_ADDR (0U) /* Aloe board PHY */ 234 #else 235 #define PHY_VSC8541_MDIO_ADDR (26U) /* SVG MSS board PHY */ 236 #endif 237 #define PHY_VSC8662_0_MDIO_ADDR (8U) /* SVG MSS board port 0 */ 238 #define PHY_VSC8662_1_MDIO_ADDR (9U) /* SVG MSS board port 1 */ 239 #define PHY_VSC8575_MDIO_ADDR (4U) /* G5 SoC Emulation Platform Peripheral Daughter Board PHY */ 240 #define PHY_DP83867_MDIO_ADDR (3U) /* G5 SoC Emulation Platform native PHY */ 241 #define PHY_NULL_MDIO_ADDR (0U) /* No PHY here actually... */ 242 #define SGMII_MDIO_ADDR (16U) /* Internal PHY in G5 SoC Emulation Platform SGMII to GMII core */ 243 244 245 /**************************************************************************/ 246 /* Public function declarations */ 247 /**************************************************************************/ 248 249 /***************************************************************************//** 250 void MSS_MAC_phy_init(mss_mac_instance_t *this_mac, uint8_t phy_addr); 251 */ 252 #if MSS_MAC_USE_PHY_VSC8541 253 void MSS_MAC_VSC8541_phy_init(/* mss_mac_instance_t */ const void *v_this_mac, uint8_t phy_addr); 254 #endif 255 256 #if MSS_MAC_USE_PHY_VSC8575 || MSS_MAC_USE_PHY_VSC8575_LITE 257 void MSS_MAC_VSC8575_phy_init(/* mss_mac_instance_t */ const void *v_this_mac, uint8_t phy_addr); 258 #endif 259 260 #if MSS_MAC_USE_PHY_VSC8662 261 void MSS_MAC_VSC8662_phy_init(/* mss_mac_instance_t */ const void *v_this_mac, uint8_t phy_addr); 262 #endif 263 264 #if MSS_MAC_USE_PHY_DP83867 265 void MSS_MAC_DP83867_phy_init(/* mss_mac_instance_t */ const void *v_this_mac, uint8_t phy_addr); 266 #endif 267 268 #if MSS_MAC_USE_PHY_NULL 269 void MSS_MAC_NULL_phy_init(/* mss_mac_instance_t */ const void *v_this_mac, uint8_t phy_addr); 270 #endif 271 272 /***************************************************************************//** 273 274 */ 275 #if MSS_MAC_USE_PHY_VSC8541 276 void MSS_MAC_VSC8541_phy_set_link_speed(/* mss_mac_instance_t*/ void *v_this_mac, uint32_t speed_duplex_select, mss_mac_speed_mode_t speed_mode); 277 #endif 278 279 #if MSS_MAC_USE_PHY_VSC8575 || MSS_MAC_USE_PHY_VSC8575_LITE 280 void MSS_MAC_VSC8575_phy_set_link_speed(/* mss_mac_instance_t */ void *v_this_mac, uint32_t speed_duplex_select, mss_mac_speed_mode_t speed_mode); 281 #endif 282 283 #if MSS_MAC_USE_PHY_VSC8662 284 void MSS_MAC_VSC8662_phy_set_link_speed(/* mss_mac_instance_t */ void *v_this_mac, uint32_t speed_duplex_select, mss_mac_speed_mode_t speed_mode); 285 #endif 286 287 #if MSS_MAC_USE_PHY_DP83867 288 void MSS_MAC_DP83867_phy_set_link_speed(/* mss_mac_instance_t */ void *v_this_mac, uint32_t speed_duplex_select, mss_mac_speed_mode_t speed_mode); 289 #endif 290 291 #if MSS_MAC_USE_PHY_NULL 292 void MSS_MAC_NULL_phy_set_link_speed(/* mss_mac_instance_t */ void *v_this_mac, uint32_t speed_duplex_select, mss_mac_speed_mode_t speed_mode); 293 #endif 294 295 /***************************************************************************//** 296 297 */ 298 #if MSS_MAC_USE_PHY_VSC8541 299 void MSS_MAC_VSC8541_phy_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 300 void MSS_MAC_VSC8541_mac_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 301 #endif 302 303 #if MSS_MAC_USE_PHY_VSC8575 || MSS_MAC_USE_PHY_VSC8575_LITE 304 void MSS_MAC_VSC8575_phy_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 305 void MSS_MAC_VSC8575_mac_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 306 #endif 307 308 #if MSS_MAC_USE_PHY_VSC8662 309 void MSS_MAC_VSC8662_phy_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 310 void MSS_MAC_VSC8662_mac_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 311 #endif 312 313 #if MSS_MAC_USE_PHY_DP83867 314 void MSS_MAC_DP83867_phy_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 315 void MSS_MAC_DP83867_mac_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 316 317 #endif 318 319 #if MSS_MAC_USE_PHY_NULL 320 void MSS_MAC_NULL_phy_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 321 void MSS_MAC_NULL_phy_mac_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac); 322 #endif 323 /***************************************************************************//** 324 325 */ 326 327 #if MSS_MAC_USE_PHY_VSC8541 328 uint8_t MSS_MAC_VSC8541_phy_get_link_status 329 ( 330 /* mss_mac_instance_t */ const void *v_this_mac, 331 mss_mac_speed_t * speed, 332 uint8_t * fullduplex 333 ); 334 #endif 335 336 #if MSS_MAC_USE_PHY_VSC8575 || MSS_MAC_USE_PHY_VSC8575_LITE 337 uint8_t MSS_MAC_VSC8575_phy_get_link_status 338 ( 339 /* mss_mac_instance_t */ const void *v_this_mac, 340 mss_mac_speed_t * speed, 341 uint8_t * fullduplex 342 ); 343 #endif 344 345 #if MSS_MAC_USE_PHY_VSC8662 346 uint8_t MSS_MAC_VSC8662_phy_get_link_status 347 ( 348 /* mss_mac_instance_t */ const void *v_this_mac, 349 mss_mac_speed_t * speed, 350 uint8_t * fullduplex 351 ); 352 #endif 353 354 #if MSS_MAC_USE_PHY_DP83867 355 uint8_t MSS_MAC_DP83867_phy_get_link_status 356 ( 357 /* mss_mac_instance_t */ const void *v_this_mac, 358 mss_mac_speed_t * speed, 359 uint8_t * fullduplex 360 ); 361 #endif 362 363 #if MSS_MAC_USE_PHY_NULL 364 uint8_t MSS_MAC_NULL_phy_get_link_status 365 ( 366 /* mss_mac_instance_t */ const void *v_this_mac, 367 mss_mac_speed_t * speed, 368 uint8_t * fullduplex 369 ); 370 #endif 371 372 373 #if MSS_MAC_USE_PHY_DP83867 374 /***************************************************************************//** 375 376 */ 377 void ti_write_extended_regs(/* mss_mac_instance_t */ const void *v_this_mac, uint16_t reg, uint16_t data); 378 379 #if MSS_MAC_USE_PHY_NULL 380 void NULL_ti_write_extended_regs(/* mss_mac_instance_t */ const void *v_this_mac, uint16_t reg, uint16_t data); 381 #endif 382 383 /***************************************************************************//** 384 385 */ 386 uint16_t ti_read_extended_regs(/* mss_mac_instance_t */ const void *v_this_mac, uint16_t reg); 387 388 #if MSS_MAC_USE_PHY_NULL 389 uint16_t NULL_ti_read_extended_regs(/* mss_mac_instance_t */ const void *v_this_mac, uint16_t reg); 390 #endif 391 392 #endif 393 394 #ifdef __cplusplus 395 } 396 #endif 397 398 #endif /* PSE_PHY_H */ 399 400 401
