Searched refs:REG32 (Results 1 – 9 of 9) sorted by relevance
330 #define MCHP_PCR_SLP_CTRL() REG32(MCHP_PCR_SYS_SLP_CTRL_ADDR)332 #define MCHP_PCR_SLOW_CLK_CTRL() REG32(MCHP_PCR_SLOW_CLK_CTRL_ADDR)333 #define MCHP_PCR_OSC_ID() REG32(MCHP_PCR_OSC_ID_ADDR)334 #define MCHP_PCR_PRS() REG32(MCHP_PCR_PRS_ADDR)335 #define MCHP_PCR_PR_CTRL() REG32(MCHP_PCR_PR_CTRL_ADDR)336 #define MCHP_PCR_SYS_RESET() REG32(MCHP_PCR_SYS_RESET_ADDR)338 REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR)339 #define MCHP_PCR_SLP_EN(n) REG32(MCHP_PCR_SLP_EN_ADDR(n))340 #define MCHP_PCR_CLK_REQ_RO(n) REG32(MCHP_PCR_CLK_REQ_ADDR(n))341 #define MCHP_PCR_SLP_EN0() REG32(MCHP_PCR_SLP_EN_ADDR(0))[all …]
147 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHB_ERR_ADDR_OFS)150 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHB_ERR_CTRL_OFS)153 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ICTRL_OFS)156 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ETM_CTRL_OFS)159 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_DCTRL_OFS)162 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHSW_OFS)165 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_GBPWR_OFS)
68 REG32(MCHP_NVIC_SET_EN_BASE + ((uintptr_t)(n) * 4u))71 REG32(MCHP_NVIC_CLR_EN_BASE + ((uintptr_t)(n) * 4u))74 REG32(MCHP_NVIC_SET_PEND_BASE + ((uintptr_t)(n) * 4u))77 REG32(MCHP_NVIC_CLR_PEND_BASE + ((uintptr_t)(n) * 4u))258 REG32(MCHP_GIRQ_BLK_ENSET_ADDR)261 REG32(MCHP_GIRQ_BLK_ENCLR_ADDR)264 REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR)272 REG32(MCHP_GIRQ_BLK_ENSET_ADDR) = BIT(n)275 REG32(MCHP_GIRQ_BLK_ENCLR_ADDR) = BIT(n)278 ((REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR) & BIT(n)) != 0u)[all …]
339 #define MCHP_QMSPI_MODE() REG32(MCHP_QMSPI_MODE_ADDR)345 #define MCHP_QMSPI_CTRL() REG32(MCHP_QMSPI_CTRL_ADDR)354 #define MCHP_QMSPI_STS() REG32(MCHP_QMSPI_STS_ADDR)357 #define MCHP_QMSPI_BCNT_STS() REG32(MCHP_QMSPI_BUFCNT_STS_ADDR)364 #define MCHP_QMSPI_IEN() REG32(MCHP_QMSPI_IEN_ADDR)367 #define MCHP_QMSPI_TXB_32() REG32(MCHP_QMSPI_TXB_ADDR)372 #define MCHP_QMSPI_RXB_32() REG32(MCHP_QMSPI_RXB_ADDR)380 #define MCHP_QMSPI_DESCR(id) REG32(MCHP_QMSPI_DESCR_ADDR(id))
949 REG32(gp_ctrl_addr) = in mchp_gpio_pud_set()950 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_PUD_MASK)) in mchp_gpio_pud_set()958 REG32(gp_ctrl_addr) = in mchp_gpio_pwrgt_set()959 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_PWRG_MASK)) in mchp_gpio_pwrgt_set()967 REG32(gp_ctrl_addr) = in mchp_gpio_idet_set()968 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_IDET_MASK)) in mchp_gpio_idet_set()976 REG32(gp_ctrl_addr) = in mchp_gpio_outbuf_set()977 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_BUFT_MASK)) in mchp_gpio_outbuf_set()985 REG32(gp_ctrl_addr) = in mchp_gpio_dir_set()986 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_DIR_MASK)) in mchp_gpio_dir_set()[all …]
106 REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_MCNT_LSW_OFS)109 REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_MCNT_MSW_OFS)
126 REG32(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_DEV_ID_REG32_OFS)
182 #define MCHP_ADC_RD_CHAN(n) REG32(MCHP_ADC_CH_ADDR(n))
44 #define REG32(a) *((volatile uint32_t *)(uintptr_t)(a)) macro