1 /******************************************************************************* 2 * Copyright 2020 Microchip Corporation. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * This file contains the type definitions for the GEM Ethernet MAC as 7 * implemented for the PolarFire SoC. This also covers the subset implemented for 8 * the FU540 on the Aloe board with the provisio that many of the registers will 9 * not be present on that device. 10 * 11 * We use separate MAC and eMAC definitions even though the eMAC is a subset 12 * of the MAC as it helps to catch errors if we try to program registers not 13 * present on the eMAC. 14 * 15 */ 16 #ifndef MSS_ETHERNET_MAC_REGISTERS_H_ 17 #define MSS_ETHERNET_MAC_REGISTERS_H_ 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 /*----------------------------------------------------------------------------*/ 23 /*----------------------------------- MAC -----------------------------------*/ 24 /*----------------------------------------------------------------------------*/ 25 #define __I const volatile 26 #define __O volatile 27 #define __IO volatile 28 29 typedef struct 30 { 31 __IO uint32_t NETWORK_CONTROL; /* 0x0000 */ 32 __IO uint32_t NETWORK_CONFIG; /* 0x0004 */ 33 __I uint32_t NETWORK_STATUS; /* 0x0008 */ 34 __IO uint32_t USER_IO; /* 0x000C */ 35 __IO uint32_t DMA_CONFIG; /* 0x0010 */ 36 __IO uint32_t TRANSMIT_STATUS; /* 0x0014 */ 37 __IO uint32_t RECEIVE_Q_PTR; /* 0x0018 */ 38 __IO uint32_t TRANSMIT_Q_PTR; /* 0x001C */ 39 __IO uint32_t RECEIVE_STATUS; /* 0x0020 */ 40 __IO uint32_t INT_STATUS; /* 0x0024 */ 41 __IO uint32_t INT_ENABLE; /* 0x0028 */ 42 __IO uint32_t INT_DISABLE; /* 0x002C */ 43 __IO uint32_t INT_MASK; /* 0x0030 */ 44 __IO uint32_t PHY_MANAGEMENT; /* 0x0034 */ 45 __IO uint32_t PAUSE_TIME; /* 0x0038 */ 46 __IO uint32_t TX_PAUSE_QUANTUM; /* 0x003C */ 47 __IO uint32_t PBUF_TXCUTTHRU; /* 0x0040 */ 48 __IO uint32_t PBUF_RXCUTTHRU; /* 0x0044 */ 49 __IO uint32_t JUMBO_MAX_LENGTH; /* 0x0048 */ 50 uint32_t reserved1; /* 0x004C */ 51 uint32_t reserved2; /* 0x0050 */ 52 __IO uint32_t AXI_MAX_PIPELINE; /* 0x0054 */ 53 uint32_t reserved3; /* 0x0058 */ 54 __IO uint32_t INT_MODERATION; /* 0x005C */ 55 __IO uint32_t SYS_WAKE_TIME; /* 0x0060 */ 56 __IO uint32_t FATAL_OR_NON_FATAL_INT_SEL; /* 0x0064 */ 57 __IO uint32_t LOCKUP_CONFIG; /* 0x0068 */ 58 __IO uint32_t RX_MAC_LOCKUP_TIME; /* 0x006C */ 59 uint32_t reserved4; /* 0x0070 */ 60 uint32_t reserved5; /* 0x0074 */ 61 uint32_t reserved6; /* 0x0078 */ 62 uint32_t reserved7; /* 0x007C */ 63 __IO uint32_t HASH_BOTTOM; /* 0x0080 */ 64 __IO uint32_t HASH_TOP; /* 0x0084 */ 65 __IO uint32_t SPEC_ADD1_BOTTOM; /* 0x0088 */ 66 __IO uint32_t SPEC_ADD1_TOP; /* 0x008C */ 67 __IO uint32_t SPEC_ADD2_BOTTOM; /* 0x0090 */ 68 __IO uint32_t SPEC_ADD2_TOP; /* 0x0094 */ 69 __IO uint32_t SPEC_ADD3_BOTTOM; /* 0x0098 */ 70 __IO uint32_t SPEC_ADD3_TOP; /* 0x009C */ 71 __IO uint32_t SPEC_ADD4_BOTTOM; /* 0x00A0 */ 72 __IO uint32_t SPEC_ADD4_TOP; /* 0x00A4 */ 73 __IO uint32_t SPEC_TYPE1; /* 0x00A8 */ 74 __IO uint32_t SPEC_TYPE2; /* 0x00AC */ 75 __IO uint32_t SPEC_TYPE3; /* 0x00B0 */ 76 __IO uint32_t SPEC_TYPE4; /* 0x00B4 */ 77 __IO uint32_t WOL_REGISTER; /* 0x00B8 */ 78 __IO uint32_t STRETCH_RATIO; /* 0x00BC */ 79 __IO uint32_t STACKED_VLAN; /* 0x00C0 */ 80 __IO uint32_t TX_PFC_PAUSE; /* 0x00C4 */ 81 __IO uint32_t MASK_ADD1_BOTTOM; /* 0x00C8 */ 82 __IO uint32_t MASK_ADD1_TOP; /* 0x00CC */ 83 __IO uint32_t DMA_ADDR_OR_MASK; /* 0x00D0 */ 84 __IO uint32_t RX_PTP_UNICAST; /* 0x00D4 */ 85 __IO uint32_t TX_PTP_UNICAST; /* 0x00D8 */ 86 __IO uint32_t TSU_NSEC_CMP; /* 0x00DC */ 87 __IO uint32_t TSU_SEC_CMP; /* 0x00E0 */ 88 __IO uint32_t TSU_MSB_SEC_CMP; /* 0x00E4 */ 89 __IO uint32_t TSU_PTP_TX_MSB_SEC_CMP; /* 0x00E8 */ 90 __IO uint32_t TSU_PTP_RX_MSB_SEC_CMP; /* 0x00EC */ 91 __IO uint32_t TSU_PEER_TX_MSB_SEC_CMP; /* 0x00F0 */ 92 __IO uint32_t TSU_PEER_RX_MSB_SEC_CMP; /* 0x00F4 */ 93 __IO uint32_t DPRAM_FILL_DBG; /* 0x00F8 */ 94 __IO uint32_t REVISION_REG; /* 0x00FC */ 95 __IO uint32_t OCTETS_TXED_BOTTOM; /* 0x0100 */ 96 __IO uint32_t OCTETS_TXED_TOP; /* 0x0104 */ 97 __IO uint32_t FRAMES_TXED_OK; /* 0x0108 */ 98 __IO uint32_t BROADCAST_TXED; /* 0x010C */ 99 __IO uint32_t MULTICAST_TXED; /* 0x0110 */ 100 __IO uint32_t PAUSE_FRAMES_TXED; /* 0x0114 */ 101 __IO uint32_t FRAMES_TXED_64; /* 0x0118 */ 102 __IO uint32_t FRAMES_TXED_65; /* 0x011C */ 103 __IO uint32_t FRAMES_TXED_128; /* 0x0120 */ 104 __IO uint32_t FRAMES_TXED_256; /* 0x0124 */ 105 __IO uint32_t FRAMES_TXED_512; /* 0x0128 */ 106 __IO uint32_t FRAMES_TXED_1024; /* 0x012C */ 107 __IO uint32_t FRAMES_TXED_1519; /* 0x0130 */ 108 __IO uint32_t TX_UNDERRUNS; /* 0x0134 */ 109 __IO uint32_t SINGLE_COLLISIONS; /* 0x0138 */ 110 __IO uint32_t MULTIPLE_COLLISIONS; /* 0x013C */ 111 __IO uint32_t EXCESSIVE_COLLISIONS; /* 0x0140 */ 112 __IO uint32_t LATE_COLLISIONS; /* 0x0144 */ 113 __IO uint32_t DEFERRED_FRAMES; /* 0x0148 */ 114 __IO uint32_t CRS_ERRORS; /* 0x014C */ 115 __IO uint32_t OCTETS_RXED_BOTTOM; /* 0x0150 */ 116 __IO uint32_t OCTETS_RXED_TOP; /* 0x0154 */ 117 __IO uint32_t FRAMES_RXED_OK; /* 0x0158 */ 118 __IO uint32_t BROADCAST_RXED; /* 0x015C */ 119 __IO uint32_t MULTICAST_RXED; /* 0x0160 */ 120 __IO uint32_t PAUSE_FRAMES_RXED; /* 0x0164 */ 121 __IO uint32_t FRAMES_RXED_64; /* 0x0168 */ 122 __IO uint32_t FRAMES_RXED_65; /* 0x016C */ 123 __IO uint32_t FRAMES_RXED_128; /* 0x0170 */ 124 __IO uint32_t FRAMES_RXED_256; /* 0x0174 */ 125 __IO uint32_t FRAMES_RXED_512; /* 0x0178 */ 126 __IO uint32_t FRAMES_RXED_1024; /* 0x017C */ 127 __IO uint32_t FRAMES_RXED_1519; /* 0x0180 */ 128 __IO uint32_t UNDERSIZE_FRAMES; /* 0x0184 */ 129 __IO uint32_t EXCESSIVE_RX_LENGTH; /* 0x0188 */ 130 __IO uint32_t RX_JABBERS; /* 0x018C */ 131 __IO uint32_t FCS_ERRORS; /* 0x0190 */ 132 __IO uint32_t RX_LENGTH_ERRORS; /* 0x0194 */ 133 __IO uint32_t RX_SYMBOL_ERRORS; /* 0x0198 */ 134 __IO uint32_t ALIGNMENT_ERRORS; /* 0x019C */ 135 __IO uint32_t RX_RESOURCE_ERRORS; /* 0x01A0 */ 136 __IO uint32_t RX_OVERRUNS; /* 0x01A4 */ 137 __IO uint32_t RX_IP_CK_ERRORS; /* 0x01A8 */ 138 __IO uint32_t RX_TCP_CK_ERRORS; /* 0x01AC */ 139 __IO uint32_t RX_UDP_CK_ERRORS; /* 0x01B0 */ 140 __IO uint32_t AUTO_FLUSHED_PKTS; /* 0x01B4 */ 141 uint32_t reserved8; /* 0x01B8 */ 142 __IO uint32_t TSU_TIMER_INCR_SUB_NSEC; /* 0x01BC */ 143 __IO uint32_t TSU_TIMER_MSB_SEC; /* 0x01C0 */ 144 __IO uint32_t TSU_STROBE_MSB_SEC; /* 0x01C4 */ 145 __IO uint32_t TSU_STROBE_SEC; /* 0x01C8 */ 146 __IO uint32_t TSU_STROBE_NSEC; /* 0x01CC */ 147 __IO uint32_t TSU_TIMER_SEC; /* 0x01D0 */ 148 __IO uint32_t TSU_TIMER_NSEC; /* 0x01D4 */ 149 __IO uint32_t TSU_TIMER_ADJUST; /* 0x01D8 */ 150 __IO uint32_t TSU_TIMER_INCR; /* 0x01DC */ 151 __IO uint32_t TSU_PTP_TX_SEC; /* 0x01E0 */ 152 __IO uint32_t TSU_PTP_TX_NSEC; /* 0x01E4 */ 153 __IO uint32_t TSU_PTP_RX_SEC; /* 0x01E8 */ 154 __IO uint32_t TSU_PTP_RX_NSEC; /* 0x01EC */ 155 __IO uint32_t TSU_PEER_TX_SEC; /* 0x01F0 */ 156 __IO uint32_t TSU_PEER_TX_NSEC; /* 0x01F4 */ 157 __IO uint32_t TSU_PEER_RX_SEC; /* 0x01F8 */ 158 __IO uint32_t TSU_PEER_RX_NSEC; /* 0x01FC */ 159 __IO uint32_t PCS_CONTROL; /* 0x0200 */ 160 __IO uint32_t PCS_STATUS; /* 0x0204 */ 161 __IO uint32_t PCS_PHY_TOP_ID; /* 0x0208 */ 162 __IO uint32_t PCS_PHY_BOT_ID; /* 0x020C */ 163 __IO uint32_t PCS_AN_ADV; /* 0x0210 */ 164 __IO uint32_t PCS_AN_LP_BASE; /* 0x0214 */ 165 __IO uint32_t PCS_AN_EXP; /* 0x0218 */ 166 __IO uint32_t PCS_AN_NP_TX; /* 0x021C */ 167 __IO uint32_t PCS_AN_LP_NP; /* 0x0220 */ 168 uint32_t reserved9[6]; /* 0x0224 - 0x0238 */ 169 __IO uint32_t PCS_AN_EXT_STATUS; /* 0x023C */ 170 uint32_t reserved10[8]; /* 0x0240 - 0x025C */ 171 __IO uint32_t TX_PAUSE_QUANTUM1; /* 0x0260 */ 172 __IO uint32_t TX_PAUSE_QUANTUM2; /* 0x0264 */ 173 __IO uint32_t TX_PAUSE_QUANTUM3; /* 0x0268 */ 174 __IO uint32_t PFC_STATUS; /* 0x026C */ 175 __IO uint32_t RX_LPI; /* 0x0270 */ 176 __IO uint32_t RX_LPI_TIME; /* 0x0274 */ 177 __IO uint32_t TX_LPI; /* 0x0278 */ 178 __IO uint32_t TX_LPI_TIME; /* 0x027C */ 179 __IO uint32_t DESIGNCFG_DEBUG1; /* 0x0280 */ 180 __IO uint32_t DESIGNCFG_DEBUG2; /* 0x0284 */ 181 __IO uint32_t DESIGNCFG_DEBUG3; /* 0x0288 */ 182 __IO uint32_t DESIGNCFG_DEBUG4; /* 0x028C */ 183 __IO uint32_t DESIGNCFG_DEBUG5; /* 0x0290 */ 184 __IO uint32_t DESIGNCFG_DEBUG6; /* 0x0294 */ 185 __IO uint32_t DESIGNCFG_DEBUG7; /* 0x0298 */ 186 __IO uint32_t DESIGNCFG_DEBUG8; /* 0x029C */ 187 __IO uint32_t DESIGNCFG_DEBUG9; /* 0x02A0 */ 188 __IO uint32_t DESIGNCFG_DEBUG10; /* 0x02A4 */ 189 __IO uint32_t DESIGNCFG_DEBUG11; /* 0x02A8 */ 190 __IO uint32_t DESIGNCFG_DEBUG12; /* 0x02AC */ 191 uint32_t reserved11[12]; /* 0x02B0 - 0x02DC */ 192 __IO uint32_t AXI_QoS_CFG_0; /* 0X02E0 */ 193 uint32_t reserved11a[71]; /* 0x02E4 - 0x03FC */ 194 __IO uint32_t INT_Q1_STATUS; /* 0x0400 */ 195 __IO uint32_t INT_Q2_STATUS; /* 0x0404 */ 196 __IO uint32_t INT_Q3_STATUS; /* 0x0408 */ 197 uint32_t reserved12[13]; /* 0x040C - 0x043C */ 198 __IO uint32_t TRANSMIT_Q1_PTR; /* 0x0440 */ 199 __IO uint32_t TRANSMIT_Q2_PTR; /* 0x0444 */ 200 __IO uint32_t TRANSMIT_Q3_PTR; /* 0x0448 */ 201 uint32_t reserved13[13]; /* 0x044C - 0x047C */ 202 __IO uint32_t RECEIVE_Q1_PTR; /* 0x0480 */ 203 __IO uint32_t RECEIVE_Q2_PTR; /* 0x0484 */ 204 __IO uint32_t RECEIVE_Q3_PTR; /* 0x0488 */ 205 uint32_t reserved14[5]; /* 0x048C - 0x049C */ 206 __IO uint32_t DMA_RXBUF_SIZE_Q1; /* 0x04A0 */ 207 __IO uint32_t DMA_RXBUF_SIZE_Q2; /* 0x04A4 */ 208 __IO uint32_t DMA_RXBUF_SIZE_Q3; /* 0x04A8 */ 209 uint32_t reserved15[4]; /* 0x04AC - 0x04B8 */ 210 __IO uint32_t CBS_CONTROL; /* 0x04BC */ 211 __IO uint32_t CBS_IDLESLOPE_Q_A; /* 0x04C0 */ 212 __IO uint32_t CBS_IDLESLOPE_Q_B; /* 0x04C4 */ 213 __IO uint32_t UPPER_TX_Q_BASE_ADDR; /* 0x04C8 */ 214 __IO uint32_t TX_BD_CONTROL; /* 0x04CC */ 215 __IO uint32_t RX_BD_CONTROL; /* 0x04D0 */ 216 __IO uint32_t UPPER_RX_Q_BASE_ADDR; /* 0x04D4 */ 217 uint32_t reserved16[5]; /* 0x04D8 - 0x04E8 */ 218 __IO uint32_t WD_COUNTER; /* 0x04EC */ 219 uint32_t reserved17[2]; /* 0x04F0 - 0x04F4 */ 220 __IO uint32_t AXI_TX_FULL_THRESH0; /* 0x04F8 */ 221 __IO uint32_t AXI_TX_FULL_THRESH1; /* 0x04FC */ 222 __IO uint32_t SCREENING_TYPE_1_REGISTER_0; /* 0x0500 */ 223 __IO uint32_t SCREENING_TYPE_1_REGISTER_1; /* 0x0504 */ 224 __IO uint32_t SCREENING_TYPE_1_REGISTER_2; /* 0x0508 */ 225 __IO uint32_t SCREENING_TYPE_1_REGISTER_3; /* 0x050C */ 226 uint32_t reserved18[12]; /* 0x0510 - 0x053C */ 227 __IO uint32_t SCREENING_TYPE_2_REGISTER_0; /* 0x0540 */ 228 __IO uint32_t SCREENING_TYPE_2_REGISTER_1; /* 0x0544 */ 229 __IO uint32_t SCREENING_TYPE_2_REGISTER_2; /* 0x0548 */ 230 __IO uint32_t SCREENING_TYPE_2_REGISTER_3; /* 0x054C */ 231 uint32_t reserved18b[12]; /* 0x0550 - 0x057C */ 232 __IO uint32_t TX_SCHED_CTRL; /* 0x0580 */ 233 uint32_t reserved19[3]; /* 0x0584 - 0x058C */ 234 __IO uint32_t BW_RATE_LIMIT_Q0TO3; /* 0x0590 */ 235 uint32_t reserved20[3]; /* 0x0594 - 0x059C */ 236 __IO uint32_t TX_Q_SEG_ALLOC_Q0TO3; /* 0x05A0 */ 237 uint32_t reserved21[23]; /* 0x05A4 - 0x05FC */ 238 __IO uint32_t INT_Q1_ENABLE; /* 0x0600 */ 239 __IO uint32_t INT_Q2_ENABLE; /* 0x0604 */ 240 __IO uint32_t INT_Q3_ENABLE; /* 0x0608 */ 241 uint32_t reserved22[5]; /* 0x060C - 0x061C */ 242 __IO uint32_t INT_Q1_DISABLE; /* 0x0620 */ 243 __IO uint32_t INT_Q2_DISABLE; /* 0x0624 */ 244 __IO uint32_t INT_Q3_DISABLE; /* 0x0628 */ 245 uint32_t reserved23[5]; /* 0x062C - 0x063C */ 246 __IO uint32_t INT_Q1_MASK; /* 0x0640 */ 247 __IO uint32_t INT_Q2_MASK; /* 0x0644 */ 248 __IO uint32_t INT_Q3_MASK; /* 0x0648 */ 249 uint32_t reserved24[37]; /* 0x064C - 0x06DC */ 250 __IO uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_0; /* 0x06E0 */ 251 __IO uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_1; /* 0x06E4 */ 252 __IO uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_2; /* 0x06E8 */ 253 __IO uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_3; /* 0x06EC */ 254 uint32_t reserved25[4]; /* 0x06F0 - 0x06FC */ 255 __IO uint32_t TYPE2_COMPARE_0_WORD_0; /* 0x0700 */ 256 __IO uint32_t TYPE2_COMPARE_0_WORD_1; /* 0x0704 */ 257 __IO uint32_t TYPE2_COMPARE_1_WORD_0; /* 0x0708 */ 258 __IO uint32_t TYPE2_COMPARE_1_WORD_1; /* 0x070C */ 259 __IO uint32_t TYPE2_COMPARE_2_WORD_0; /* 0x0710 */ 260 __IO uint32_t TYPE2_COMPARE_2_WORD_1; /* 0x0714 */ 261 __IO uint32_t TYPE2_COMPARE_3_WORD_0; /* 0x0718 */ 262 __IO uint32_t TYPE2_COMPARE_3_WORD_1; /* 0x071C */ 263 uint32_t reserved26[56]; /* 0x0720 - 0x07FC */ 264 __IO uint32_t ENST_START_TIME_Q0; /* 0x0800 */ 265 __IO uint32_t ENST_START_TIME_Q1; /* 0x0804 */ 266 __IO uint32_t ENST_START_TIME_Q2; /* 0x0808 */ 267 __IO uint32_t ENST_START_TIME_Q3; /* 0x080C */ 268 uint32_t reserved27[4]; /* 0x0810 - 0x081C */ 269 __IO uint32_t ENST_ON_TIME_Q0; /* 0x0820 */ 270 __IO uint32_t ENST_ON_TIME_Q1; /* 0x0824 */ 271 __IO uint32_t ENST_ON_TIME_Q2; /* 0x0828 */ 272 __IO uint32_t ENST_ON_TIME_Q3; /* 0x082C */ 273 uint32_t reserved28[4]; /* 0x0830 - 0x083C */ 274 __IO uint32_t ENST_OFF_TIME_Q0; /* 0x0840 */ 275 __IO uint32_t ENST_OFF_TIME_Q1; /* 0x0844 */ 276 __IO uint32_t ENST_OFF_TIME_Q2; /* 0x0848 */ 277 __IO uint32_t ENST_OFF_TIME_Q3; /* 0x084C */ 278 __IO uint32_t ENST_CONTROL; /* 0x0850 */ 279 uint32_t reserved29[427]; /* 0x0854 - 0x0EFC */ 280 __IO uint32_t MMSL_CONTROL; /* 0x0F00 */ 281 __IO uint32_t MMSL_STATUS; /* 0x0F04 */ 282 __IO uint32_t MMSL_ERR_STATS; /* 0x0F08 */ 283 __IO uint32_t MMSL_ASS_OK_COUNT; /* 0x0F0C */ 284 __IO uint32_t MMSL_FRAG_COUNT_RX; /* 0x0F10 */ 285 __IO uint32_t MMSL_FRAG_COUNT_TX; /* 0x0F14 */ 286 __IO uint32_t MMSL_INT_STATUS; /* 0x0F18 */ 287 __IO uint32_t MMSL_INT_ENABLE; /* 0x0F1C */ 288 __IO uint32_t MMSL_INT_DISABLE; /* 0x0F20 */ 289 __IO uint32_t MMSL_INT_MASK; /* 0x0F24 */ 290 uint32_t reserved30[54]; /* 0x0F28 - 0x0FFC */ 291 } MAC_TypeDef; 292 293 typedef struct 294 { 295 __IO uint32_t NETWORK_CONTROL; /* 0x1000 */ 296 __IO uint32_t NETWORK_CONFIG; /* 0x1004 */ 297 __IO uint32_t NETWORK_STATUS; /* 0x1008 */ 298 uint32_t reserved31; /* 0x100C */ 299 __IO uint32_t DMA_CONFIG; /* 0x1010 */ 300 __IO uint32_t TRANSMIT_STATUS; /* 0x1014 */ 301 __IO uint32_t RECEIVE_Q_PTR; /* 0x1018 */ 302 __IO uint32_t TRANSMIT_Q_PTR; /* 0x101C */ 303 __IO uint32_t RECEIVE_STATUS; /* 0x1020 */ 304 __IO uint32_t INT_STATUS; /* 0x1024 */ 305 __IO uint32_t INT_ENABLE; /* 0x1028 */ 306 __IO uint32_t INT_DISABLE; /* 0x102C */ 307 __IO uint32_t INT_MASK; /* 0x1030 */ 308 __IO uint32_t PHY_MANAGEMENT; /* 0x1034 */ 309 __IO uint32_t PAUSE_TIME; /* 0x1038 */ 310 __IO uint32_t TX_PAUSE_QUANTUM; /* 0x103C */ 311 __IO uint32_t PBUF_TXCUTTHRU; /* 0x1040 */ 312 __IO uint32_t PBUF_RXCUTTHRU; /* 0x1044 */ 313 __IO uint32_t JUMBO_MAX_LENGTH; /* 0x1048 */ 314 uint32_t reserved32[2]; /* 0x104C - 0x1050 */ 315 __IO uint32_t AXI_MAX_PIPELINE; /* 0x1054 */ 316 uint32_t reserved33; /* 0x1058 */ 317 __IO uint32_t INT_MODERATION; /* 0x105C */ 318 __IO uint32_t SYS_WAKE_TIME; /* 0x1060 */ 319 __IO uint32_t FATAL_OR_NON_FATAL_INT_SEL; /* 0x1064 */ 320 __IO uint32_t LOCKUP_CONFIG; /* 0x1068 */ 321 __IO uint32_t RX_MAC_LOCKUP_TIME; /* 0x106C */ 322 uint32_t reserved34[4]; /* 0x1070 - 0x107C */ 323 __IO uint32_t HASH_BOTTOM; /* 0x1080 */ 324 __IO uint32_t HASH_TOP; /* 0x1084 */ 325 __IO uint32_t SPEC_ADD1_BOTTOM; /* 0x1088 */ 326 __IO uint32_t SPEC_ADD1_TOP; /* 0x108C */ 327 __IO uint32_t SPEC_ADD2_BOTTOM; /* 0x1090 */ 328 __IO uint32_t SPEC_ADD2_TOP; /* 0x1094 */ 329 __IO uint32_t SPEC_ADD3_BOTTOM; /* 0x1098 */ 330 __IO uint32_t SPEC_ADD3_TOP; /* 0x109C */ 331 __IO uint32_t SPEC_ADD4_BOTTOM; /* 0x10A0 */ 332 __IO uint32_t SPEC_ADD4_TOP; /* 0x10A4 */ 333 __IO uint32_t SPEC_TYPE1; /* 0x10A8 */ 334 __IO uint32_t SPEC_TYPE2; /* 0x10AC */ 335 __IO uint32_t SPEC_TYPE3; /* 0x10B0 */ 336 __IO uint32_t SPEC_TYPE4; /* 0x10B4 */ 337 __IO uint32_t WOL_REGISTER; /* 0x10B8 */ 338 __IO uint32_t STRETCH_RATIO; /* 0x10BC */ 339 __IO uint32_t STACKED_VLAN; /* 0x10C0 */ 340 __IO uint32_t TX_PFC_PAUSE; /* 0x10C4 */ 341 __IO uint32_t MASK_ADD1_BOTTOM; /* 0x10C8 */ 342 __IO uint32_t MASK_ADD1_TOP; /* 0x10CC */ 343 __IO uint32_t DMA_ADDR_OR_MASK; /* 0x10D0 */ 344 __IO uint32_t RX_PTP_UNICAST; /* 0x10D4 */ 345 __IO uint32_t TX_PTP_UNICAST; /* 0x10D8 */ 346 __IO uint32_t TSU_NSEC_CMP; /* 0x10DC */ 347 __IO uint32_t TSU_SEC_CMP; /* 0x10E0 */ 348 __IO uint32_t TSU_MSB_SEC_CMP; /* 0x10E4 */ 349 __IO uint32_t TSU_PTP_TX_MSB_SEC; /* 0x10E8 */ 350 __IO uint32_t TSU_PTP_RX_MSB_SEC; /* 0x10EC */ 351 __IO uint32_t TSU_PEER_TX_MSB_SEC; /* 0x10F0 */ 352 __IO uint32_t TSU_PEER_RX_MSB_SEC; /* 0x10F4 */ 353 __IO uint32_t DPRAM_FILL_DBG; /* 0x10F8 */ 354 __IO uint32_t REVISION_REG; /* 0x10FC */ 355 __IO uint32_t OCTETS_TXED_BOTTOM; /* 0x1100 */ 356 __IO uint32_t OCTETS_TXED_TOP; /* 0x1104 */ 357 __IO uint32_t FRAMES_TXED_OK; /* 0x1108 */ 358 __IO uint32_t BROADCAST_TXED; /* 0x110C */ 359 __IO uint32_t MULTICAST_TXED; /* 0x1110 */ 360 __IO uint32_t PAUSE_FRAMES_TXED; /* 0x1114 */ 361 __IO uint32_t FRAMES_TXED_64; /* 0x1118 */ 362 __IO uint32_t FRAMES_TXED_65; /* 0x111C */ 363 __IO uint32_t FRAMES_TXED_128; /* 0x1120 */ 364 __IO uint32_t FRAMES_TXED_256; /* 0x1124 */ 365 __IO uint32_t FRAMES_TXED_512; /* 0x1128 */ 366 __IO uint32_t FRAMES_TXED_1024; /* 0x112C */ 367 __IO uint32_t FRAMES_TXED_1519; /* 0x1130 */ 368 __IO uint32_t TX_UNDERRUNS; /* 0x1134 */ 369 __IO uint32_t SINGLE_COLLISIONS; /* 0x1138 */ 370 __IO uint32_t MULTIPLE_COLLISIONS; /* 0x113C */ 371 __IO uint32_t EXCESSIVE_COLLISIONS; /* 0x1140 */ 372 __IO uint32_t LATE_COLLISIONS; /* 0x1144 */ 373 __IO uint32_t DEFERRED_FRAMES; /* 0x1148 */ 374 __IO uint32_t CRS_ERRORS; /* 0x114C */ 375 __IO uint32_t OCTETS_RXED_BOTTOM; /* 0x1150 */ 376 __IO uint32_t OCTETS_RXED_TOP; /* 0x1154 */ 377 __IO uint32_t FRAMES_RXED_OK; /* 0x1158 */ 378 __IO uint32_t BROADCAST_RXED; /* 0x115C */ 379 __IO uint32_t MULTICAST_RXED; /* 0x1160 */ 380 __IO uint32_t PAUSE_FRAMES_RXED; /* 0x1164 */ 381 __IO uint32_t FRAMES_RXED_64; /* 0x1168 */ 382 __IO uint32_t FRAMES_RXED_65; /* 0x116C */ 383 __IO uint32_t FRAMES_RXED_128; /* 0x1170 */ 384 __IO uint32_t FRAMES_RXED_256; /* 0x1174 */ 385 __IO uint32_t FRAMES_RXED_512; /* 0x1178 */ 386 __IO uint32_t FRAMES_RXED_1024; /* 0x117C */ 387 __IO uint32_t FRAMES_RXED_1519; /* 0x1180 */ 388 __IO uint32_t UNDERSIZE_FRAMES; /* 0x1184 */ 389 __IO uint32_t EXCESSIVE_RX_LENGTH; /* 0x1188 */ 390 __IO uint32_t RX_JABBERS; /* 0x118C */ 391 __IO uint32_t FCS_ERRORS; /* 0x1190 */ 392 __IO uint32_t RX_LENGTH_ERRORS; /* 0x1194 */ 393 __IO uint32_t RX_SYMBOL_ERRORS; /* 0x1198 */ 394 __IO uint32_t ALIGNMENT_ERRORS; /* 0x119C */ 395 __IO uint32_t RX_RESOURCE_ERRORS; /* 0x11A0 */ 396 __IO uint32_t RX_OVERRUNS; /* 0x11A4 */ 397 __IO uint32_t RX_IP_CK_ERRORS; /* 0x11A8 */ 398 __IO uint32_t RX_TCP_CK_ERRORS; /* 0x11AC */ 399 __IO uint32_t RX_UDP_CK_ERRORS; /* 0x11B0 */ 400 __IO uint32_t AUTO_FLUSHED_PKTS; /* 0x11B4 */ 401 uint32_t reserved35; /* 0x10B8 */ 402 __IO uint32_t TSU_TIMER_INCR_SUB_NSEC; /* 0x11BC */ 403 __IO uint32_t TSU_TIMER_MSB_SEC; /* 0x11C0 */ 404 __IO uint32_t TSU_STROBE_MSB_SEC; /* 0x11C4 */ 405 __IO uint32_t TSU_STROBE_SEC; /* 0x11C8 */ 406 __IO uint32_t TSU_STROBE_NSEC; /* 0x11CC */ 407 __IO uint32_t TSU_TIMER_SEC; /* 0x11D0 */ 408 __IO uint32_t TSU_TIMER_NSEC; /* 0x11D4 */ 409 __IO uint32_t TSU_TIMER_ADJUST; /* 0x11D8 */ 410 __IO uint32_t TSU_TIMER_INCR; /* 0x11DC */ 411 __IO uint32_t TSU_PTP_TX_SEC; /* 0x11E0 */ 412 __IO uint32_t TSU_PTP_TX_NSEC; /* 0x11E4 */ 413 __IO uint32_t TSU_PTP_RX_SEC; /* 0x11E8 */ 414 __IO uint32_t TSU_PTP_RX_NSEC; /* 0x11EC */ 415 __IO uint32_t TSU_PEER_TX_SEC; /* 0x11F0 */ 416 __IO uint32_t TSU_PEER_TX_NSEC; /* 0x11F4 */ 417 __IO uint32_t TSU_PEER_RX_SEC; /* 0x11F8 */ 418 __IO uint32_t TSU_PEER_RX_NSEC; /* 0x11FC */ 419 uint32_t reserved36[24]; /* 0x1200 - 0x125C */ 420 __IO uint32_t TX_PAUSE_QUANTUM1; /* 0x1260 */ 421 __IO uint32_t TX_PAUSE_QUANTUM2; /* 0x1264 */ 422 __IO uint32_t TX_PAUSE_QUANTUM3; /* 0x1268 */ 423 __IO uint32_t PFC_STATUS; /* 0x126C */ 424 __IO uint32_t RX_LPI; /* 0x1270 */ 425 __IO uint32_t RX_LPI_TIME; /* 0x1274 */ 426 __IO uint32_t TX_LPI; /* 0x1278 */ 427 __IO uint32_t TX_LPI_TIME; /* 0x127C */ 428 __IO uint32_t DESIGNCFG_DEBUG1; /* 0x1280 */ 429 __IO uint32_t DESIGNCFG_DEBUG2; /* 0x1284 */ 430 __IO uint32_t DESIGNCFG_DEBUG3; /* 0x1288 */ 431 __IO uint32_t DESIGNCFG_DEBUG4; /* 0x128C */ 432 __IO uint32_t DESIGNCFG_DEBUG5; /* 0x1290 */ 433 __IO uint32_t DESIGNCFG_DEBUG6; /* 0x1294 */ 434 __IO uint32_t DESIGNCFG_DEBUG7; /* 0x1298 */ 435 __IO uint32_t DESIGNCFG_DEBUG8; /* 0x129C */ 436 __IO uint32_t DESIGNCFG_DEBUG9; /* 0x12A0 */ 437 __IO uint32_t DESIGNCFG_DEBUG10; /* 0x12A4 */ 438 __IO uint32_t DESIGNCFG_DEBUG11; /* 0x12A8 */ 439 __IO uint32_t DESIGNCFG_DEBUG12; /* 0x12AC */ 440 uint32_t reserved37[12]; /* 0x12B0 - 0x12DC */ 441 __IO uint32_t AXI_QoS_CFG_0; /* 0X12E0 */ 442 uint32_t reserved37a[118]; /* 0x12E4 - 0x14B8 */ 443 __IO uint32_t CBS_CONTROL; /* 0x14BC */ 444 __IO uint32_t CBS_IDLESLOPE_Q_A; /* 0x14C0 */ 445 __IO uint32_t CBS_IDLESLOPE_Q_B; /* 0x14C4 */ 446 __IO uint32_t UPPER_TX_Q_BASE_ADDR; /* 0x14C8 */ 447 __IO uint32_t TX_BD_CONTROL; /* 0x14CC */ 448 __IO uint32_t RX_BD_CONTROL; /* 0x14D0 */ 449 __IO uint32_t UPPER_RX_Q_BASE_ADDR; /* 0x14D4 */ 450 uint32_t reserved38[10]; /* 0x14D8 - 0x14FC */ 451 __IO uint32_t SCREENING_TYPE_1_REGISTER_0; /* 0x1500 - TBD PMCS Remove this and look for other possible additional registers near end of eMAC that we might be missing... */ 452 uint32_t reserved39[15]; /* 0x1504 - 0x153C */ 453 __IO uint32_t SCREENING_TYPE_2_REGISTER_0; /* 0x1540 */ 454 __IO uint32_t SCREENING_TYPE_2_REGISTER_1; /* 0x1544 */ 455 uint32_t reserved40[110]; /* 0x1548 - 0x16FC */ 456 __IO uint32_t TYPE2_COMPARE_0_WORD_0; /* 0x1700 */ 457 __IO uint32_t TYPE2_COMPARE_0_WORD_1; /* 0x1704 */ 458 __IO uint32_t TYPE2_COMPARE_1_WORD_0; /* 0x1708 */ 459 __IO uint32_t TYPE2_COMPARE_1_WORD_1; /* 0x170C */ 460 __IO uint32_t TYPE2_COMPARE_2_WORD_0; /* 0x1710 */ 461 __IO uint32_t TYPE2_COMPARE_2_WORD_1; /* 0x1714 */ 462 __IO uint32_t TYPE2_COMPARE_3_WORD_0; /* 0x1718 */ 463 __IO uint32_t TYPE2_COMPARE_3_WORD_1; /* 0x171C */ 464 __IO uint32_t TYPE2_COMPARE_4_WORD_0; /* 0x1720 */ 465 __IO uint32_t TYPE2_COMPARE_4_WORD_1; /* 0x1724 */ 466 __IO uint32_t TYPE2_COMPARE_5_WORD_0; /* 0x1728 */ 467 __IO uint32_t TYPE2_COMPARE_5_WORD_1; /* 0x172C */ 468 uint32_t reserved41[52]; /* 0x1730 - 0x17FC */ 469 __IO uint32_t ENST_START_TIME; /* 0x1800 */ 470 uint32_t reserved42[7]; /* 0x1804 - 0x181C */ 471 __IO uint32_t ENST_ON_TIME; /* 0x1820 */ 472 uint32_t reserved43[7]; /* 0x1824 - 0x183C */ 473 __IO uint32_t ENST_OFF_TIME; /* 0x1840 */ 474 uint32_t reserved44[15]; /* 0x1844 - 0x187C */ 475 __IO uint32_t ENST_CONTROL; /* 0x1820 */ 476 } eMAC_TypeDef; 477 478 #ifdef __cplusplus 479 } 480 #endif 481 482 #endif /* MSS_ETHERNET_MAC_REGISTERS_H_ */ 483
