Searched refs:CONTROL (Results 1 – 11 of 11) sorted by relevance
183 this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK; in MSS_SPI_init()212 this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_MASTER_MASK; in MSS_SPI_configure_slave_mode()215 this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK; in MSS_SPI_configure_slave_mode()216 this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~PROTOCOL_MODE_MASK) in MSS_SPI_configure_slave_mode()221 this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) in MSS_SPI_configure_slave_mode()225 this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK; in MSS_SPI_configure_slave_mode()265 this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK; in MSS_SPI_configure_master_mode()266 this_spi->hw_reg->CONTROL |= CTRL_MASTER_MASK; in MSS_SPI_configure_master_mode()267 this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK; in MSS_SPI_configure_master_mode()322 ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) in MSS_SPI_set_slave_select()[all …]
233 volatile uint32_t CONTROL; member
36 QSPI->CONTROL = CTRL_EN_MASK | in MSS_QSPI_init()51 QSPI->CONTROL = (uint32_t)(config->sample << CTRL_SAMPLE) | in MSS_QSPI_configure()70 reg = QSPI->CONTROL; in MSS_QSPI_get_config()121 skips |= (((QSPI->CONTROL & CTRL_QMODE12_MASK)? 1u:0u) << FRMS_QSPI); in MSS_QSPI_polled_transfer_block()127 QSPI->CONTROL |= CTRL_FLAGSX4_MASK; in MSS_QSPI_polled_transfer_block()138 QSPI->CONTROL &= ~CTRL_FLAGSX4_MASK; in MSS_QSPI_polled_transfer_block()154 QSPI->CONTROL |= CTRL_FLAGSX4_MASK; in MSS_QSPI_polled_transfer_block()162 QSPI->CONTROL &= ~CTRL_FLAGSX4_MASK; in MSS_QSPI_polled_transfer_block()223 skips |= (((QSPI->CONTROL & CTRL_QMODE12_MASK)? 1u:0u) << FRMS_QSPI); in MSS_QSPI_irq_transfer_block()229 QSPI->CONTROL |= CTRL_FLAGSX4_MASK; in MSS_QSPI_irq_transfer_block()[all …]
368 volatile uint32_t CONTROL; member443 QSPI->CONTROL |= CTRL_EN_MASK; in MSS_QSPI_enable()461 QSPI->CONTROL &= ~CTRL_EN_MASK; in MSS_QSPI_disable()
281 volatile uint32_t CONTROL; member556 wdog_hw_base[wd_num]->CONTROL |= MSS_WDOG_INTEN_MVRP_MASK; in MSS_WD_enable_mvrp_irq()585 wdog_hw_base[wd_num]->CONTROL &= ~(MSS_WDOG_INTEN_MVRP_MASK); in MSS_WD_disable_mvrp_irq()
72 wdog_hw_base[wd_num]->CONTROL = (uint32_t)(config->forbidden_en << in MSS_WD_configure()102 config->forbidden_en = (uint8_t)((wdog_hw_base[wd_num]->CONTROL & in MSS_WD_get_config()
162 __IOM uint32_t CONTROL; /*!< (@ 0x0000) TACH Control b[31:0] */ member
156 __IOM uint8_t CONTROL; /*! (@ 0x0010) RTC Control */ member
195 __IOM uint8_t CONTROL; /*!< (@ 0x0008) PECI Control */ member
188 __IOM uint32_t CONTROL; /*!< (@ 0x0000) ADC Control */ member
795 …__IO uint32_t CONTROL; /*!< (@ 0x40002450) DMA Channel N Control … member1011 …__IO uint32_t CONTROL; /*!< (@ 0x40002490) DMA Channel N Control … member1201 …__IO uint32_t CONTROL; /*!< (@ 0x400024D0) DMA Channel N Control … member7750 …__IO uint8_t CONTROL; /*!< (@ 0x400F0508) Keyboard Control Register … member24487 …__IO uint32_t CONTROL; /*!< (@ 0x40000C10) Timer Control Register … member25032 …__IO uint32_t CONTROL; /*!< (@ 0x400F5010) RTC Control Register … member25459 …__IO uint8_t CONTROL; /*!< (@ 0x40006408) Control Register … member25592 …__IO uint32_t CONTROL; /*!< (@ 0x40007C00) The ADC Control Register is us… member26015 __IO uint32_t CONTROL : 2; /*!< [0..1] CONTROL 3=PWM is always on member26309 …__O uint32_t CONTROL; /*!< (@ 0x40004000) Control Register … member[all …]
