1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file timer.h 28 *MEC1501 Timer definitions 29 */ 30 /** @defgroup MEC1501 Peripherals Timers 31 */ 32 33 #ifndef _TIMER_H 34 #define _TIMER_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* 42 * Basic timers base address 43 * Offset between each timer block 44 */ 45 #define MCHP_B16TMR_BASE 0x40000c00u 46 #define MCHP_B16TMR_MAX_INSTANCE 2u 47 #define MCHP_B32TMR_BASE 0x40000c80u 48 #define MCHP_B32TMR_MAX_INSTANCE 2u 49 50 /* 51 * Offset between instances of the Basic Timer blocks 52 */ 53 #define MCHP_BTMR_INSTANCE_POS 5u 54 #define MCHP_BTMR_INSTANCE_OFS (1u << (MCHP_BTMR_INSTANCE_POS)) 55 56 /* 0 <= n < MCHP_B16TMR_MAX_INSTANCE */ 57 #define MCHP_B16TMR_ADDR(n) \ 58 (MCHP_B16TMR_BASE + ((uint32_t)(n) << MCHP_BTMR_INSTANCE_POS)) 59 60 #define MCHP_B16TMR0_ADDR 0x40000c00u 61 #define MCHP_B16TMR1_ADDR 0x40000c20u 62 63 /* 0 <= n < MCHP_B32TMR_MAX_INSTANCE */ 64 #define MCHP_B32TMR_ADDR(n) \ 65 (MCHP_B32TMR_BASE + ((uint32_t)(n) << MCHP_BTMR_INSTANCE_POS)) 66 67 #define MCHP_B32TMR0_ADDR 0x40000c80u 68 #define MCHP_B32TMR1_ADDR 0x40000ca0u 69 70 /* 71 * Basic Timer Count Register (Offset +00h) 72 * 32-bit R/W 73 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0 74 */ 75 #define MCHP_BTMR_CNT_OFS 0x00u 76 77 /* 78 * Basic Timer Preload Register (Offset +04h) 79 * 32-bit R/W 80 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0 81 */ 82 #define MCHP_BTMR_PRELOAD_OFS 0x04 83 84 /* 85 * Basic Timer Status Register (Offset +08h) 86 * R/W1C 87 */ 88 #define MCHP_BTMR_STS_OFS 0x08u 89 #define MCHP_BTMR_STS_MASK 0x01u 90 #define MCHP_BTMR_STS_ACTIVE_POS 0u 91 #define MCHP_BTMR_STS_ACTIVE 0x01u 92 93 /* 94 * Basic Timer Interrupt Enable Register (Offset +0Ch) 95 */ 96 #define MCHP_BTMR_INTEN_OFS 0x0cu 97 #define MCHP_BTMR_INTEN_MASK 0x01u 98 #define MCHP_BTMR_INTEN_POS 0u 99 #define MCHP_BTMR_INTEN 0x01u 100 #define MCHP_BTMR_INTDIS 0u 101 102 /* 103 * Basic Timer Control Register (Offset +10h) 104 */ 105 #define MCHP_BTMR_CTRL_OFS 0x10u 106 #define MCHP_BTMR_CTRL_MASK 0xffff00fdu 107 108 #define MCHP_BTMR_CTRL_PRESCALE_POS 16u 109 #define MCHP_BTMR_CTRL_PRESCALE_MASK0 0xffffu 110 #define MCHP_BTMR_CTRL_PRESCALE_MASK 0xffff0000u 111 112 #define MCHP_BTMR_CTRL_HALT 0x80u 113 #define MCHP_BTMR_CTRL_RELOAD 0x40u 114 #define MCHP_BTMR_CTRL_START 0x20u 115 #define MCHP_BTMR_CTRL_SOFT_RESET 0x10u 116 #define MCHP_BTMR_CTRL_AUTO_RESTART 0x08u 117 #define MCHP_BTMR_CTRL_COUNT_UP 0x04u 118 #define MCHP_BTMR_CTRL_ENABLE 0x01u 119 /* */ 120 #define MCHP_BTMR_CTRL_HALT_POS 7u 121 #define MCHP_BTMR_CTRL_RELOAD_POS 6u 122 #define MCHP_BTMR_CTRL_START_POS 5u 123 #define MCHP_BTMR_CTRL_SRESET_POS 4u 124 #define MCHP_BTMR_CTRL_AUTO_RESTART_POS 3u 125 #define MCHP_BTMR_CTRL_COUNT_DIR_POS 2u 126 #define MCHP_BTMR_CTRL_ENABLE_POS 0u 127 128 /* Basic Timer interrupt routing */ 129 #define MCHP_B16TMR0_GIRQ 23u 130 #define MCHP_B16TMR1_GIRQ 23u 131 #define MCHP_B32TMR0_GIRQ 23u 132 #define MCHP_B32TMR1_GIRQ 23u 133 134 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 135 #define MCHP_B16TMR0_GIRQ_POS 0u 136 #define MCHP_B16TMR1_GIRQ_POS 1u 137 #define MCHP_B32TMR0_GIRQ_POS 4u 138 #define MCHP_B32TMR1_GIRQ_POS 5u 139 140 #define MCHP_B16TMR0_GIRQ_VAL (1u << 0) 141 #define MCHP_B16TMR1_GIRQ_VAL (1u << 1) 142 #define MCHP_B32TMR0_GIRQ_VAL (1u << 4) 143 #define MCHP_B32TMR1_GIRQ_VAL (1u << 5) 144 145 /* Basic timer GIRQ aggregated NVIC input */ 146 #define MCHP_B16TMR0_NVIC_AGGR 14u 147 #define MCHP_B16TMR1_NVIC_AGGR 14u 148 #define MCHP_B32TMR0_NVIC_AGGR 14u 149 #define MCHP_B32TMR1_NVIC_AGGR 14u 150 151 /* Basic timer direct NVIC inputs */ 152 #define MCHP_B16TMR0_NVIC_DIRECT 136u 153 #define MCHP_B16TMR1_NVIC_DIRECT 137u 154 #define MCHP_B32TMR0_NVIC_DIRECT 140u 155 #define MCHP_B32TMR1_NVIC_DIRECT 141u 156 157 /* =========================================================================*/ 158 /* ================ 32/16-bit Basic Timer ================ */ 159 /* =========================================================================*/ 160 161 /** 162 * @brief 32-bit and 16-bit Basic Timer (BTMR) 163 * @note Basic timers 0 & 1 are 16-bit, 2 & 3 are 32-bit. 164 */ 165 typedef struct btmr_regs 166 { 167 __IOM uint32_t CNT; /*!< (@ 0x00000000) BTMR Count */ 168 __IOM uint32_t PRLD; /*!< (@ 0x00000004) BTMR Preload */ 169 __IOM uint8_t STS; /*!< (@ 0x00000008) BTMR Status */ 170 uint8_t RSVDC[3]; 171 __IOM uint8_t IEN; /*!< (@ 0x0000000c) BTMR Interrupt Enable */ 172 uint8_t RSVDD[3]; 173 __IOM uint32_t CTRL; /*!< (@ 0x00000010) BTMR Control */ 174 } BTMR_Type; 175 176 /* =========================================================================*/ 177 /* ================ HTMR ================ */ 178 /* =========================================================================*/ 179 180 #define MCHP_HTMR_BASE_ADDR 0x40009800u 181 #define MCHP_HTMR_MAX_INSTANCES 2u 182 #define MCHP_HTMR_SPACING 0x20u 183 #define MCHP_HTMR_SPACING_PWROF2 5u 184 185 #define MCHP_HTMR_ADDR(n) \ 186 (MCHP_HTMR_BASE_ADDR + ((uint32_t)(n) << MCHP_HTMR_SPACING_PWROF2)) 187 188 #define MCHP_HTMR0_ADDR 0x40009800u 189 #define MCHP_HTMR1_ADDR 0x40009820u 190 191 /* 192 * Set count resolution in bit[0] 193 * 0 = 30.5 us (32786 Hz) 194 * 1 = 125 ms (8 Hz) 195 */ 196 #define MCHP_HTMR_CTRL_REG_MASK 0x01u 197 #define MCHP_HTMR_CTRL_RESOL_POS 0u 198 #define MCHP_HTMR_CTRL_RESOL_MASK (1u << (MCHP_HTMR_CTRL_EN_POS)) 199 #define MCHP_HTMR_CTRL_RESOL_30US (0u << (MCHP_HTMR_CTRL_EN_POS)) 200 #define MCHP_HTMR_CTRL_RESOL_125MS (1u << (MCHP_HTMR_CTRL_EN_POS)) 201 202 /* 203 * Hibernation timer is started and stopped by writing a value 204 * to the CNT (count) register. 205 * Writing a non-zero value resets and start the counter counting down. 206 * Writing 0 stops the timer. 207 */ 208 #define MCHP_HTMR_CNT_STOP_VALUE 0u 209 210 /* Hibernation timer interrupt routing */ 211 #define MCHP_HTMR0_GIRQ 23u 212 #define MCHP_HTMR1_GIRQ 23u 213 214 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 215 #define MCHP_HTMR0_GIRQ_POS 16u 216 #define MCHP_HTMR1_GIRQ_POS 17u 217 218 #define MCHP_HTMR0_GIRQ_VAL (1u << 16) 219 #define MCHP_HTMR1_GIRQ_VAL (1u << 17) 220 221 /* Hibernation timer GIRQ aggregated NVIC input */ 222 #define MCHP_HTMR0_NVIC_AGGR 14u 223 #define MCHP_GTMR1_NVIC_AGGR 14u 224 225 /* Hibernation timer direct NVIC inputs */ 226 #define MCHP_HTMR0_NVIC_DIRECT 112u 227 #define MCHP_HTMR1_NVIC_DIRECT 113u 228 229 /** 230 * @brief Hibernation Timer (HTMR) 231 */ 232 typedef struct htmr_regs 233 { /*!< (@ 0x40009800) HTMR Structure */ 234 __IOM uint16_t PRLD; /*!< (@ 0x00000000) HTMR Preload */ 235 uint8_t RSVD1[2]; 236 __IOM uint16_t CTRL; /*!< (@ 0x00000004) HTMR Control */ 237 uint8_t RSVD2[2]; 238 __IM uint16_t CNT; /*!< (@ 0x00000008) HTMR Count (RO) */ 239 uint8_t RSVD3[2]; 240 } HTMR_Type; 241 242 /* =========================================================================*/ 243 /* ================ Capture/Compare Timer ================ */ 244 /* =========================================================================*/ 245 246 #define MCHP_CCT_BASE_ADDR 0x40001000u 247 #define MCHP_CCT_MAX_INSTANCE 1u 248 249 /* Control register at offset 0x00 */ 250 #define MCHP_CCT_CTRL_ACTIVATE (1u << 0) 251 #define MCHP_CCT_CTRL_FRUN_EN (1u << 1) 252 #define MCHP_CCT_CTRL_FRUN_RESET (1u << 2) /* self clearing bit */ 253 #define MCHP_CCT_CTRL_TCLK_MASK0 (0x07u) 254 #define MCHP_CCT_CTRL_TCLK_MASK ((MCHP_CCT_CTRL_TCLK_MASK0) << 4) 255 #define MCHP_CCT_CTRL_TCLK_DIV_1 (0u) 256 #define MCHP_CCT_CTRL_TCLK_DIV_2 (1u << 4) 257 #define MCHP_CCT_CTRL_TCLK_DIV_4 (2u << 4) 258 #define MCHP_CCT_CTRL_TCLK_DIV_8 (3u << 4) 259 #define MCHP_CCT_CTRL_TCLK_DIV_16 (4u << 4) 260 #define MCHP_CCT_CTRL_TCLK_DIV_32 (5u << 4) 261 #define MCHP_CCT_CTRL_TCLK_DIV_64 (6u << 4) 262 #define MCHP_CCT_CTRL_TCLK_DIV_128 (7u << 4) 263 #define MCHP_CCT_CTRL_COMP0_EN (1u << 8) 264 #define MCHP_CCT_CTRL_COMP1_EN (1u << 9) 265 #define MCHP_CCT_CTRL_COMP1_SET (1u << 16) /* R/WS */ 266 #define MCHP_CCT_CTRL_COMP0_SET (1u << 17) /* R/WS */ 267 #define MCHP_CCT_CTRL_COMP1_CLR (1u << 24) /* R/W1C */ 268 #define MCHP_CCT_CTRL_COMP0_CLR (1u << 25) /* R/W1C */ 269 270 271 /* Capture Compare timer interrupt routing */ 272 #define MCHP_CCT_GIRQ 18u 273 274 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 275 #define MCHP_CCT_TMR_GIRQ_POS 20u 276 #define MCHP_CCT_CAP0_GIRQ_POS 21u 277 #define MCHP_CCT_CAP1_GIRQ_POS 22u 278 #define MCHP_CCT_CAP2_GIRQ_POS 23u 279 #define MCHP_CCT_CAP3_GIRQ_POS 24u 280 #define MCHP_CCT_CAP4_GIRQ_POS 25u 281 #define MCHP_CCT_CAP5_GIRQ_POS 26u 282 #define MCHP_CCT_CMP0_GIRQ_POS 27u 283 #define MCHP_CCT_CMP1_GIRQ_POS 28u 284 285 #define MCHP_CCT_TMR_GIRQ_VAL (1u << 20) 286 #define MCHP_CCT_CAP0_GIRQ_VAL (1u << 21) 287 #define MCHP_CCT_CAP1_GIRQ_VAL (1u << 22) 288 #define MCHP_CCT_CAP2_GIRQ_VAL (1u << 23) 289 #define MCHP_CCT_CAP3_GIRQ_VAL (1u << 24) 290 #define MCHP_CCT_CAP4_GIRQ_VAL (1u << 25) 291 #define MCHP_CCT_CAP5_GIRQ_VAL (1u << 26) 292 #define MCHP_CCT_CMP0_GIRQ_VAL (1u << 27) 293 #define MCHP_CCT_CMP1_GIRQ_VAL (1u << 28) 294 #define MCHP_CCT_GIRQ_VAL_ALL 0x1ff00000u 295 296 /* Capture Compare timer GIRQ aggregated NVIC input */ 297 #define MCHP_CCT_NVIC_AGGR 10u 298 299 /* Capture Compare timer direct NVIC inputs */ 300 #define MCHP_CCT_TMR_NVIC_DIRECT 146u 301 #define MCHP_CCT_CAP0_NVIC_DIRECT 147u 302 #define MCHP_CCT_CAP1_NVIC_DIRECT 148u 303 #define MCHP_CCT_CAP2_NVIC_DIRECT 149u 304 #define MCHP_CCT_CAP3_NVIC_DIRECT 150u 305 #define MCHP_CCT_CAP4_NVIC_DIRECT 151u 306 #define MCHP_CCT_CAP5_NVIC_DIRECT 152u 307 #define MCHP_CCT_CMP0_NVIC_DIRECT 153u 308 #define MCHP_CCT_CMP1_NVIC_DIRECT 154u 309 310 /** 311 * @brief Capture/Compare Timer (CCT) 312 */ 313 typedef struct cct_regs 314 { 315 __IOM uint32_t CTRL; /*!< (@ 0x00000000) CCT Control */ 316 __IOM uint32_t CAP0_CTRL; /*!< (@ 0x00000004) CCT Capture 0 Control */ 317 __IOM uint32_t CAP1_CTRL; /*!< (@ 0x00000008) CCT Capture 1 Control */ 318 __IOM uint32_t FREE_RUN; /*!< (@ 0x0000000c) CCT Free run counter */ 319 __IOM uint32_t CAP0; /*!< (@ 0x00000010) CCT Capture 0 */ 320 __IOM uint32_t CAP1; /*!< (@ 0x00000014) CCT Capture 1 */ 321 __IOM uint32_t CAP2; /*!< (@ 0x00000018) CCT Capture 2 */ 322 __IOM uint32_t CAP3; /*!< (@ 0x0000001c) CCT Capture 3 */ 323 __IOM uint32_t CAP4; /*!< (@ 0x00000020) CCT Capture 4 */ 324 __IOM uint32_t CAP5; /*!< (@ 0x00000024) CCT Capture 5 */ 325 __IOM uint32_t COMP0; /*!< (@ 0x00000028) CCT Compare 0 */ 326 __IOM uint32_t COMP1; /*!< (@ 0x0000002c) CCT Compare 1 */ 327 } CCT_Type; 328 329 /* =========================================================================*/ 330 /* ================ RTMR ================ */ 331 /* =========================================================================*/ 332 333 #define MCHP_RTMR_BASE_ADDR 0x40007400u 334 335 #define MCHP_RTMR_FREQ_HZ 32768u 336 337 #define MCHP_RTMR_CTRL_MASK 0x1fu 338 #define MCHP_RTMR_CTRL_BLK_EN_POS 0u 339 #define MCHP_RTMR_CTRL_BLK_EN_MASK (1u << (MCHP_RTMR_CTRL_BLK_EN_POS)) 340 #define MCHP_RTMR_CTRL_BLK_EN (1u << (MCHP_RTMR_CTRL_BLK_EN_POS)) 341 342 #define MCHP_RTMR_CTRL_AUTO_RELOAD_POS 1u 343 #define MCHP_RTMR_CTRL_AUTO_RELOAD_MASK (1u << (MCHP_RTMR_CTRL_AUTO_RELOAD_POS)) 344 #define MCHP_RTMR_CTRL_AUTO_RELOAD (1u << (MCHP_RTMR_CTRL_AUTO_RELOAD_POS)) 345 346 #define MCHP_RTMR_CTRL_START_POS 2u 347 #define MCHP_RTMR_CTRL_START_MASK (1u << (MCHP_RTMR_CTRL_START_POS)) 348 #define MCHP_RTMR_CTRL_START (1u << (MCHP_RTMR_CTRL_START_POS)) 349 350 #define MCHP_RTMR_CTRL_HW_HALT_EN_POS 3u 351 #define MCHP_RTMR_CTRL_HW_HALT_EN_MASK (1u << (MCHP_RTMR_CTRL_HW_HALT_EN_POS)) 352 #define MCHP_RTMR_CTRL_HW_HALT_EN (1u << (MCHP_RTMR_CTRL_HW_HALT_EN_POS)) 353 354 #define MCHP_RTMR_CTRL_FW_HALT_EN_POS 4u 355 #define MCHP_RTMR_CTRL_FW_HALT_EN_MASK (1u << (MCHP_RTMR_CTRL_FW_HALT_EN_POS)) 356 #define MCHP_RTMR_CTRL_FW_HALT_EN (1u << (MCHP_RTMR_CTRL_FW_HALT_EN_POS)) 357 358 /* RTOS timer interrupt routing */ 359 #define MCHP_RTMR_GIRQ 23u 360 361 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 362 #define MCHP_RTMR_GIRQ_POS 10u 363 364 #define MCHP_RTMR_GIRQ_VAL (1u << 10) 365 366 /* RTOS timer GIRQ aggregated NVIC input */ 367 #define MCHP_RTMR_NVIC_AGGR 14u 368 369 /* RTOS timer direct NVIC inputs */ 370 #define MCHP_RTMR_NVIC_DIRECT 111u 371 372 /** 373 * @brief RTOS Timer (RTMR) 374 */ 375 typedef struct rtmr_regs 376 { /*!< (@ 0x40007400) RTMR Structure */ 377 __IOM uint32_t CNT; /*!< (@ 0x00000000) RTMR Counter */ 378 __IOM uint32_t PRLD; /*!< (@ 0x00000004) RTMR Preload */ 379 __IOM uint8_t CTRL; /*!< (@ 0x00000008) RTMR Control */ 380 uint8_t RSVD1[3]; 381 __IOM uint32_t SOFTIRQ; /*!< (@ 0x0000000c) RTMR Soft IRQ */ 382 } RTMR_Type; 383 384 /* =========================================================================*/ 385 /* ================ WKTMR ================ */ 386 /* =========================================================================*/ 387 388 #define MCHP_WKTMR_BASE_ADDR 0x4000ac80u 389 390 #define MCHP_WKTMR_CTRL_MASK 0x41u 391 #define MCHP_WKTMR_CTRL_WT_EN_POS 0u 392 #define MCHP_WKTMR_CTRL_WT_EN_MASK (1u << (MCHP_WKTMR_CTRL_WT_EN_POS)) 393 #define MCHP_WKTMR_CTRL_WT_EN (1u << (MCHP_WKTMR_CTRL_WT_EN_POS)) 394 #define MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS 6u 395 #define MCHP_WKTMR_CTRL_PWRUP_EV_EN_MASK \ 396 (1u << (MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS)) 397 #define MCHP_WKTMR_CTRL_PWRUP_EV_EN \ 398 (1u << (MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS)) 399 400 #define MCHP_WKTMR_ALARM_CNT_MASK 0x0fffffffu 401 #define MCHP_WKTMR_TMR_CMP_MASK 0x0fffffffu 402 #define MCHP_WKTMR_CLK_DIV_MASK 0x7fffu 403 404 #define MCHP_WKTMR_SS_MASK 0x0fu 405 #define MCHP_WKTMR_SS_RATE_DIS 0x00u 406 #define MCHP_WKTMR_SS_RATE_2HZ 0x01u 407 #define MCHP_WKTMR_SS_RATE_4HZ 0x02u 408 #define MCHP_WKTMR_SS_RATE_8HZ 0x03u 409 #define MCHP_WKTMR_SS_RATE_16HZ 0x04u 410 #define MCHP_WKTMR_SS_RATE_32HZ 0x05u 411 #define MCHP_WKTMR_SS_RATE_64HZ 0x06u 412 #define MCHP_WKTMR_SS_RATE_128HZ 0x07u 413 #define MCHP_WKTMR_SS_RATE_256HZ 0x08u 414 #define MCHP_WKTMR_SS_RATE_512HZ 0x09u 415 #define MCHP_WKTMR_SS_RATE_1024HZ 0x0au 416 #define MCHP_WKTMR_SS_RATE_2048HZ 0x0bu 417 #define MCHP_WKTMR_SS_RATE_4096HZ 0x0cu 418 #define MCHP_WKTMR_SS_RATE_8192HZ 0x0du 419 #define MCHP_WKTMR_SS_RATE_16384HZ 0x0eu 420 #define MCHP_WKTMR_SS_RATE_32768HZ 0x0fu 421 422 #define MCHP_WKTMR_SWKC_MASK 0x3c3u 423 #define MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS 0u 424 #define MCHP_WKTMR_SWKC_PWRUP_EV_STS_MASK \ 425 (1u << (MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS)) 426 #define MCHP_WKTMR_SWKC_PWRUP_EV_STS \ 427 (1u << (MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS)) 428 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS 4u 429 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_MASK \ 430 (1u << (MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS)) 431 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS \ 432 (1u << (MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS)) 433 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS 5u 434 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_MASK \ 435 (1u << (MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS)) 436 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN \ 437 (1u << (MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS)) 438 #define MCHP_WKTMR_SWKC_AUTO_RELOAD_POS \ 439 6u 440 #define MCHP_WKTMR_SWKC_AUTO_RELOAD_MASK \ 441 (1u << (MCHP_WKTMR_SWKC_AUTO_RELOAD_POS)) 442 #define MCHP_WKTMR_SWKC_AUTO_RELOAD \ 443 (1u << (MCHP_WKTMR_SWKC_AUTO_RELOAD_POS)) 444 445 /* Week timer interrupt routing */ 446 #define MCHP_WKTMR_GIRQ 21u 447 448 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 449 #define MCHP_WKTMR_ALARM_GIRQ_POS 3u 450 #define MCHP_WKTMR_SUBWK_GIRQ_POS 4u 451 #define MCHP_WKTMR_ONESEC_GIRQ_POS 5u 452 #define MCHP_WKTMR_SUBSEC_GIRQ_POS 6u 453 #define MCHP_WKTMR_SUSPWR_GIRQ_POS 7u 454 455 #define MCHP_WKTMR_ALARM_GIRQ_VAL (1u << 3) 456 #define MCHP_WKTMR_SUBWK_GIRQ_VAL (1u << 4) 457 #define MCHP_WKTMR_ONESEC_GIRQ_VAL (1u << 5) 458 #define MCHP_WKTMR_SUBSEC_GIRQ_VAL (1u << 6) 459 #define MCHP_WKTMR_SUSPWR_GIRQ_VAL (1u << 7) 460 461 /* Capture Compare timer GIRQ aggregated NVIC input */ 462 #define MCHP_WKTMR_NVIC_AGGR 13u 463 464 /* Capture Compare timer direct NVIC inputs */ 465 #define MCHP_WKTMR_ALARM_NVIC_DIRECT 114u 466 #define MCHP_WKTMR_SUBWK_NVIC_DIRECT 115u 467 #define MCHP_WKTMR_ONESEC_NVIC_DIRECT 116u 468 #define MCHP_WKTMR_SUBSEC_NVIC_DIRECT 117u 469 #define MCHP_WKTMR_SUSPWR_NVIC_DIRECT 118u 470 471 /** 472 * @brief Week Timer (WKTMR) 473 */ 474 475 typedef struct wktmr_regs 476 { /*!< (@ 0x4000ac80) WKTMR Structure */ 477 __IOM uint32_t CTRL; /*! (@ 0x00000000) WKTMR control */ 478 __IOM uint32_t ALARM_CNT; /*! (@ 0x00000004) WKTMR Week alarm counter */ 479 __IOM uint32_t TMR_COMP; /*! (@ 0x00000008) WKTMR Week timer compare */ 480 __IM uint32_t CLKDIV; /*! (@ 0x0000000c) WKTMR Clock Divider (RO) */ 481 __IOM uint32_t SS_INTR_SEL; /*! (@ 0x00000010) WKTMR Sub-second interrupt select */ 482 __IOM uint32_t SWK_CTRL; /*! (@ 0x00000014) WKTMR Sub-week control */ 483 __IOM uint32_t SWK_ALARM; /*! (@ 0x00000018) WKTMR Sub-week alarm */ 484 __IOM uint32_t BGPO_DATA; /*! (@ 0x0000001c) WKTMR BGPO data */ 485 __IOM uint32_t BGPO_PWR; /*! (@ 0x00000020) WKTMR BGPO power */ 486 __IOM uint32_t BGPO_RST; /*! (@ 0x00000024) WKTMR BGPO reset */ 487 } WKTMR_Type; 488 489 #endif /* #ifndef _TIMER_H */ 490 /* end timer.h */ 491 /** @} 492 */ 493
