1 /**************************************************************************//**
2 * @file     MEC1501hsz.h
3 * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
4 *           Device Microchip MEC1501-H-SZ
5 * @version  V5.00
6 * @date     03. January 2019
7 * Copyright (c) 2019 Microchip Technology Inc.
8 ******************************************************************************/
9 /*
10  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
11  * Copyright (c) 2019 Microchip Technology Incorporated. All rights reserved.
12  *
13  * SPDX-License-Identifier: Apache-2.0
14  *
15  * Licensed under the Apache License, Version 2.0 (the License); you may
16  * not use this file except in compliance with the License.
17  * You may obtain a copy of the License at
18  *
19  * www.apache.org/licenses/LICENSE-2.0
20  *
21  * Unless required by applicable law or agreed to in writing, software
22  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
23  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24  * See the License for the specific language governing permissions and
25  * limitations under the License.
26  */
27 
28 #ifndef MEC1501HSZ_H
29 #define MEC1501HSZ_H
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 /** @addtogroup MCHP
36   * @{
37   */
38 
39 /** @addtogroup MEC1501
40   * @{
41   */
42 
43 /** @addtogroup Configuration_of_CMSIS
44   * @{
45   */
46 
47 /* =========================================================================================================================== */
48 /* ================                                Interrupt Number Definition                                ================ */
49 /* =========================================================================================================================== */
50 
51 typedef enum IRQn {
52 	/* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
53 
54 	Reset_IRQn = -15,	/*!< -15  Reset Vector, invoked on Power up and warm reset                     */
55 	NonMaskableInt_IRQn = -14,	/*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
56 	HardFault_IRQn = -13,	/*!< -13  Hard Fault, all classes of Fault                                     */
57 	MemoryManagement_IRQn = -12,	/*!< -12  Memory Management, MPU mismatch, including Access Violation
58 						   and No Match                                                         */
59 	BusFault_IRQn = -11,	/*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
60 					   related Fault                                                        */
61 	UsageFault_IRQn = -10,	/*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
62 	SVCall_IRQn = -5,	/*!< -5 System Service Call via SVC instruction                                */
63 	DebugMonitor_IRQn = -4,	/*!< -4 Debug Monitor                                                          */
64 	PendSV_IRQn = -2,	/*!< -2 Pendable request for system service                                    */
65 	SysTick_IRQn = -1,	/*!< -1 System Tick Timer                                                      */
66 
67 	/* ===========================================  MEC15xx Specific Interrupt Numbers  ========================================= */
68 
69 	GIRQ08_IRQn = 0,	/*!< GPIO 0140 - 0176 */
70 	GIRQ09_IRQn = 1,	/*!< GPIO 0100 - 0136 */
71 	GIRQ10_IRQn = 2,	/*!< GPIO 0040 - 0076 */
72 	GIRQ11_IRQn = 3,	/*!< GPIO 0000 - 0036 */
73 	GIRQ12_IRQn = 4,	/*!< GPIO 0200 - 0236 */
74 	GIRQ13_IRQn = 5,	/*!< SMBus Aggregated */
75 	GIRQ14_IRQn = 6,	/*!< DMA Aggregated */
76 	GIRQ15_IRQn = 7,
77 	GIRQ16_IRQn = 8,
78 	GIRQ17_IRQn = 9,
79 	GIRQ18_IRQn = 10,
80 	GIRQ19_IRQn = 11,
81 	GIRQ20_IRQn = 12,
82 	GIRQ21_IRQn = 13,
83 	/* GIRQ22 is not connected to EC. It's purpose is peripheral clock wake */
84 	GIRQ23_IRQn = 14,
85 	GIRQ24_IRQn = 15,
86 	GIRQ25_IRQn = 16,
87 	GIRQ26_IRQn = 17,	/*!< GPIO 0240 - 0276 */
88 	/* Reserved gap, 18-19 */
89 	/* GIRQ's 8 - 12, 24 - 26 no direct connections */
90 	SMB0_IRQn = 20,	/* GIRQ13 b[0] */
91 	SMB1_IRQn = 21,	/* GIRQ13 b[1] */
92 	SMB2_IRQn = 22,	/* GIRQ13 b[2] */
93 	SMB3_IRQn = 23,	/* GIRQ13 b[3] */
94 	DMA0_IRQn = 24,	/* GIRQ14 b[0] */
95 	DMA1_IRQn = 25,	/* GIRQ14 b[1] */
96 	DMA2_IRQn = 26,	/* GIRQ14 b[2] */
97 	DMA3_IRQn = 27,	/* GIRQ14 b[3] */
98 	DMA4_IRQn = 28,	/* GIRQ14 b[4] */
99 	DMA5_IRQn = 29,	/* GIRQ14 b[5] */
100 	DMA6_IRQn = 30,	/* GIRQ14 b[6] */
101 	DMA7_IRQn = 31,	/* GIRQ14 b[7] */
102 	DMA8_IRQn = 32,	/* GIRQ14 b[8] */
103 	DMA9_IRQn = 33,	/* GIRQ14 b[9] */
104 	DMA10_IRQn = 34,	/* GIRQ14 b[10] */
105 	DMA11_IRQn = 35,	/* GIRQ14 b[11] */
106 	/* Reserved gap, 36-37 */
107 	/* Reserved gap, 38-39 */
108 	UART0_IRQn = 40,	/* GIRQ15 b[0] */
109 	UART1_IRQn = 41,	/* GIRQ15 b[1] */
110 	EMI0_IRQn = 42,	/* GIRQ15 b[2] */
111 	EMI1_IRQn = 43,	/* GIRQ15 b[3] */
112 	UART2_IRQn = 44,	/* GIRQ15 b[4] */
113 	ACPI_EC0_IBF_IRQn = 45,	/* GIRQ15 b[5] */
114 	ACPI_EC0_OBE_IRQn = 46,	/* GIRQ15 b[6] */
115 	ACPI_EC1_IBF_IRQn = 47,	/* GIRQ15 b[7] */
116 	ACPI_EC1_OBE_IRQn = 48,	/* GIRQ15 b[8] */
117 	ACPI_EC2_IBF_IRQn = 49,	/* GIRQ15 b[9] */
118 	ACPI_EC2_OBE_IRQn = 50,	/* GIRQ15 b[10] */
119 	ACPI_EC3_IBF_IRQn = 51,	/* GIRQ15 b[11] */
120 	ACPI_EC3_OBE_IRQn = 52,	/* GIRQ15 b[12] */
121 	/* Reserved gap, 53-54 */
122 	ACPI_PM1_CTL_IRQn = 55,	/* GIRQ15 b[15] */
123 	ACPI_PM1_EN_IRQn = 56,	/* GIRQ15 b[16] */
124 	ACPI_PM1_STS_IRQn = 57,	/* GIRQ15 b[17] */
125 	KBC_OBE_IRQn = 58,	/* GIRQ15 b[18] */
126 	KBC_IBF_IRQn = 59,	/* GIRQ15 b[19] */
127 	MBOX_IRQn = 60,	/* GIRQ15 b[20] */
128 	/* reserved gap 61 */
129 	P80CAP0_IRQn = 62,	/* GIRQ15 b[22] */
130 	P80CAP1_IRQn = 63,	/* GIRQ15 b[23] */
131 	/* reserved gap 64 */
132 	PKE_ERR_IRQn = 65,	/* GIRQ16 b[0] */
133 	PKE_DONE_IRQn = 66,	/* GIRQ16 b[1] */
134 	RNG_IRQn = 67,	/* GIRQ16 b[2] */
135 	AES_IRQn = 68,	/* GIRQ16 b[3] */
136 	HASH_IRQn = 69,	/* GIRQ16 b[4] */
137 	PECI_IRQn = 70,	/* GIRQ17 b[0] */
138 	TACH0_IRQn = 71,	/* GIRQ17 b[1] */
139 	TACH1_IRQn = 72,	/* GIRQ17 b[2] */
140 	TACH2_IRQn = 73,	/* GIRQ17 b[3] */
141 	/* reserved gap 74-77 */
142 	ADC_SNGL_IRQn = 78,	/* GIRQ17 b[8] */
143 	ADC_RPT_IRQn = 79,	/* GIRQ17 b[9] */
144 	/* reserved gap 80-82 */
145 	LED0_IRQn = 83,	/* GIRQ17 b[13] */
146 	LED1_IRQn = 84,	/* GIRQ17 b[14] */
147 	LED2_IRQn = 85,	/* GIRQ17 b[15] */
148 	/* reserved gap 86 */
149 	PHOT_IRQn = 87,	/* GIRQ17 b[17] */
150 	/* reserved gap 88-89 */
151 	SPISLV_IRQn = 90,	/* GIRQ18 b[0] */
152 	QMSPI_IRQn = 91,	/* GIRQ18 b[1] */
153 	/* reserved gap 92-99 */
154 	PS2_0_ACT_IRQn = 100,	/* GIRQ18 b[10] */
155 	PS2_1_ACT_IRQn = 101,	/* GIRQ18 b[11] */
156 	/* reserved gap 102 */
157 	ESPI_PC_IRQn = 103,	/* GIRQ19 b[0] */
158 	ESPI_BM1_IRQn = 104,	/* GIRQ19 b[1] */
159 	ESPI_BM2_IRQn = 105,	/* GIRQ19 b[2] */
160 	ESPI_LTR_IRQn = 106,	/* GIRQ19 b[3] */
161 	ESPI_OOB_UP_IRQn = 107,	/* GIRQ19 b[4] */
162 	ESPI_OOB_DN_IRQn = 108,	/* GIRQ19 b[5] */
163 	ESPI_FLASH_IRQn = 109,	/* GIRQ19 b[6] */
164 	ESPI_RESET_IRQn = 110,	/* GIRQ19 b[7] */
165 	RTMR_IRQn = 111,	/* GIRQ23 b[10] */
166 	HTMR0_IRQn = 112,	/* GIRQ23 b[16] */
167 	HTMR1_IRQn = 113,	/* GIRQ23 b[17] */
168 	WK_IRQn = 114,	/* GIRQ21 b[3] */
169 	WKSUB_IRQn = 115,	/* GIRQ21 b[4] */
170 	WKSEC_IRQn = 116,	/* GIRQ21 b[5] */
171 	WKSUBSEC_IRQn = 117,	/* GIRQ21 b[6] */
172 	SYSPWR_IRQn = 118,	/* GIRQ21 b[7] */
173 	RTC_IRQn = 119,	/* GIRQ21 b[8] */
174 	RTC_ALARM_IRQn = 120,	/* GIRQ21 b[9] */
175 	VCI_OVRD_IN_IRQn = 121,	/* GIRQ21 b[10] */
176 	VCI_IN0_IRQn = 122,	/* GIRQ21 b[11] */
177 	VCI_IN1_IRQn = 123,	/* GIRQ21 b[12] */
178 	VCI_IN2_IRQn = 124,	/* GIRQ21 b[13] */
179 	VCI_IN3_IRQn = 125,	/* GIRQ21 b[14] */
180 	/* reserved 126 - 128 */
181 	PS2_0A_WAKE_IRQn = 129,	/* GIRQ21 b[18] */
182 	PS2_0B_WAKE_IRQn = 130,	/* GIRQ21 b[19] */
183 	/* reserved gap 131 */
184 	PS2_1B_WAKE_IRQn = 132,	/* GIRQ21 b[21] */
185 	/* reserved gap 133 - 134 */
186 	KEYSCAN_IRQn = 135,	/* GIRQ21 b[25] */
187 	B16TMR0_IRQn = 136,	/* GIRQ23 b[0] */
188 	B16TMR1_IRQn = 137,	/* GIRQ23 b[1] */
189 	/* reserved gap 138 - 139 */
190 	B32TMR0_IRQn = 140,	/* GIRQ23 b[4] */
191 	B32TMR1_IRQn = 141,	/* GIRQ23 b[5] */
192 	/* reserved 142 - 145 */
193 	CCT_IRQn = 146,	/* GIRQ18 b[20] */
194 	CCT_CAP0_IRQn = 147,	/* GIRQ18 b[21] */
195 	CCT_CAP1_IRQn = 148,	/* GIRQ18 b[22] */
196 	CCT_CAP2_IRQn = 149,	/* GIRQ18 b[23] */
197 	CCT_CAP3_IRQn = 150,	/* GIRQ18 b[24] */
198 	CCT_CAP4_IRQn = 151,	/* GIRQ18 b[25] */
199 	CCT_CAP5_IRQn = 152,	/* GIRQ18 b[26] */
200 	CCT_CMP0_IRQn = 153,	/* GIRQ18 b[27] */
201 	CCT_CMP1_IRQn = 154,	/* GIRQ18 b[28] */
202 	EEPROM_CTRL_IRQn = 155,	/* GIRQ18 b[13] */
203 	ESPI_VWIRE_IRQn = 156,	/* GIRQ19 b[8] */
204 	/* reserved gap 157 */
205 	SMB4_IRQn = 158,	/* GIRQ13 b[4] */
206 	TACH3_IRQn = 159,	/* GIRQ17 b[4] */
207 	CEC_IRQn = 160,	/* GIRQ17 b[5] */
208 	SGPIOCtrl0_IRQn = 161,	/* GIRQ18 b[14] */
209 	SGPIOCtrl1_IRQn = 162,	/* GIRQ18 b[15] */
210 	SGPIOCtrl2_IRQn = 163,	/* GIRQ18 b[16] */
211 	SGPIOCtrl3_IRQn = 164,	/* GIRQ18 b[17] */
212 	/* reserved gap 165 */
213 	SAF_DONE_IRQn = 166,	/* GIRQ19 b[9] */
214 	SAF_ERR_IRQn = 167,	/* GIRQ19 b[10] */
215 	I2C0_IRQn = 168,	/* GIRQ13 b[5] */
216 	I2C1_IRQn = 169,	/* GIRQ13 b[6] */
217 	I2C2_IRQn = 170,	/* GIRQ13 b[7] */
218 	WDT_IRQn = 171,	/* GIRQ21 b[2] */
219 	GLUE_IRQn = 172,	/* GIRQ23 b[26] */
220 	OTP_READY_IRQn = 173,	/* GIRQ20 b[3] */
221 	MAX_IRQn = 174
222 } IRQn_Type;
223 
224 /* =========================================================================================================================== */
225 /* ================                           Processor and Core Peripheral Section                           ================ */
226 /* =========================================================================================================================== */
227 
228 /* ===========================  Configuration of the Arm Cortex-M4 Processor and Core Peripherals  =========================== */
229 
230 #define __CM4_REV                 0x0201	/*!< Core Revision r2p1 */
231 
232 #define __MPU_PRESENT             1	/*!< Set to 1 if MPU is present */
233 #define __VTOR_PRESENT            1	/*!< Set to 1 if VTOR is present */
234 #define __NVIC_PRIO_BITS          3	/*!< Number of Bits used for Priority Levels */
235 #define __Vendor_SysTickConfig    0	/*!< Set to 1 if different SysTick Config is used */
236 #define __FPU_PRESENT             0	/*!< Set to 1 if FPU is present */
237 #define __FPU_DP                  0	/*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */
238 #define __ICACHE_PRESENT          0	/*!< Set to 1 if I-Cache is present */
239 #define __DCACHE_PRESENT          0	/*!< Set to 1 if D-Cache is present */
240 #define __DTCM_PRESENT            0	/*!< Set to 1 if DTCM is present */
241 
242 /** @} *//* End of group Configuration_of_CMSIS */
243 
244 #include "core_cm4.h"		/*!< Arm Cortex-M4 processor and core peripherals */
245 
246 /* ========================================  Start of section using anonymous unions  ======================================== */
247 #if   defined (__CC_ARM)
248 #pragma push
249 #pragma anon_unions
250 #elif defined (__ICCARM__)
251 #pragma language=extended
252 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
253 #pragma clang diagnostic push
254 #pragma clang diagnostic ignored "-Wc11-extensions"
255 #pragma clang diagnostic ignored "-Wreserved-id-macro"
256 #elif defined (__GNUC__)
257 /* anonymous unions are enabled by default */
258 #elif defined (__TMS470__)
259 /* anonymous unions are enabled by default */
260 #elif defined (__TASKING__)
261 #pragma warning 586
262 #elif defined (__CSMC__)
263 /* anonymous unions are enabled by default */
264 #else
265 #warning Not supported compiler type
266 #endif
267 
268 /* ======================================================================== */
269 /* ================   Device Specific Peripheral Section   ================ */
270 /* ======================================================================== */
271 
272 /** @addtogroup MEC1501_Peripheral_peripherals
273   * @{
274   */
275 
276 /*@}*//* end of group MEC15xx_Peripherals */
277 
278 /* =========================================  End of section using anonymous unions  ========================================= */
279 #if   defined (__CC_ARM)
280 #pragma pop
281 #elif defined (__ICCARM__)
282 /* leave anonymous unions enabled */
283 #elif (__ARMCC_VERSION >= 6010050)
284 #pragma clang diagnostic pop
285 #elif defined (__GNUC__)
286 /* anonymous unions are enabled by default */
287 #elif defined (__TMS470__)
288 /* anonymous unions are enabled by default */
289 #elif defined (__TASKING__)
290 #pragma warning restore
291 #elif defined (__CSMC__)
292 /* anonymous unions are enabled by default */
293 #else
294 #warning Not supported compiler type
295 #endif
296 
297 /* =========================================================================*/
298 /* ================ Device Specific Peripheral Address Map ================ */
299 /* =========================================================================*/
300 
301 /** @addtogroup Device_Peripheral_peripheralAddr
302   * @{
303   */
304 
305 /* Peripheral and SRAM base address */
306 #define CODE_SRAM_BASE          0x000e0000u	/*!< (CODE SRAM ) Base Address */
307 #define DATA_SRAM_BASE          0x00118000u	/*!< (DATA SRAM ) Base Address */
308 #define PERIPH_BASE             0x40000000u	/*!< (Peripheral) Base Address */
309 
310 /* Peripheral memory map */
311 #define WDT_BASE            (PERIPH_BASE + 0x0400u)	/*!< (WDT0   )  Base Address */
312 #define B16TMR0_BASE        (PERIPH_BASE + 0x0c00u)	/*!< (B16TMR0 ) Base Address */
313 #define B16TMR1_BASE        (PERIPH_BASE + 0x0c20u)	/*!< (B16TMR1 ) Base Address */
314 #define B32TMR0_BASE        (PERIPH_BASE + 0x0c80u)	/*!< (B32TMR0 ) Base Address */
315 #define B32TMR1_BASE        (PERIPH_BASE + 0x0ca0u)	/*!< (B32TMR1 ) Base Address */
316 #define CCT_BASE            (PERIPH_BASE + 0x1000u)	/*!< (CCT0 ) Base Address */
317 #define DMA_BASE            (PERIPH_BASE + 0x2400u)	/*!< (DMA ) Base Address */
318 #define DMA_CHAN_BASE(n)    (DMA_BASE + (((n)+1)<<6))
319 #define DMA_CH0_BASE        (DMA_BASE + 0x0040u)	/*!< (DMA Chan 00 ) Base Address */
320 #define DMA_CH1_BASE        (DMA_BASE + 0x0080u)	/*!< (DMA Chan 01 ) Base Address */
321 #define DMA_CH2_BASE        (DMA_BASE + 0x00c0u)	/*!< (DMA Chan 02 ) Base Address */
322 #define DMA_CH3_BASE        (DMA_BASE + 0x0100u)	/*!< (DMA Chan 03 ) Base Address */
323 #define DMA_CH4_BASE        (DMA_BASE + 0x0140u)	/*!< (DMA Chan 04 ) Base Address */
324 #define DMA_CH5_BASE        (DMA_BASE + 0x0180u)	/*!< (DMA Chan 05 ) Base Address */
325 #define DMA_CH6_BASE        (DMA_BASE + 0x01c0u)	/*!< (DMA Chan 06 ) Base Address */
326 #define DMA_CH7_BASE        (DMA_BASE + 0x0200u)	/*!< (DMA Chan 07 ) Base Address */
327 #define DMA_CH8_BASE        (DMA_BASE + 0x0240u)	/*!< (DMA Chan 08 ) Base Address */
328 #define DMA_CH9_BASE        (DMA_BASE + 0x0280u)	/*!< (DMA Chan 09 ) Base Address */
329 #define DMA_CH10_BASE       (DMA_BASE + 0x02c0u)	/*!< (DMA Chan 10 ) Base Address */
330 #define DMA_CH11_BASE       (DMA_BASE + 0x0300u)	/*!< (DMA Chan 11 ) Base Address */
331 #define EEPROM_CTRL_BASE    (PERIPH_BASE + 0x2c00u)	/*!< (EEPROM_CTRL ) Base Address */
332 #define PROCHOT_BASE        (PERIPH_BASE + 0x3400u)	/*!< (PROCHOT ) Base Address */
333 #define SMB_BASE(n)         (PERIPH_BASE + 0x4000u + ((n)<<10))
334 #define SMB0_BASE           (PERIPH_BASE + 0x4000u)	/*!< (SMB0 ) Base Address */
335 #define SMB1_BASE           (PERIPH_BASE + 0x4400u)	/*!< (SMB1 ) Base Address */
336 #define SMB2_BASE           (PERIPH_BASE + 0x4800u)	/*!< (SMB2 ) Base Address */
337 #define SMB3_BASE           (PERIPH_BASE + 0x4c00u)	/*!< (SMB3 ) Base Address */
338 #define SMB4_BASE           (PERIPH_BASE + 0x5000u)	/*!< (SMB4 ) Base Address */
339 #define I2C_BASE(n)         (PERIPH_BASE + 0x5100u + ((n)<<8))
340 #define I2C0_BASE           (PERIPH_BASE + 0x5100u)	/*!< (I2C0 ) Base Address */
341 #define I2C1_BASE           (PERIPH_BASE + 0x5200u)	/*!< (I2C1 ) Base Address */
342 #define I2C2_BASE           (PERIPH_BASE + 0x5300u)	/*!< (I2C2 ) Base Address */
343 #define PWM_BASE(n)         (PERIPH_BASE + 0x5800u + ((n)<<4))
344 #define PWM0_BASE           (PERIPH_BASE + 0x5800u)	/*!< (PWM0 ) Base Address */
345 #define PWM1_BASE           (PERIPH_BASE + 0x5810u)	/*!< (PWM1 ) Base Address */
346 #define PWM2_BASE           (PERIPH_BASE + 0x5820u)	/*!< (PWM2 ) Base Address */
347 #define PWM3_BASE           (PERIPH_BASE + 0x5830u)	/*!< (PWM3 ) Base Address */
348 #define PWM4_BASE           (PERIPH_BASE + 0x5840u)	/*!< (PWM4 ) Base Address */
349 #define PWM5_BASE           (PERIPH_BASE + 0x5850u)	/*!< (PWM5 ) Base Address */
350 #define PWM6_BASE           (PERIPH_BASE + 0x5860u)	/*!< (PWM6 ) Base Address */
351 #define PWM7_BASE           (PERIPH_BASE + 0x5870u)	/*!< (PWM7 ) Base Address */
352 #define PWM8_BASE           (PERIPH_BASE + 0x5880u)	/*!< (PWM8 ) Base Address */
353 #define TACH_BASE(n)        (PERIPH_BASE + 0x6000u + ((n)<<4))
354 #define TACH0_BASE          (PERIPH_BASE + 0x6000u)	/*!< (TACH0 ) Base Address */
355 #define TACH1_BASE          (PERIPH_BASE + 0x6010u)	/*!< (TACH1 ) Base Address */
356 #define TACH2_BASE          (PERIPH_BASE + 0x6020u)	/*!< (TACH2 ) Base Address */
357 #define TACH3_BASE          (PERIPH_BASE + 0x6030u)	/*!< (TACH3 ) Base Address */
358 #define PECI_BASE           (PERIPH_BASE + 0x6400u)	/*!< (PECI ) Base Address */
359 #define HDMI_CEC_BASE       (PERIPH_BASE + 0x6800u)	/*!< (HDMI_CEC ) Base Address */
360 #define SPIP_BASE           (PERIPH_BASE + 0x7000u)	/*!< (SPIP ) Base Address */
361 #define RTMR_BASE           (PERIPH_BASE + 0x7400u)	/*!< (RTMR ) Base Address */
362 #define ADC_BASE            (PERIPH_BASE + 0x7c00u)	/*!< (ADC ) Base Address */
363 #define TFDP_BASE           (PERIPH_BASE + 0x8c00u)	/*!< (TFDP ) Base Address */
364 #define PS2_0_BASE          (PERIPH_BASE + 0x9000u)	/*!< (PS2 0 ) Base Address */
365 #define PS2_1_BASE          (PERIPH_BASE + 0x9040u)	/*!< (PS2 1 ) Base Address */
366 #define HTMR0_BASE          (PERIPH_BASE + 0x9800u)	/*!< (HTMR0 ) Base Address */
367 #define HTMR1_BASE          (PERIPH_BASE + 0x9820u)	/*!< (HTMR1 ) Base Address */
368 #define KEYSCAN_BASE        (PERIPH_BASE + 0x9c00u)	/*!< (KEYSCAN ) Base Address */
369 #define VBATR_BASE          (PERIPH_BASE + 0xa400u)	/*!< (VBATR ) Base Address */
370 #define VBATM_BASE          (PERIPH_BASE + 0xa800u)	/*!< (VBATM ) Base Address */
371 #define WKTMR_BASE          (PERIPH_BASE + 0xac80u)	/*!< (WKTMR ) Base Address */
372 #define VCI_BASE            (PERIPH_BASE + 0xae00u)	/*!< (VCI ) Base Address */
373 #define LED0_BASE           (PERIPH_BASE + 0xb800u)	/*!< (BBLED0 ) Base Address */
374 #define LED1_BASE           (PERIPH_BASE + 0xb900u)	/*!< (BBLED1 ) Base Address */
375 #define LED2_BASE           (PERIPH_BASE + 0xba00u)	/*!< (BBLED2 ) Base Address */
376 #define ECIA_BASE           (PERIPH_BASE + 0xe000u)	/*!< (ECIA ) Base Address */
377 #define ECS_BASE            (PERIPH_BASE + 0xfc00u)	/*!< (ECS ) Base Address */
378 #define QMSPI_BASE          (PERIPH_BASE + 0x70000u)	/*!< (QMSPI0 ) Base Address */
379 #define PCR_BASE            (PERIPH_BASE + 0x80100u)	/*!< (PCR ) Base Address */
380 #define GPIO_BASE           (PERIPH_BASE + 0x81000u)	/*!< (GPIO ) Base Address */
381 #define GPIO_CTRL_BASE      (GPIO_BASE)	/*!< (GPIO ) Control Base Address */
382 #define GPIO_PARIN_BASE     (GPIO_BASE + 0x0300u)	/*!< (GPIO Parallel I/O) Base Address */
383 #define GPIO_PAROUT_BASE    (GPIO_BASE + 0x0380u)	/*!< (GPIO Parallel I/O) Base Address */
384 #define GPIO_LOCK_BASE      (GPIO_BASE + 0x03e8u)	/*!< (GPIO Lock) Base Address */
385 #define GPIO_CTRL2_BASE     (GPIO_BASE + 0x0500u)	/*!< (GPIO ) Control2 Base Address */
386 #define OTP_BASE            (PERIPH_BASE + 0x82000u)	/*!< (OTP ) Base Address */
387 #define MBOX_BASE           (PERIPH_BASE + 0xf0000u)	/*!< (MBOX ) Base Address */
388 #define KBC_BASE            (PERIPH_BASE + 0xf0400u)	/*!< (KBC ) Base Address */
389 #define ACPI_EC_BASE(n)     (PERIPH_BASE + 0xf0800u + ((n)<<10))
390 #define ACPI_EC_0_BASE      (PERIPH_BASE + 0xf0800u)	/*!< (ACPI EC0 ) Base Address */
391 #define ACPI_EC_1_BASE      (PERIPH_BASE + 0xf0c00u)	/*!< (ACPI EC1 ) Base Address */
392 #define ACPI_EC_2_BASE      (PERIPH_BASE + 0xf1000u)	/*!< (ACPI EC2 ) Base Address */
393 #define ACPI_EC_3_BASE      (PERIPH_BASE + 0xf1400u)	/*!< (ACPI EC3 ) Base Address */
394 #define ACPI_PM1_BASE       (PERIPH_BASE + 0xf1c00u)	/*!< (ACPI PM1 ) Base Address */
395 #define PORT92_BASE         (PERIPH_BASE + 0xf2000u)	/*!< (PORT92 ) Base Address */
396 #define UART_BASE(n)        (PERIPH_BASE + 0xf2400u + ((n)<<10))
397 #define UART0_BASE          (PERIPH_BASE + 0xf2400u)	/*!< (UART0 ) Base Address */
398 #define UART1_BASE          (PERIPH_BASE + 0xf2800u)	/*!< (UART1 ) Base Address */
399 #define UART2_BASE          (PERIPH_BASE + 0xf2c00u)	/*!< (UART2 ) Base Address */
400 #define ESPI_IO_BASE        (PERIPH_BASE + 0xf3400u)	/*!< (ESPI IO Component) Base Address */
401 #define ESPI_IO_PC_BASE     ((ESPI_IO_BASE) + 0x100u)	/*!< (ESPI IO Peripheral Channel) Base Address */
402 #define ESPI_IO_HOST_BAR_BASE ((ESPI_IO_BASE) + 0x120u)	/*!< (ESPI IO Host IO BAR) Base Address */
403 #define ESPI_IO_LTR_BASE    ((ESPI_IO_BASE) + 0x220u)	/*!< (ESPI IO LTR) Base Address */
404 #define ESPI_IO_OOB_BASE    ((ESPI_IO_BASE) + 0x240u)	/*!< (ESPI IO Out-of-Band Channel) Base Address */
405 #define ESPI_IO_FC_BASE     ((ESPI_IO_BASE) + 0x280u)	/*!< (ESPI IO Flash Channel) Base Address */
406 #define ESPI_IO_CAP_BASE    ((ESPI_IO_BASE) + 0x2b0u)	/*!< (ESPI IO Capabilities) Base Address */
407 #define ESPI_IO_EC_BAR_BASE ((ESPI_IO_BASE) + 0x330u)	/*!< (ESPI IO EC IO BAR) Base Address */
408 #define ESPI_IO_VW_BASE     ((ESPI_IO_BASE) + 0x2b0u)	/*!< (ESPI IO EC IO VW registers) Base Address */
409 #define ESPI_IO_SIRQ_BASE   ((ESPI_IO_BASE) + 0x3a0u)	/*!< (ESPI IO Seril IRQ registers) Base Address */
410 
411 #define ESPI_MEM_BASE       (PERIPH_BASE + 0xf3800u)	/*!< (ESPI Memory Component) Base Address */
412 #define ESPI_MEM_EC_BAR_BASE ((ESPI_MEM_BASE) + 0x0130u)	/*!< (ESPI Logical Device Memory BAR EC */
413 #define ESPI_MEM_HOST_BAR_BASE ((ESPI_MEM_BASE) + 0x0330u)	/*!< (ESPI Logical Device Memory BAR Host */
414 #define ESPI_MEM_SRAM_EC_BAR_BASE ((ESPI_MEM_BASE) + 0x01a0u)	/*!< (ESPI Memory SRAM BAR EC */
415 #define ESPI_MEM_SRAM_HOST_BAR_BASE ((ESPI_MEM_BASE) + 0x03a0u)	/*!< (ESPI Memory SRAM BAR Host */
416 #define ESPI_MEM_BM_BASE    ((ESPI_MEM_BASE) + 0x0200u)	/*!< (ESPI Memory Component Bus Master) Base Address */
417 
418 #define EMI0_BASE           (PERIPH_BASE + 0xf4000u)	/*!< (EMI0 ) Base Address */
419 #define EMI1_BASE           (PERIPH_BASE + 0xf4400u)	/*!< (EMI1 ) Base Address */
420 
421 #define RTC_BASE            (PERIPH_BASE + 0xf5000u)	/*!< (RTC ) Base Address */
422 
423 #define P80CAP0_BASE        (PERIPH_BASE + 0xf8000u)	/*!< (P80CAP0 ) Base Address */
424 #define P80CAP1_BASE        (PERIPH_BASE + 0xf8400u)	/*!< (P80CAP1 ) Base Address */
425 
426 #define ESPI_VW_BASE        (PERIPH_BASE + 0xf9c00u)	/*!< (ESPI VW Component) Base Address */
427 #define ESPI_SMVW_BASE      (ESPI_VW_BASE + 0x200u)	/*!< (ESPI VW Component Slave-to-Master) Base Address */
428 
429 #define GCFG_BASE           (PERIPH_BASE + 0xfff00u)	/*!< (GCFG ) Base Address */
430 
431 #define DELAY_US_BASE (0x10000000u) /*!< (1 us Delay register) Base Address */
432 
433 /** @} *//* End of group Device_Peripheral_peripheralAddr */
434 
435 #define MCHP_ACMP_INSTANCES 1
436 #define MCHP_ACPI_EC_INSTANCES 4
437 #define MCHP_ACPI_PM1_INSTANCES 1
438 #define MCHP_ADC_INSTANCES 1
439 #define MCHP_BTMR16_INSTANCES 2
440 #define MCHP_BTMR32_INSTANCES 2
441 #define MCHP_CCT_INSTANCES 1
442 #define MCHP_CTMR_INSTANCES 0
443 #define MCHP_DMA_INSTANCES 1
444 #define MCHP_ECIA_INSTANCES 1
445 #define MCHP_EMI_INSTANCES 2
446 #define MCHP_HDMI_CEC_INSTANCES 1
447 #define MCHP_HTMR_INSTANCES 2
448 #define MCHP_I2C_INSTANCES 3
449 #define MCHP_I2C_SMB_INSTANCES 5
450 #define MCHP_LED_INSTANCES 3
451 #define MCHP_MBOX_INSTANCES 1
452 #define MCHP_OTP_INSTANCES 1
453 #define MCHP_P80CAP_INSTANCES 2
454 #define MCHP_PECI_INSTANCES 1
455 #define MCHP_PROCHOT_INSTANCES 1
456 #define MCHP_PS2_INSTANCES 2
457 #define MCHP_PWM_INSTANCES 9
458 #define MCHP_QMSPI_INSTANCES 1
459 #define MCHP_RCID_INSTANCES 3
460 #define MCHP_RPMFAN_INSTANCES 0
461 #define MCHP_RTC_INSTANCES 1
462 #define MCHP_RTMR_INSTANCES 1
463 #define MCHP_SPIP_INSTANCES 1
464 #define MCHP_TACH_INSTANCES 4
465 #define MCHP_TFDP_INSTANCES 1
466 #define MCHP_UART_INSTANCES 3
467 #define MCHP_WDT_INSTANCES 1
468 #define MCHP_WKTMR_INSTANCES 1
469 
470 #define MCHP_ACMP_CHANNELS 2
471 #define MCHP_ADC_CHANNELS 8
472 #define MCHP_BGPO_GPIO_PINS 3
473 #define MCHP_DMA_CHANNELS 12
474 #define MCHP_GIRQS 19
475 #define MCHP_GPIO_PINS 128
476 #define MCHP_GPIO_PORTS 6
477 #define MCHP_GPTP_PORTS 3
478 #define MCHP_I2C_SMB_PORTS 15
479 #define MCHP_I2C_PORTMAP 0xffffu;
480 #define MCHP_QMSPI_PORTS 3
481 #define MCHP_PS2_PORTS 2
482 #define MCHP_VCI_IN_PINS 4
483 #define MCHP_VCI_OUT_PINS 1
484 #define MCHP_VCI_OVRD_IN_PINS 0
485 
486 #include "component/acpi_ec.h"
487 #include "component/adc.h"
488 #include "component/dma.h"
489 #include "component/ecia.h"
490 #include "component/ecs.h"
491 #include "component/gpio.h"
492 #include "component/emi.h"
493 #include "component/espi_io.h"
494 #include "component/espi_mem.h"
495 #include "component/espi_saf.h"
496 #include "component/espi_vw.h"
497 #include "component/global_cfg.h"
498 #include "component/hdmi_cec.h"
499 #include "component/i2c.h"
500 #include "component/kbc.h"
501 #include "component/keyscan.h"
502 #include "component/led.h"
503 #include "component/mailbox.h"
504 #include "component/pcr.h"
505 #include "component/peci.h"
506 #include "component/port80cap.h"
507 #include "component/port92.h"
508 #include "component/prochot.h"
509 #include "component/ps2_ctrl.h"
510 #include "component/pwm.h"
511 #include "component/qmspi.h"
512 #include "component/rtc.h"
513 #include "component/smb.h"
514 #include "component/spi_periph.h"
515 #include "component/tach.h"
516 #include "component/tfdp.h"
517 #include "component/timer.h"
518 #include "component/uart.h"
519 #include "component/vbat.h"
520 #include "component/wdt.h"
521 
522 /* =========================================================================================================================== */
523 /* ================                                  Peripheral declaration                                   ================ */
524 /* =========================================================================================================================== */
525 
526 /** @addtogroup Device_Peripheral_declaration
527   * @{
528   */
529 
530 #define WDT_REGS        ((WDT_Type *) WDT_BASE)
531 #define B16TMR0_REGS    ((BTMR_Type *) B16TMR0_BASE)
532 #define B16TMR1_REGS    ((BTMR_Type *) B16TMR1_BASE)
533 #define B32TMR0_REGS    ((BTMR_Type *) B32TMR0_BASE)
534 #define B32TMR1_REGS	((BTMR_Type *) B32TMR1_BASE)
535 #define CCT_REGS	((CCT_Type *) (CCT_BASE))
536 
537 #define DMAM_REGS       ((DMAM_Type *) DMA_BASE)
538 /* Individual DMA channels */
539 #define DMA0_REGS       ((DMA_CHAN_ALU_Type *)(DMA_CHAN_BASE(0)))
540 #define DMA1_REGS       ((DMA_CHAN_ALU_Type *)(DMA_CHAN_BASE(1)))
541 #define DMA2_REGS       ((DMA_CHAN_Type *)(DMA_CHAN_BASE(2)))
542 #define DMA3_REGS       ((DMA_CHAN_Type *)(DMA_CHAN_BASE(3)))
543 #define DMA4_REGS       ((DMA_CHAN_Type *)(DMA_CHAN_BASE(4)))
544 #define DMA5_REGS       ((DMA_CHAN_Type *)(DMA_CHAN_BASE(5)))
545 #define DMA6_REGS       ((DMA_CHAN_Type *)(DMA_CHAN_BASE(6)))
546 #define DMA7_REGS       ((DMA_CHAN_Type *)(DMA_CHAN_BASE(7)))
547 #define DMA8_REGS       ((DMA_CHAN_Type *)(DMA_CHAN_BASE(8)))
548 #define DMA9_REGS       ((DMA_CHAN_Type *)(DMA_CHAN_BASE(9)))
549 #define DMA10_REGS      ((DMA_CHAN_Type *)(DMA_CHAN_BASE(10)))
550 #define DMA11_REGS      ((DMA_CHAN_Type *)(DMA_CHAN_BASE(11)))
551 
552 #define PROCHOT_REGS	((PROCHOT_Type *) PROCHOT_BASE)
553 
554 #define SMB0_REGS       ((I2C_SMB_Type *) SMB0_BASE)
555 #define SMB1_REGS       ((I2C_SMB_Type *) SMB1_BASE)
556 #define SMB2_REGS       ((I2C_SMB_Type *) SMB2_BASE)
557 #define SMB3_REGS       ((I2C_SMB_Type *) SMB3_BASE)
558 #define SMB4_REGS       ((I2C_SMB_Type *) SMB4_BASE)
559 
560 #define PWM0_REGS	((PWM_Type *) PWM0_BASE)
561 #define PWM1_REGS	((PWM_Type *) PWM1_BASE)
562 #define PWM2_REGS	((PWM_Type *) PWM2_BASE)
563 #define PWM3_REGS	((PWM_Type *) PWM3_BASE)
564 #define PWM4_REGS	((PWM_Type *) PWM4_BASE)
565 #define PWM5_REGS	((PWM_Type *) PWM5_BASE)
566 #define PWM6_REGS	((PWM_Type *) PWM6_BASE)
567 #define PWM7_REGS	((PWM_Type *) PWM7_BASE)
568 #define PWM8_REGS	((PWM_Type *) PWM8_BASE)
569 
570 #define TACH0_REGS	((TACH_Type *) TACH0_BASE)
571 #define TACH1_REGS	((TACH_Type *) TACH1_BASE)
572 #define TACH2_REGS	((TACH_Type *) TACH2_BASE)
573 #define TACH3_REGS	((TACH_Type *) TACH3_BASE)
574 
575 #define PECI_REGS	((PECI_Type *) PECI_BASE)
576 
577 #define HDMI_CEC_REGS	((HDMI_CEC_Type *) HDMI_CEC_BASE)
578 
579 #define SPIP_REGS	((SPIP_Type *) SPIP_BASE)
580 
581 #define RTMR_REGS       ((RTMR_Type *) RTMR_BASE)
582 
583 #define ADC_REGS	((ADC_Type *) ADC_BASE)
584 
585 #define TFDP_REGS	((TFDP_Type *) TFDP_BASE)
586 
587 #define PS2_0_REGS	((PS2_Type *) PS2_0_BASE)
588 #define PS2_1_REGS	((PS2_Type *) PS2_1_BASE)
589 
590 #define HTMR0_REGS      ((HTMR_Type *) HTMR0_BASE)
591 #define HTMR1_REGS      ((HTMR_Type *) HTMR1_BASE)
592 
593 #define KSCAN_REGS      ((KSCAN_Type *)(KEYSCAN_BASE))
594 
595 #define VBATR_REGS      ((VBATR_Type *) VBATR_BASE)
596 #define VBATM_REGS      ((VBATM_Type *) VBATM_BASE)
597 #define WKTMR_REGS      ((WKTMR_Type *) WKTMR_BASE)
598 
599 #define VCI_REGS	((VCI_Type *) VCI_BASE)
600 
601 #define LED0_REGS       ((LED_Type *) LED0_BASE)
602 #define LED1_REGS       ((LED_Type *) LED1_BASE)
603 #define LED2_REGS       ((LED_Type *) LED2_BASE)
604 
605 #define ECIA_REGS       ((ECIA_Type *) ECIA_BASE)
606 #define GIRQ08_REGS     ((GIRQ_Type *) ECIA_BASE)
607 #define GIRQ09_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x14))
608 #define GIRQ10_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x28))
609 #define GIRQ11_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x3C))
610 #define GIRQ12_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x50))
611 #define GIRQ13_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x64))
612 #define GIRQ14_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x78))
613 #define GIRQ15_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x8C))
614 #define GIRQ16_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0xA0))
615 #define GIRQ17_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0xB4))
616 #define GIRQ18_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0xC8))
617 #define GIRQ19_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0xDC))
618 #define GIRQ20_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0xF0))
619 #define GIRQ21_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x104))
620 #define GIRQ22_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x118))
621 #define GIRQ23_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x12C))
622 #define GIRQ24_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x140))
623 #define GIRQ25_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x154))
624 #define GIRQ26_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x168))
625 
626 #define ECS_REGS        ((ECS_Type *) ECS_BASE)
627 
628 #define QMSPI_REGS      ((QMSPI_Type *) QMSPI_BASE)
629 
630 #define PCR_REGS        ((PCR_Type *) PCR_BASE)
631 
632 #define GPIO_CTRL_REGS      ((GPIO_CTRL_Type *)(GPIO_CTRL_BASE))
633 #define GPIO_CTRL2_REGS     ((GPIO_CTRL2_Type *)(GPIO_CTRL2_BASE))
634 #define GPIO_PARIN_REGS     ((GPIO_PARIN_Type *)(GPIO_PARIN_BASE))
635 #define GPIO_PAROUT_REGS    ((GPIO_PAROUT_Type *)(GPIO_PAROUT_BASE))
636 #define GPIO_LOCK_REGS      ((GPIO_LOCK_Type *)(GPIO_LOCK_BASE))
637 
638 #define MBOX_REGS       ((MBOX_Type *)(MBOX_BASE))
639 
640 #define KBC_REGS        ((KBC_Type *)(KBC_BASE))
641 
642 #define ACPI_EC_0_REGS  ((ACPI_EC_Type *)(ACPI_EC_0_BASE))
643 #define ACPI_EC_1_REGS  ((ACPI_EC_Type *)(ACPI_EC_1_BASE))
644 #define ACPI_EC_2_REGS  ((ACPI_EC_Type *)(ACPI_EC_2_BASE))
645 #define ACPI_EC_3_REGS  ((ACPI_EC_Type *)(ACPI_EC_3_BASE))
646 
647 #define ACPI_PM1_REGS	((ACPI_PM1_Type *) ACPI_PM1_BASE)
648 
649 #define PORT92_REGS     ((PORT92_Type *)(PORT92_BASE))
650 
651 #define UART0_REGS      ((UART_Type *) UART0_BASE)
652 #define UART1_REGS      ((UART_Type *) UART1_BASE)
653 #define UART2_REGS      ((UART_Type *) UART2_BASE)
654 
655 #define ESPI_PC_REGS        ((ESPI_IO_PC_Type *)(ESPI_IO_PC_BASE))
656 #define ESPI_HIO_BAR_REGS   ((ESPI_IO_BAR_HOST_Type *)(ESPI_IO_HOST_BAR_BASE))
657 #define ESPI_LTR_REGS       ((ESPI_IO_LTR_Type *)(ESPI_IO_LTR_BASE))
658 #define ESPI_OOB_REGS       ((ESPI_IO_OOB_Type *)(ESPI_IO_OOB_BASE))
659 #define ESPI_FC_REGS        ((ESPI_IO_FC_Type *)(ESPI_IO_FC_BASE))
660 #define ESPI_CAP_REGS       ((ESPI_IO_CAP_Type *)(ESPI_IO_CAP_BASE))
661 #define ESPI_EIO_BAR_REGS   ((ESPI_IO_BAR_EC_Type *)(ESPI_IO_EC_BAR_BASE))
662 #define ESPI_SIRQ_REGS      ((ESPI_IO_SIRQ_Type *)(ESPI_IO_SIRQ_BASE))
663 
664 #define ESPI_MEM_EBAR_REGS  ((ESPI_MEM_BAR_EC_Type *)(ESPI_MEM_EC_BAR_BASE))
665 #define ESPI_MEM_HBAR_REGS  ((ESPI_MEM_BAR_HOST_Type *)(ESPI_MEM_HOST_BAR_BASE))
666 
667 #define ESPI_MEM_SRAM_EBAR_REGS \
668 	((ESPI_MEM_SRAM_BAR_EC_Type *)(ESPI_MEM_SRAM_EC_BAR_BASE))
669 #define ESPI_MEM_SRAM_HBAR_REGS \
670 	((ESPI_MEM_SRAM_BAR_HOST_Type *)(ESPI_MEM_SRAM_HOST_BAR_BASE))
671 
672 #define ESPI_MEM_BM_REGS  ((ESPI_MEM_BM_Type *)(ESPI_MEM_BM_BASE))
673 
674 /* eSPI Virtual Wire registers in IO component */
675 #define ESPI_IO_VW_REGS      ((ESPI_IO_VW_Type *) (ESPI_IO_VW_BASE))
676 /* eSPI Virtual Wire registers for each group of 4 VWires */
677 #define ESPI_M2S_VW_REGS    ((ESPI_M2S_VW_Type *) (ESPI_VW_BASE))
678 #define ESPI_S2M_VW_REGS    ((ESPI_S2M_VW_Type *) (ESPI_SMVW_BASE))
679 
680 #define EMI0_REGS       ((EMI_Type *)(EMI0_BASE))
681 #define EMI1_REGS       ((EMI_Type *)(EMI0_BASE))
682 
683 #define RTC_REGS	((RTC_Type *) RTC_BASE)
684 
685 #define PORT80_CAP0_REGS	((PORT80_CAP_Type *)(P80CAP0_BASE))
686 #define PORT80_CAP1_REGS	((PORT80_CAP_Type *)(P80CAP1_BASE))
687 
688 #define GLOBAL_CFG_REGS		((GLOBAL_CFG_Type *) GCFG_BASE)
689 
690 /** @} *//* End of group MEC1501 */
691 
692 /** @} *//* End of group MCHP */
693 
694 #ifdef __cplusplus
695 }
696 #endif
697 #endif				/* MEC1501HSZ_H */
698