1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file port92.h 28 *MEC1501 Fast Port92h Registers 29 */ 30 /** @defgroup MEC1501 Peripherals Fast Port92 31 */ 32 33 #ifndef _PORT92_H 34 #define _PORT92_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* =========================================================================*/ 42 /* ================ PORT92 ================ */ 43 /* =========================================================================*/ 44 45 #define MCHP_PORT92_BASE_ADDR 0x400f2000u 46 47 /* 48 * HOST_P92 49 */ 50 #define MCHP_PORT92_HOST_MASK 0x03u 51 #define MCHP_PORT92_HOST_ALT_CPU_RST_POS 0u 52 #define MCHP_PORT92_HOST_ALT_CPU_RST (1u << 0) 53 #define MCHP_PORT92_HOST_ALT_GA20_POS 1u 54 #define MCHP_PORT92_HOST_ALT_GA20 (1u << 1) 55 56 /* 57 * GATEA20_CTRL 58 */ 59 #define MCHP_PORT92_GA20_CTRL_MASK 0x01u 60 #define MCHP_PORT92_GA20_CTRL_VAL_POS 0u 61 #define MCHP_PORT92_GA20_CTRL_VAL_MASK (1u << 0) 62 #define MCHP_PORT92_GA20_CTRL_VAL_HI (1u << 0) 63 #define MCHP_PORT92_GA20_CTRL_VAL_LO (0u << 0) 64 65 /* 66 * SETGA20L - writes of any data to this register causes 67 * GATEA20 latch to be set. 68 */ 69 #define MCHP_PORT92_SETGA20L_MASK 0x01u 70 #define MCHP_PORT92_SETGA20L_SET_POS 0u 71 #define MCHP_PORT92_SETGA20L_SET (1u << 0) 72 73 /* 74 * RSTGA20L - writes of any data to this register causes 75 * the GATEA20 latch to be reset 76 */ 77 #define MCHP_PORT92_RSTGA20L_MASK 0x01u 78 #define MCHP_PORT92_RSTGA20L_SET_POS 0u 79 #define MCHP_PORT92_RSTGA20L_RST (1u << 0) 80 81 /* 82 * ACTV 83 */ 84 #define MCHP_PORT92_ACTV_MASK 0x01u 85 #define MCHP_PORT92_ACTV_ENABLE 0x01u 86 87 /** 88 * @brief Fast Port92h Registers (PORT92) 89 */ 90 typedef struct port92_regs 91 { 92 __IOM uint32_t HOST_P92; /*!< (@ 0x0000) HOST Port92h register */ 93 uint8_t RSVD1[0x100u - 0x04u]; 94 __IOM uint32_t GATEA20_CTRL; /*!< (@ 0x0100) Gate A20 Control */ 95 uint8_t RSVD2[4]; 96 __IOM uint32_t SETGA20L; /*!< (@ 0x0108) Set Gate A20 */ 97 __IOM uint32_t RSTGA20L; /*!< (@ 0x010c) Reset Gate A20 */ 98 uint8_t RSVD3[0x0330u - 0x0110u]; 99 __IOM uint32_t ACTV; /*!< (@ 0x0330) Logical device Activate */ 100 } PORT92_Type; 101 102 #endif /* #ifndef _PORT92_H */ 103 /* end port92.h */ 104 /** @} 105 */ 106
