1 /**
2  *
3  * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
4  *
5  * \asf_license_start
6  *
7  * \page License
8  *
9  * SPDX-License-Identifier: Apache-2.0
10  *
11  * Licensed under the Apache License, Version 2.0 (the "License"); you may
12  * not use this file except in compliance with the License.
13  * You may obtain a copy of the Licence at
14  *
15  * http://www.apache.org/licenses/LICENSE-2.0
16  *
17  * Unless required by applicable law or agreed to in writing, software
18  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
19  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20  * See the License for the specific language governing permissions and
21  * limitations under the License.
22  *
23  * \asf_license_stop
24  *
25  */
26 
27 /** @file i2c.h
28  *MEC1501 I2C register definitions
29  */
30 /** @defgroup MEC1501 Peripherals I2C
31  */
32 
33 #ifndef _I2C_H
34 #define _I2C_H
35 
36 #include <stdint.h>
37 #include <stddef.h>
38 
39 #include "regaccess.h"
40 
41 #define MCHP_I2C_MAX_INSTANCES		3u
42 #define MCHP_I2C_INST_SPACING		0x100u
43 #define MCHP_I2C_INST_SPACING_P2	8u
44 
45 #define MCHP_I2C0_BASE_ADDR	0x40005100u
46 #define MCHP_I2C1_BASE_ADDR	0x40005200u
47 #define MCHP_I2C2_BASE_ADDR	0x40005300u
48 
49 /* 0 <= n < MCHP_I2C_MAX_INSTANCES */
50 #define MCHP_I2C_BASE_ADDR(n) \
51 	((MCHP_I2C0_BASE_ADDR) + (n) << (MCHP_I2C_INST_SPACING_P2))
52 
53 /*
54  * Offset 0x00
55  * Control and Status register
56  * Write to Control
57  * Read from Status
58  * Size 8-bit
59  */
60 #define MCHP_I2C_CTRL_OFS	0x00u
61 #define MCHP_I2C_CTRL_MASK	0xcfu
62 #define MCHP_I2C_CTRL_ACK	(1u << 0)
63 #define MCHP_I2C_CTRL_STO	(1u << 1)
64 #define MCHP_I2C_CTRL_STA	(1u << 2)
65 #define MCHP_I2C_CTRL_ENI	(1u << 3)
66 /* bits [5:4] reserved */
67 #define MCHP_I2C_CTRL_ESO	(1u << 6)
68 #define MCHP_I2C_CTRL_PIN	(1u << 7)
69 /* Status Read-only */
70 #define MCHP_I2C_STS_OFS	0x00u
71 #define MCHP_I2C_STS_NBB	(1u << 0)
72 #define MCHP_I2C_STS_LAB	(1u << 1)
73 #define MCHP_I2C_STS_AAS	(1u << 2)
74 #define MCHP_I2C_STS_LRB_AD0	(1u << 3)
75 #define MCHP_I2C_STS_BER	(1u << 4)
76 #define MCHP_I2C_STS_EXT_STOP	(1u << 5)
77 #define MCHP_I2C_STS_PIN	(1u << 7)
78 
79 /*
80  * Offset 0x04
81  * Own Address b[7:0] = Slave address 1
82  * b[14:8] = Slave address 2
83  */
84 #define MCHP_I2C_OWN_ADDR_OFS	0x04u
85 #define MCHP_I2C_OWN_ADDR2_OFS	0x05u
86 #define MCHP_I2C_OWN_ADDR_MASK	0x7f7fu
87 
88 /*
89  * Offset 0x08
90  * Data register, 8-bit
91  * Data to be shifted out or shifted in.
92  */
93 #define MCHP_I2C_DATA_OFS	0x08u
94 
95 /*
96  * Offset 0x18
97  * Repeated Start Hold Time register, 8-bit read-write
98  */
99 #define MCHP_I2C_RSHT_OFS	0x18u
100 
101 /*
102  * Offset 0x20
103  * Complettion register, 32-bit
104  */
105 #define MCHP_I2C_CMPL_OFS		0x20u
106 #define MCHP_I2C_CMPL_MASK		0xe33b7f7cu
107 #define MCHP_I2C_CMPL_RW1C_MASK		0xe1397f00u
108 #define MCHP_I2C_CMPL_DTEN		(1u << 2)
109 #define MCHP_I2C_CMPL_MCEN		(1u << 3)
110 #define MCHP_I2C_CMPL_SCEN		(1u << 4)
111 #define MCHP_I2C_CMPL_BIDEN		(1u << 5)
112 #define MCHP_I2C_CMPL_TIMERR		(1u << 6)
113 #define MCHP_I2C_CMPL_DTO_RWC		(1u << 8)
114 #define MCHP_I2C_CMPL_MCTO_RWC		(1u << 9)
115 #define MCHP_I2C_CMPL_SCTO_RWC		(1u << 10)
116 #define MCHP_I2C_CMPL_CHDL_RWC		(1u << 11)
117 #define MCHP_I2C_CMPL_CHDH_RWC		(1u << 12)
118 #define MCHP_I2C_CMPL_BER_RWC		(1u << 13)
119 #define MCHP_I2C_CMPL_LAB_RWC		(1u << 14)
120 #define MCHP_I2C_CMPL_SNAKR_RWC		(1u << 16)
121 #define MCHP_I2C_CMPL_STR_RO		(1u << 17)
122 #define MCHP_I2C_CMPL_RPT_RD_RWC	(1u << 20)
123 #define MCHP_I2C_CMPL_RPT_WR_RWC	(1u << 21)
124 #define MCHP_I2C_CMPL_MNAKX_RWC		(1u << 24)
125 #define MCHP_I2C_CMPL_MTR_RO		(1u << 25)
126 #define MCHP_I2C_CMPL_IDLE_RWC		(1u << 29)
127 #define MCHP_I2C_CMPL_MDONE_RWC		(1u << 30)
128 #define MCHP_I2C_CMPL_SDONE_RWC		(1u << 31)
129 
130 /*
131  * Offset 0x28
132  * Configuration register
133  */
134 #define MCHP_I2C_CFG_OFS		0x28u
135 #define MCHP_I2C_CFG_MASK		0x0000c73fu
136 #define MCHP_I2C_CFG_PORT_SEL_MASK	0x0fu
137 #define MCHP_I2C_CFG_TCEN		(1u << 4)
138 #define MCHP_I2C_CFG_SLOW_CLK		(1u << 5)
139 #define MCHP_I2C_CFG_FEN		(1u << 8)
140 #define MCHP_I2C_CFG_RESET		(1u << 9)
141 #define MCHP_I2C_CFG_ENAB		(1u << 10)
142 #define MCHP_I2C_CFG_GC_EN		(1u << 14)
143 #define MCHP_I2C_CFG_PROM_EN		(1u << 15)
144 
145 /*
146  * Offset 0x2c
147  * Bus Clock register
148  */
149 #define MCHP_I2C_BUS_CLK_OFS		0x2cu
150 #define MCHP_I2C_BUS_CLK_MASK		0x0000ffffu
151 #define MCHP_I2C_BUS_CLK_LO_POS		0u
152 #define MCHP_I2C_BUS_CLK_HI_POS		8u
153 
154 /*
155  * Offset 0x30
156  * Block ID register, 8-bit read-only
157  */
158 #define MCHP_I2C_BLOCK_ID_OFS		0x30u
159 #define MCHP_I2C_BLOCK_ID_MASK		0xffu
160 
161 /*
162  * Offset 0x34
163  * Block Revision register, 8-bit read-only
164  */
165 #define MCHP_I2C_BLOCK_REV_OFS		0x34u
166 #define MCHP_I2C_BLOCK_REV_MASK		0xffu
167 
168 /*
169  * Offset 0x38
170  * Bit-Bang Control register, 8-bit read-write
171  */
172 #define MCHP_I2C_BB_OFS			0x38u
173 #define MCHP_I2C_BB_MASK		0x7fu
174 #define MCHP_I2C_BB_EN			(1u << 0)
175 #define MCHP_I2C_BB_SCL_DIR_IN		(0u << 1)
176 #define MCHP_I2C_BB_SCL_DIR_OUT		(1u << 1)
177 #define MCHP_I2C_BB_SDA_DIR_IN		(0u << 2)
178 #define MCHP_I2C_BB_SDA_DIR_OUT		(1u << 2)
179 #define MCHP_I2C_BB_CL			(1u << 3)
180 #define MCHP_I2C_BB_DAT			(1u << 4)
181 #define MCHP_I2C_BB_IN_POS		5u
182 #define MCHP_I2C_BB_IN_MASK0		0x03u
183 #define MCHP_I2C_BB_IN_MASK		(0x03u << 5)
184 #define MCHP_I2C_BB_CLKI_RO		(1u << 5)
185 #define MCHP_I2C_BB_DATI_RO		(1u << 6)
186 
187 /*
188  * Offset 0x40
189  * Data Timing register
190  */
191 #define MCHP_I2C_DATA_TM_OFS			0x40u
192 #define MCHP_I2C_DATA_TM_MASK			0xffffffffu
193 #define MCHP_I2C_DATA_TM_DATA_HOLD_POS		0u
194 #define MCHP_I2C_DATA_TM_DATA_HOLD_MASK		0xffu
195 #define MCHP_I2C_DATA_TM_DATA_HOLD_MASK0	0xffu
196 #define MCHP_I2C_DATA_TM_RESTART_POS		8u
197 #define MCHP_I2C_DATA_TM_RESTART_MASK		0xff00u
198 #define MCHP_I2C_DATA_TM_RESTART_MASK0		0xffu
199 #define MCHP_I2C_DATA_TM_STOP_POS		16u
200 #define MCHP_I2C_DATA_TM_STOP_MASK		0xff0000u
201 #define MCHP_I2C_DATA_TM_STOP_MASK0		0xffu
202 #define MCHP_I2C_DATA_TM_FSTART_POS		24u
203 #define MCHP_I2C_DATA_TM_FSTART_MASK		0xff000000u
204 #define MCHP_I2C_DATA_TM_FSTART_MASK0		0xffu
205 
206 /*
207  * Offset 0x44
208  * Time-out Scaling register
209  */
210 #define MCHP_I2C_TMTSC_OFS		0x44u
211 #define MCHP_I2C_TMTSC_MASK		0xffffffffu
212 #define MCHP_I2C_TMTSC_CLK_HI_POS	0u
213 #define MCHP_I2C_TMTSC_CLK_HI_MASK	0xffu
214 #define MCHP_I2C_TMTSC_CLK_HI_MASK0	0xffu
215 #define MCHP_I2C_TMTSC_SLV_POS		8u
216 #define MCHP_I2C_TMTSC_SLV_MASK		0xff00u
217 #define MCHP_I2C_TMTSC_SLV_MASK0	0xffu
218 #define MCHP_I2C_TMTSC_MSTR_POS		16u
219 #define MCHP_I2C_TMTSC_MSTR_MASK	0xff0000u
220 #define MCHP_I2C_TMTSC_MSTR_MASK0	0xffu
221 #define MCHP_I2C_TMTSC_BUS_POS		24u
222 #define MCHP_I2C_TMTSC_BUS_MASK		0xff000000u
223 #define MCHP_I2C_TMTSC_BUS_MASK0	0xffu
224 
225 /*
226  * Offset 0x60
227  * Wake Status register
228  */
229 #define MCHP_I2C_WAKE_STS_OFS		0x60u
230 #define MCHP_I2C_WAKE_STS_START_RWC	(1u << 0)
231 
232 /*
233  * Offset 0x64
234  * Wake Enable register
235  */
236 #define MCHP_I2C_WAKE_EN_OFS		0x64u
237 #define MCHP_I2C_WAKE_EN		(1u << 0)
238 
239 /*
240  * Offset 0x6c
241  * Slave Address captured from bus
242  */
243 #define MCHP_I2C_SLV_ADDR_OFS		0x6cu
244 #define MCHP_I2C_SLV_ADDR_MASK		0xffu
245 
246 /*
247  * Offset 0x70
248  * Promiscuous Interrupt Status
249  */
250 #define MCHP_I2C_PROM_INTR_STS_OFS	0x70u
251 #define MCHP_I2C_PROM_INTR_STS		0x01u
252 
253 /*
254  * Offset 0x74
255  * Promiscuous Interrupt Enable
256  */
257 #define MCHP_I2C_PROM_INTR_EN_OFS	0x74u
258 #define MCHP_I2C_PROM_INTR_EN		0x01u
259 
260 /*
261  * Offset 0x78
262  * Promiscuous Control
263  */
264 #define MCHP_I2C_PROM_CTRL_OFS		0x78u
265 #define MCHP_I2C_PROM_CTRL_ACK_ADDR	0x01u
266 #define MCHP_I2C_PROM_CTRL_NACK_ADDR	0x00u
267 
268 /*
269  * I2C GIRQ and NVIC mapping
270  */
271 #define MCHP_I2C_GIRQ		3u
272 #define MCHP_I2C_GIRQ_IDX	(13u - 8u)
273 #define MCHP_I2C_NVIC_GIRQ	5u
274 #define MCHP_I2C0_NVIC_DIRECT	168u
275 #define MCHP_I2C1_NVIC_DIRECT	169u
276 #define MCHP_I2C2_NVIC_DIRECT	170u
277 
278 #define MCHP_I2C_GIRQ_SRC_ADDR		0x4000e064u
279 #define MCHP_I2C_GIRQ_SET_EN_ADDR	0x4000e068u
280 #define MCHP_I2C_GIRQ_RESULT_ADDR	0x4000e06cu
281 #define MCHP_I2C_GIRQ_CLR_EN_ADDR	0x4000e070u
282 
283 #define MCHP_I2C0_GIRQ_POS	5u
284 #define MCHP_I2C1_GIRQ_POS	6u
285 #define MCHP_I2C2_GIRQ_POS	7u
286 
287 #define MCHP_I2C0_GIRQ_VAL	(1u << 5)
288 #define MCHP_I2C1_GIRQ_VAL	(1u << 6)
289 #define MCHP_I2C2_GIRQ_VAL	(1u << 7)
290 
291 /*
292  * Register access by controller base address
293  */
294 
295 /* I2C Control register, write-only */
296 #define MCHP_I2C_CTRL_WO(ba) REG8(ba)
297 /* I2C Status register, read-only */
298 #define MCHP_I2C_STS_RO(ba)  REG8(ba)
299 
300 #define MCHP_I2C_CTRL(ba) REG8_OFS(ba, MCHP_I2C_CTRL_OFS)
301 
302 /* Own Address register (slave addresses) */
303 #define MCHP_I2C_OWN_ADDR(ba) REG16_OFS(ba, MCHP_I2C_OWN_ADDR_OFS)
304 /* access bits[7:0] OWN_ADDRESS_1 */
305 #define MCHP_I2C_OWN_ADDR1(ba) REG8_OFS(ba, MCHP_I2C_OWN_ADDR_OFS)
306 /* access bits[15:8] OWN_ADDRESS_2 */
307 #define MCHP_I2C_OWN_ADDR2(ba) REG8_OFS(ba, (MCHP_I2C_OWN_ADDR_OFS + 1))
308 
309 /* I2C Data register */
310 #define MCHP_I2C_DATA(ba) REG8_OFS(ba, MCHP_I2C_DATA_OFS)
311 
312 /* Repeated Start Hold Time register */
313 #define MCHP_I2C_RSHT(ba) REG8_OFS(ba, MCHP_I2C_RSHT_OFS)
314 
315 /* Completion register */
316 #define MCHP_I2C_CMPL(ba) REG32_OFS(ba, MCHP_I2C_CMPL_OFS)
317 /* access only bits[7:0] R/W timeout enables */
318 #define MCHP_I2C_CMPL_B0(ba) REG8_OFS(ba, MCHP_I2C_CMPL_OFS)
319 
320 /* Idle Scaling register */
321 #define MCHP_I2C_IDLSC(ba) REG32_OFS(ba, MCHP_I2C_IDLSC_OFS)
322 
323 /* Configuration register */
324 #define MCHP_I2C_CFG(ba) REG32_OFS(ba, MCHP_I2C_CFG_OFS)
325 /* access each byte */
326 #define MCHP_I2C_CFG_B0(ba) REG8_OFS(ba, (MCHP_I2C_CFG_OFS + 0x00u))
327 #define MCHP_I2C_CFG_B1(ba) REG8_OFS(ba, (MCHP_I2C_CFG_OFS + 0x01u))
328 #define MCHP_I2C_CFG_B2(ba) REG8_OFS(ba, (MCHP_I2C_CFG_OFS + 0x02u))
329 #define MCHP_I2C_CFG_B3(ba) REG8_OFS(ba, (MCHP_I2C_CFG_OFS + 0x03u))
330 
331 /* Bus Clock register */
332 #define MCHP_I2C_BUS_CLK(ba) REG32_OFS(ba, MCHP_I2C_BUS_CLK_OFS)
333 #define MCHP_I2C_BUS_CLK_LO_PERIOD(ba) \
334 	REG8_OFS(ba, (MCHP_I2C_BUS_CLK_OFS + 0x00u))
335 #define MCHP_I2C_BUS_CLK_HI_PERIOD(ba) \
336 	REG8_OFS(ba, (MCHP_I2C_BUS_CLK_OFS + 0x01u))
337 
338 /* Bit-Bang Control register */
339 #define MCHP_I2C_BB_CTRL(ba) REG8_OFS(ba, MCHP_I2C_BB_OFS)
340 
341 /* MCHP Reserved 0x3c register */
342 #define MCHP_I2C_RSVD_3C(ba) REG8_OFS(ba, MCHP_I2C_RSVD_3C)
343 
344 /* Data Timing register */
345 #define MCHP_I2C_DATA_TM(ba) REG32_OFS(ba, MCHP_I2C_DATA_TM_OFS)
346 
347 /* Timeout Scaling register */
348 #define MCHP_I2C_TMTSC(ba) REG32_OFS(ba, MCHP_I2C_TMTSC_OFS)
349 
350 /* Wake Status register */
351 #define MCHP_I2C_WAKE_STS(ba) REG8_OFS(ba, MCHP_I2C_WAKE_STS_OFS)
352 
353 /* Wake Enable register */
354 #define MCHP_I2C_WAKE_ENABLE(ba) REG8_OFS(ba, MCHP_I2C_WAKE_EN_OFS)
355 
356 /* Captured Slave Address */
357 #define MCHP_I2C_SLV_ADDR(ba) REG8_OFS(ba, MCHP_I2C_SLV_ADDR_OFS)
358 
359 /* Promiscuous Interrupt Status */
360 #define MCHP_I2C_PROM_ISTS(ba) REG8_OFS(ba, MCHP_I2C_PROM_INTR_STS_OFS)
361 
362 /* Promiscuous Interrupt Enable */
363 #define MCHP_I2C_PROM_IEN(ba) REG8_OFS(ba, MCHP_I2C_PROM_INTR_EN_OFS)
364 
365 /* Promiscuous Interrupt Control */
366 #define MCHP_I2C_PROM_CTLR(ba) REG8_OFS(ba, MCHP_I2C_PROM_CTRL_OFS)
367 
368 /* =========================================================================*/
369 /* ================	       SMB			   ================ */
370 /* =========================================================================*/
371 
372 /**
373   * @brief SMBus Network Layer Block (SMB)
374   */
375 typedef struct i2c_regs
376 {		/*!< (@ 0x40004000) SMB Structure	 */
377 	__IOM uint8_t CTRLSTS;	/*!< (@ 0x00000000) I2C Status(RO), Control(WO) */
378 	uint8_t RSVD1[3];
379 	__IOM uint32_t OWN_ADDR;	/*!< (@ 0x00000004) I2C Own address */
380 	__IOM uint8_t I2CDATA;	/*!< (@ 0x00000008) I2C I2C Data */
381 	uint8_t RSVD2[15];
382 	__IOM uint8_t RSHTM;	/*!< (@ 0x00000018) I2C Repeated-Start hold time */
383 	uint8_t RSVD3[7];
384 	__IOM uint32_t COMPL;	/*!< (@ 0x00000020) I2C Completion */
385 	uint8_t RSVD4[4];
386 	__IOM uint32_t CFG;	/*!< (@ 0x00000028) I2C Configuration */
387 	__IOM uint32_t BUSCLK;	/*!< (@ 0x0000002c) I2C Bus Clock */
388 	__IOM uint8_t BLKID;	/*!< (@ 0x00000030) I2C Block ID */
389 	uint8_t RSVD5[3];
390 	__IOM uint8_t BLKREV;	/*!< (@ 0x00000034) I2C Block revision */
391 	uint8_t RSVD6[3];
392 	__IOM uint8_t BBCTRL;	/*!< (@ 0x00000038) I2C Bit-Bang control */
393 	uint8_t RSVD7[7];
394 	__IOM uint32_t DATATM;	/*!< (@ 0x00000040) I2C Data timing */
395 	__IOM uint32_t TMOUTSC;	/*!< (@ 0x00000044) I2C Time-out scaling */
396 	uint8_t RSVD8[0x60u - 0x48u];
397 	__IOM uint8_t WAKE_STS;	/*!< (@ 0x00000060) I2C Wake status */
398 	uint8_t RSVD9[3];
399 	__IOM uint8_t WAKE_EN;	/*!< (@ 0x00000064) I2C Wake enable */
400 	uint8_t RSVD10[4];
401 	__IOM uint8_t SLV_ADDR;	/*!< (@ 0x0000006c) I2C Slave Address */
402 	uint8_t RSVD11[3];
403 	__IOM uint8_t PROM_INTR_STS;	/*!< (@ 0x00000070) I2C Promiscuous Interrupt Status */
404 	uint8_t RSVD12[3];
405 	__IOM uint8_t PROM_INTR_EN;	/*!< (@ 0x00000074) I2C Promiscuous Interrupt Enable */
406 	uint8_t RSVD13[3];
407 	__IOM uint8_t PROM_CTRL;	/*!< (@ 0x00000078) I2C Promiscuous Interrupt Enable */
408 	uint8_t RSVD14[3];
409 } I2C_Type;
410 
411 #endif				// #ifndef _I2C_H
412 /* end i2c.h */
413 /**   @}
414  */
415