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Searched refs:read32 (Results 1 – 8 of 8) sorted by relevance

/hal_intel-latest/bsp_sedi/soc/intel_ish/pm/aon/
Daon_task.c332 uint32_t pmu_sram_val = read32(PMU_SRAM_PG_EN); in sram_toggle_tile()
339 while (!(pmu_toggle_bit & read32(PMU_SRAM_PWR_STATUS))) in sram_toggle_tile()
346 while ((pmu_toggle_bit & read32(PMU_SRAM_PWR_STATUS))) in sram_toggle_tile()
367 while (read32(ISH_SRAM_CTRL_ERASE_CTRL) & 0x1) in sram_toggle_bank()
375 write32(ISH_SRAM_CTRL_INTR, read32(ISH_SRAM_CTRL_INTR)); in sram_toggle_bank()
392 #define BANK_PG_STATUS(i) (read32(PMU_SRAM_PG_EN) & (0x1 << (i)))
395 #define BANK_PG_ENABLE(i) (write32(PMU_SRAM_PG_EN, (read32(PMU_SRAM_PG_EN) | (0x1 << (i)))))
399 (write32(PMU_SRAM_PG_EN, (read32(PMU_SRAM_PG_EN) & (~(0x1 << (i))))))
405 #define BANK_DISABLE_STATUS(i) (read32(ISH_SRAM_CTRL_CSFGR) & (0x1 << ((i) + 4)))
410 (read32(ISH_SRAM_CTRL_CSFGR) & (~(0x1 << ((i) + 4))))))
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/hal_intel-latest/bsp_sedi/soc/intel_ish/pm/
Dish_pm.c72 write32(CCU_RST_HST, read32(CCU_RST_HST)); in pg_exit_restore_hw()
106 if (read32(ISH_GPIO_GIMR) & BIT(i) && read32(ISH_GPIO_GRER) & BIT(i) && in convert_both_edge_gpio_to_single_edge()
107 read32(ISH_GPIO_GFER) & BIT(i)) { in convert_both_edge_gpio_to_single_edge()
111 if (read32(ISH_GPIO_GPLR) & BIT(i)) { in convert_both_edge_gpio_to_single_edge()
113 write32(ISH_GPIO_GRER, read32(ISH_GPIO_GRER) & ~BIT(i)); in convert_both_edge_gpio_to_single_edge()
116 write32(ISH_GPIO_GFER, read32(ISH_GPIO_GFER) & ~BIT(i)); in convert_both_edge_gpio_to_single_edge()
126 write32(ISH_GPIO_GRER, read32(ISH_GPIO_GRER) | both_edge_pin_map); in restore_both_edge_gpio_config()
127 write32(ISH_GPIO_GFER, read32(ISH_GPIO_GFER) | both_edge_pin_map); in restore_both_edge_gpio_config()
260 aon_share->uma_msb = read32(IPC_UMA_RANGE_LOWER_1); in init_aon_task()
389 write32(CCU_BCG_MIA, read32(CCU_BCG_MIA) | CCU_BCG_BIT_MIA); in enter_d0i1()
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Dish_dma.c23 if ((read32(addr) & mask) == expected) { in dma_poll()
68 uma_msb = read32(IPC_UMA_RANGE_LOWER_1); in ish_dma_init()
86 while (!(read32(PMU_VNN_REQ_ACK) & PMU_VNN_REQ_ACK_STATUS)) in ish_dma_copy()
150 if (read32(DMA_EN_REG) & DMA_CH_EN_BIT(channel)) { in ish_dma_disable()
156 while ((read32(DMA_EN_REG) & DMA_CH_EN_BIT(channel)) && in ish_dma_disable()
/hal_intel-latest/zephyr/iut_test/test_zephyr/gpio/
Dtest_gpio.c23 iut_print("GPLR register is 0x%x\n", read32(regs + 0x4)); in dump_gpio_regs()
24 iut_print("GPDR register is 0x%x\n", read32(regs + 0x1C)); in dump_gpio_regs()
25 iut_print("GRER register is 0x%x\n", read32(regs + 0x64)); in dump_gpio_regs()
26 iut_print("GFER register is 0x%x\n", read32(regs + 0x7c)); in dump_gpio_regs()
27 iut_print("GIMR register is 0x%x\n", read32(regs + 0xac)); in dump_gpio_regs()
28 iut_print("GISR register is 0x%x\n", read32(regs + 0xc4)); in dump_gpio_regs()
/hal_intel-latest/bsp_sedi/soc/intel_ish/
Dsedi_soc.c52 while (!(read32(PMU_VNN_REQ_ACK) & PMU_VNN_REQ_ACK_STS)) in PM_VNN_DRIVER_REQ()
69 write32(PMU_VNN_REQ_ACK, read32(PMU_VNN_REQ_ACK)); in PM_VNN_DRIVER_DEREQ()
78 write32(PMU_VNN_REQ_31_0, read32(PMU_VNN_REQ_31_0)); in PM_VNN_ALL_RESET()
79 write32(PMU_VNN_REQ_ACK, read32(PMU_VNN_REQ_ACK)); in PM_VNN_ALL_RESET()
92 write32(PMU_VNN_REQ_31_0, read32(PMU_VNN_REQ_31_0) & BIT(vnn_id)); in PM_VNN_DRIVER_RESET()
/hal_intel-latest/bsp_sedi/drivers/rtc/
Dsedi_rtc.c64 upper = read32(SEDI_RTC_COUNTER1); in sedi_rtc_get()
65 lower = read32(SEDI_RTC_COUNTER0); in sedi_rtc_get()
66 } while (upper != read32(SEDI_RTC_COUNTER1)); in sedi_rtc_get()
/hal_intel-latest/bsp_sedi/include/driver/
Dsedi_driver_common.h360 static inline uint32_t read32(IN uint32_t addr) in read32() function
393 write32(address, read32(address) | (smask))
396 write32(address, read32(address) & ~(cmask))
/hal_intel-latest/bsp_sedi/soc/intel_ish/include/
Dsedi_driver_core.h68 return read32(SEDI_IOAPIC_WDW); in read_ioapic_reg()
119 if (!(read32(SEDI_IOAPIC_WDW) & SEDI_IOAPIC_REDTBL_MASK)) { in sedi_core_get_irq_map()