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Searched refs:BIT (Results 1 – 12 of 12) sorted by relevance

/hal_intel-latest/bsp_sedi/soc/intel_ish/pm/
Dpm_regs.h12 #ifndef BIT
13 #define BIT(x) (1U << (x)) macro
27 #define PMU_HOST_RST_B BIT(0)
29 #define PMU_PCE_PG_ALLOWED BIT(4)
30 #define PMU_PCE_CHANGE_MASK BIT(9)
31 #define PMU_PCE_CHANGE_DETECTED BIT(8)
32 #define PMU_PCE_PMCRE BIT(0)
33 #define PMU_SW_PG_REQ_B_VAL BIT(0)
34 #define PMU_SW_PG_REQ_B_RISE BIT(1)
35 #define PMU_SW_PG_REQ_B_FALL BIT(2)
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Dish_dma.h22 #define DST_IS_DRAM BIT(0)
23 #define SRC_IS_DRAM BIT(1)
24 #define NON_SNOOP BIT(2)
Dish_pm.c106 if (read32(ISH_GPIO_GIMR) & BIT(i) && read32(ISH_GPIO_GRER) & BIT(i) && in convert_both_edge_gpio_to_single_edge()
107 read32(ISH_GPIO_GFER) & BIT(i)) { in convert_both_edge_gpio_to_single_edge()
109 both_edge_pins |= BIT(i); in convert_both_edge_gpio_to_single_edge()
111 if (read32(ISH_GPIO_GPLR) & BIT(i)) { in convert_both_edge_gpio_to_single_edge()
113 write32(ISH_GPIO_GRER, read32(ISH_GPIO_GRER) & ~BIT(i)); in convert_both_edge_gpio_to_single_edge()
116 write32(ISH_GPIO_GFER, read32(ISH_GPIO_GFER) & ~BIT(i)); in convert_both_edge_gpio_to_single_edge()
/hal_intel-latest/bsp_sedi/include/driver/
Dsedi_driver_ipc.h95 #define IPC_IS_BUSY(drbl) ((drbl) & BIT(IPC_DRBL_BUSY_OFFS))
96 #define IPC_SET_BUSY(drbl) ((drbl) | BIT(IPC_DRBL_BUSY_OFFS))
111 #define IPC_CSR_RESET_ENTRY BIT(0)
112 #define IPC_CSR_RESET_EXIT BIT(1)
113 #define IPC_CSR_QUERY BIT(2)
114 #define IPC_CSR_ASSERT_VALID BIT(3)
115 #define IPC_CSR_ACKED_VALID BIT(4)
116 #define IPC_CSR_DEASSERT_VALID BIT(5)
117 #define IPC_CSR_SRAM_CLAIM BIT(31)
Dsedi_driver_uart.h32 SEDI_UART_RX_OE = BIT(1), /**< Receiver overrun. */
33 SEDI_UART_RX_PE = BIT(2), /**< Parity error. */
34 SEDI_UART_RX_FE = BIT(3), /**< Framing error. */
35 SEDI_UART_RX_BI = BIT(4), /**< Break interrupt. */
36 SEDI_UART_TX_BUSY = BIT(5), /**< TX Busy flag. */
37 SEDI_UART_RX_BUSY = BIT(6), /**< RX Busy flag. */
38 SEDI_UART_TX_NFULL = BIT(7), /**< TX FIFO not full. */
39 SEDI_UART_RX_NEMPTY = BIT(8), /**< RX FIFO not empty. */
40 SEDI_UART_UNHANDLED_INT = BIT(9) /**< Unhandled Interrupt. */
Dsedi_driver_common.h31 #ifndef BIT
32 #define BIT(x) (1U << (x)) macro
/hal_intel-latest/bsp_sedi/drivers/dma/
Dsedi_dma_ann_1p0.c21 #define DMA_WRITE_ENABLE(i) (BIT(i) | BIT(DMA_CHANNEL_NUM + i))
22 #define DMA_WRITE_DISABLE(i) BIT(DMA_CHANNEL_NUM + i)
121 dma_context[dma_device].vnn_status |= BIT(channel_id); in dma_vnn_req()
129 if (dma_context[dma_device].vnn_status & (BIT(channel_id))) { in dma_vnn_dereq()
130 dma_context[dma_device].vnn_status &= (~BIT(channel_id)); in dma_vnn_dereq()
171 regs->int_reg.clear_tfr_low = BIT(channel_id); in clear_channel_interrupt()
172 regs->int_reg.clear_block_low = BIT(channel_id); in clear_channel_interrupt()
173 regs->int_reg.clear_src_trans_low = BIT(channel_id); in clear_channel_interrupt()
174 regs->int_reg.clear_dst_trans_low = BIT(channel_id); in clear_channel_interrupt()
175 regs->int_reg.clear_err_low = BIT(channel_id); in clear_channel_interrupt()
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/hal_intel-latest/bsp_sedi/soc/intel_ish/
Dsedi_soc.c47 write32(PMU_VNN_REQ_31_0, BIT(vnn_id)); in PM_VNN_DRIVER_REQ()
68 write32(PMU_VNN_REQ_31_0, BIT(vnn_id)); in PM_VNN_DRIVER_DEREQ()
92 write32(PMU_VNN_REQ_31_0, read32(PMU_VNN_REQ_31_0) & BIT(vnn_id)); in PM_VNN_DRIVER_RESET()
/hal_intel-latest/bsp_sedi/drivers/hpet/
Dsedi_hpet.c269 if (!(SEDI_REG_GET(HPET, GIS_LOW) & BIT(timer_id))) in sedi_hpet_timer_int_handler()
273 sedi_hpet_set_int_status(BIT(timer_id)); in sedi_hpet_timer_int_handler()
319 sedi_hpet_set_int_status(BIT(timer_id)); in sedi_hpet_kill_timer()
/hal_intel-latest/bsp_sedi/soc/intel_ish/include/
Dsedi_soc.h91 #define PMU_VNN_REQ_ACK_STS BIT(0)
/hal_intel-latest/zephyr/iut_test/test_zephyr/gpio/
Dtest_gpio.c106 gpio_init_callback(&gp_cb, test_callback, BIT(GPIO_LOOP_INPUT)); in test_gpio_loopback()
/hal_intel-latest/bsp_sedi/drivers/usart/
Dsedi_dw_uart.c1151 regs->rbr_thr_dll = (BIT(8) | (uint32_t)address); in sedi_uart_9bit_send_address()