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Searched refs:write32 (Results 1 – 7 of 7) sorted by relevance

/hal_intel-3.7.0/bsp_sedi/soc/intel_ish/pm/
Dish_pm.c43 write32(SEDI_IREG_BASE(UART, 0) + LCR, 0x80); in uart_to_idle()
44 write32(SEDI_IREG_BASE(UART, 0) + DLL, 0x1); in uart_to_idle()
45 write32(SEDI_IREG_BASE(UART, 0) + DLH, 0x0); in uart_to_idle()
46 write32(SEDI_IREG_BASE(UART, 0) + LCR, 0); in uart_to_idle()
49 write32(SEDI_IREG_BASE(UART, 1) + LCR, 0x80); in uart_to_idle()
50 write32(SEDI_IREG_BASE(UART, 1) + DLL, 0x1); in uart_to_idle()
51 write32(SEDI_IREG_BASE(UART, 1) + DLH, 0x0); in uart_to_idle()
52 write32(SEDI_IREG_BASE(UART, 1) + LCR, 0); in uart_to_idle()
55 write32(SEDI_IREG_BASE(UART, 2) + LCR, 0x80); in uart_to_idle()
56 write32(SEDI_IREG_BASE(UART, 2) + DLL, 0x1); in uart_to_idle()
[all …]
Dish_dma.c55 write32(DMA_PSIZE_01, (DMA_PSIZE_UPDATE | in dma_configure_psize()
85 write32(PMU_VNN_REQ, (1 << VNN_ID_DMA(chan))); in ish_dma_copy()
95 write32(MISC_CHID_CFG_REG, chan); /* Set channel to configure */ in ish_dma_copy()
98 write32(MISC_DMA_CTL_REG(chan), mode); /* Set transfer direction */ in ish_dma_copy()
100 write32(DMA_CFG_REG, DMA_ENABLE); /* Enable DMA module */ in ish_dma_copy()
101 write32(DMA_LLP(chan_reg), 0); /* Linked lists are not used */ in ish_dma_copy()
102 write32(DMA_CTL_LOW(chan_reg), in ish_dma_copy()
121 write32(MISC_CHID_CFG_REG, chan); /* Set channel to configure */ in ish_dma_copy()
122 write32(DMA_CTL_HIGH(chan_reg), chunk); /* Set number of bytes to transfer */ in ish_dma_copy()
123 write32(DMA_DAR(chan_reg), dst); /* Destination address */ in ish_dma_copy()
[all …]
Dish_pm.h60 write32(ISH_RST_REG, 0); in ish_mia_reset()
61 write32(ISH_RST_REG, 1); in ish_mia_reset()
/hal_intel-3.7.0/bsp_sedi/soc/intel_ish/pm/aon/
Daon_task.c29 write32(SEDI_IOAPIC_EOI, SEDI_VEC_PMU2IOAPIC); in pmu_wakeup_isr()
30 write32(LAPIC_EOI, 0x0); in pmu_wakeup_isr()
41 write32(PMU_RST_PREP, PMU_RST_PREP_INT_MASK); in reset_prep_isr()
47 write32(SEDI_IOAPIC_EOI, SEDI_VEC_RESET_PREP); in reset_prep_isr()
48 write32(LAPIC_EOI, 0x0); in reset_prep_isr()
198 write32(CCU_BCG_DMA, 1); in enable_dma_bcg()
203 write32(CCU_BCG_DMA, 0); in disable_dma_bcg()
335 write32(PMU_SRAM_PG_EN, pmu_sram_val); in sram_toggle_tile()
342 write32(PMU_SRAM_PG_EN, pmu_sram_val); in sram_toggle_tile()
360 write32(ISH_SRAM_CTRL_ERASE_ADDR, in sram_toggle_bank()
[all …]
/hal_intel-3.7.0/bsp_sedi/soc/intel_ish/
Dsedi_soc.c47 write32(PMU_VNN_REQ_31_0, BIT(vnn_id)); in PM_VNN_DRIVER_REQ()
68 write32(PMU_VNN_REQ_31_0, BIT(vnn_id)); in PM_VNN_DRIVER_DEREQ()
69 write32(PMU_VNN_REQ_ACK, read32(PMU_VNN_REQ_ACK)); in PM_VNN_DRIVER_DEREQ()
78 write32(PMU_VNN_REQ_31_0, read32(PMU_VNN_REQ_31_0)); in PM_VNN_ALL_RESET()
79 write32(PMU_VNN_REQ_ACK, read32(PMU_VNN_REQ_ACK)); in PM_VNN_ALL_RESET()
92 write32(PMU_VNN_REQ_31_0, read32(PMU_VNN_REQ_31_0) & BIT(vnn_id)); in PM_VNN_DRIVER_RESET()
/hal_intel-3.7.0/bsp_sedi/soc/intel_ish/include/
Dsedi_driver_core.h61 write32(SEDI_IOAPIC_IDX, (unsigned char)reg); in write_ioapic_reg()
62 write32(SEDI_IOAPIC_WDW, val); in write_ioapic_reg()
67 write32(SEDI_IOAPIC_IDX, (unsigned char)reg); in read_ioapic_reg()
118 write32(SEDI_IOAPIC_IDX, SEDI_IOAPIC_IOREDTBL + pin * 2); in sedi_core_get_irq_map()
/hal_intel-3.7.0/bsp_sedi/include/driver/
Dsedi_driver_common.h381 static inline void write32(uint32_t addr, IN uint32_t val) in write32() function
393 write32(address, read32(address) | (smask))
396 write32(address, read32(address) & ~(cmask))