Searched refs:regs (Results 1 – 5 of 5) sorted by relevance
| /hal_intel-3.6.0/bsp_sedi/drivers/usart/ |
| D | sedi_dw_uart.c | 207 sedi_uart_regs_t *const regs = SEDI_UART[ctxt->uart]; in sedi_dma_event_cb() local
208 uint32_t line_err_status = (regs->lsr & BSETS_UART_LSR_ERROR); in sedi_dma_event_cb()
227 while (!(regs->lsr & SEDI_RBFVM(UART, LSR, TEMT, ENABLED))) { in sedi_dma_event_cb()
297 sedi_uart_regs_t *const regs = SEDI_UART[uart]; in io_vec_write_callback() local
305 while (!(regs->lsr & SEDI_RBFVM(UART, LSR, TEMT, ENABLED))) { in io_vec_write_callback()
308 regs->iir_fcr = (SEDI_RBFM(UART, IIR, FIFOE) | SEDI_UART_FCR_TX_0_RX_1_2_THRESHOLD); in io_vec_write_callback()
311 regs->ier_dlh |= SEDI_RBFVM(UART, IER, ETBEI, ENABLE); in io_vec_write_callback()
337 sedi_uart_regs_t *const regs = SEDI_UART[uart]; in io_vec_read_callback() local
345 regs->iir_fcr = in io_vec_read_callback()
352 regs->ier_dlh |= SEDI_RBFVM(UART, IER, ERBFI, ENABLE) | SEDI_RBFVM(UART, IER, ELSI, ENABLE); in io_vec_read_callback()
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| /hal_intel-3.6.0/bsp_sedi/drivers/ipc/ |
| D | sedi_ipc.c | 154 volatile sedi_ipc_regs_t *regs = ipc_resource[ipc_device].reg_base_addr; in sedi_ipc_init() local
172 ®s->ish2agent_doorbell_agent)) { in sedi_ipc_init()
175 ®s->ish2agent_doorbell_agent); in sedi_ipc_init()
182 ®s->ish_ipc_busy_clear_agent)) { in sedi_ipc_init()
185 ISH2AGENT_BUSY_CLEAR, 1, ®s->ish_ipc_busy_clear_agent); in sedi_ipc_init()
188 SEDI_PREG_RBFV_SET(IPC, PIMR_AGENT2ISH, AGENT2ISH_DB, 1, ®s->pimr_agent2ish); in sedi_ipc_init()
189 SEDI_PREG_RBFV_SET(IPC, PIMR_AGENT2ISH, ISH2AGENT_BC, 1, ®s->pimr_agent2ish); in sedi_ipc_init()
190 SEDI_PREG_RBFV_SET(IPC, PIMR_ISH2AGENT, ISH2AGENT_DB, 1, ®s->pimr_ish2agent); in sedi_ipc_init()
191 SEDI_PREG_RBFV_SET(IPC, CIM_AGENT, CH_INTR_MASK, 0, ®s->cim_agent); in sedi_ipc_init()
199 volatile sedi_ipc_regs_t *regs = ipc_resource[ipc_device].reg_base_addr; in sedi_ipc_uninit() local
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| /hal_intel-3.6.0/bsp_sedi/drivers/dma/ |
| D | sedi_dma_ann_1p0.c | 84 dma_ann_1p0_regs_t *regs; /* register interface*/ member
91 { .regs = (dma_ann_1p0_regs_t *)SEDI_IREG_BASE(DMA, 0) },
151 volatile dma_ann_1p0_regs_t *regs = resources[dma_device].regs; in mask_channel_interrupt() local
153 regs->int_reg.mask_tfr_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
154 regs->int_reg.mask_block_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
155 regs->int_reg.mask_src_trans_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
156 regs->int_reg.mask_dst_trans_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
157 regs->int_reg.mask_err_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
163 volatile dma_ann_1p0_regs_t *regs = resources[dma_device].regs; in clear_channel_interrupt() local
165 regs->int_reg.clear_tfr_low = BIT(channel_id); in clear_channel_interrupt()
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| /hal_intel-3.6.0/zephyr/iut_test/test_zephyr/gpio/ |
| D | test_gpio.c | 21 uint32_t regs = SEDI_IREG_BASE(GPIO, 0); in dump_gpio_regs() local
23 iut_print("GPLR register is 0x%x\n", read32(regs + 0x4)); in dump_gpio_regs()
24 iut_print("GPDR register is 0x%x\n", read32(regs + 0x1C)); in dump_gpio_regs()
25 iut_print("GRER register is 0x%x\n", read32(regs + 0x64)); in dump_gpio_regs()
26 iut_print("GFER register is 0x%x\n", read32(regs + 0x7c)); in dump_gpio_regs()
27 iut_print("GIMR register is 0x%x\n", read32(regs + 0xac)); in dump_gpio_regs()
28 iut_print("GISR register is 0x%x\n", read32(regs + 0xc4)); in dump_gpio_regs()
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| /hal_intel-3.6.0/bsp_sedi/drivers/i2c/ |
| D | sedi_i2c_dw_apb_200a.c | 1213 sedi_i2c_regs_t *regs = (void *)context->base; in i2c_isr_complete() local
1238 val = regs->clr_intr; in i2c_isr_complete()
1250 sedi_i2c_regs_t *regs = (void *)context->base; in sedi_i2c_isr_handler() local
1259 stat = regs->intr_stat; in sedi_i2c_isr_handler()
1281 val = regs->clr_stop_det; in sedi_i2c_isr_handler()
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