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Searched refs:speed (Results 1 – 2 of 2) sorted by relevance

/hal_intel-3.5.0/bsp_sedi/drivers/i2c/
Dsedi_i2c_dw_apb_200a.c100 int speed; member
132 .base = SEDI_I2C_##x##_REG_BASE, .dma_handshake = 0xff, .speed = I2C_SPEED_FAST, \
215 static int dw_i2c_config_speed(uint32_t base, int speed, in dw_i2c_config_speed() argument
224 i2c->con = BSETS_MASTER_DEFAULT | regval_speed[speed]; in dw_i2c_config_speed()
231 switch (speed) { in dw_i2c_config_speed()
603 context->speed = I2C_SPEED_STANDARD; in sedi_i2c_init()
605 dw_i2c_config_speed(context->base, context->speed, context->clk_info); in sedi_i2c_init()
635 dw_i2c_config_speed(context->base, context->speed, in sedi_i2c_set_power()
1132 context->speed = I2C_SPEED_STANDARD; in sedi_i2c_control()
1135 context->speed = I2C_SPEED_FAST; in sedi_i2c_control()
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/hal_intel-3.5.0/docs/
Dbsp_sedi_doxyfile458 # the optimal cache size from a speed point of view.
467 # speed. At this moment only the input processing can be done using multiple
2320 # speed.