Searched refs:regs (Results 1 – 4 of 4) sorted by relevance
| /hal_intel-3.5.0/bsp_sedi/drivers/usart/ |
| D | sedi_dw_uart.c | 207 sedi_uart_regs_t *const regs = SEDI_UART[ctxt->uart]; in sedi_dma_event_cb() local
208 uint32_t line_err_status = (regs->lsr & BSETS_UART_LSR_ERROR); in sedi_dma_event_cb()
227 while (!(regs->lsr & SEDI_RBFVM(UART, LSR, TEMT, ENABLED))) { in sedi_dma_event_cb()
297 sedi_uart_regs_t *const regs = SEDI_UART[uart]; in io_vec_write_callback() local
305 while (!(regs->lsr & SEDI_RBFVM(UART, LSR, TEMT, ENABLED))) { in io_vec_write_callback()
308 regs->iir_fcr = (SEDI_RBFM(UART, IIR, FIFOE) | SEDI_UART_FCR_TX_0_RX_1_2_THRESHOLD); in io_vec_write_callback()
311 regs->ier_dlh |= SEDI_RBFVM(UART, IER, ETBEI, ENABLE); in io_vec_write_callback()
337 sedi_uart_regs_t *const regs = SEDI_UART[uart]; in io_vec_read_callback() local
345 regs->iir_fcr = in io_vec_read_callback()
352 regs->ier_dlh |= SEDI_RBFVM(UART, IER, ERBFI, ENABLE) | SEDI_RBFVM(UART, IER, ELSI, ENABLE); in io_vec_read_callback()
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| /hal_intel-3.5.0/bsp_sedi/drivers/ipc/ |
| D | sedi_ipc.c | 129 volatile ipc_reg_t *regs = ipc_resource[ipc_device].reg_base_addr; in sedi_ipc_init() local
146 if ((regs->drbl_out & BIT(IPC_BUSY_BIT)) != 0) { in sedi_ipc_init()
147 regs->pimr_out &= ~BIT(IPC_INT_MASK_OUT_BIT); in sedi_ipc_init()
149 regs->drbl_out = 0; in sedi_ipc_init()
154 if (regs->ipc_busy_clear_peer2local) { in sedi_ipc_init()
156 regs->ipc_busy_clear_peer2local = 1; in sedi_ipc_init()
159 regs->pimr_in |= (BIT(IPC_INT_MASK_IN_BIT) | BIT(IPC_INT_MASK_BC_BIT)); in sedi_ipc_init()
160 regs->pimr_out |= BIT(IPC_INT_MASK_OUT_BIT); in sedi_ipc_init()
161 regs->channel_intr_mask = 0; in sedi_ipc_init()
169 volatile ipc_reg_t *regs = ipc_resource[ipc_device].reg_base_addr; in sedi_ipc_uninit() local
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| /hal_intel-3.5.0/bsp_sedi/drivers/dma/ |
| D | sedi_dma_ann_1p0.c | 84 dma_ann_1p0_regs_t *regs; /* register interface*/ member
91 { .regs = (dma_ann_1p0_regs_t *)SEDI_DMA_0_REG_BASE },
151 volatile dma_ann_1p0_regs_t *regs = resources[dma_device].regs; in mask_channel_interrupt() local
153 regs->int_reg.mask_tfr_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
154 regs->int_reg.mask_block_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
155 regs->int_reg.mask_src_trans_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
156 regs->int_reg.mask_dst_trans_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
157 regs->int_reg.mask_err_low = DMA_WRITE_DISABLE(channel_id); in mask_channel_interrupt()
163 volatile dma_ann_1p0_regs_t *regs = resources[dma_device].regs; in clear_channel_interrupt() local
165 regs->int_reg.clear_tfr_low = BIT(channel_id); in clear_channel_interrupt()
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| /hal_intel-3.5.0/bsp_sedi/drivers/i2c/ |
| D | sedi_i2c_dw_apb_200a.c | 1239 sedi_i2c_regs_t *regs = (void *)context->base; in i2c_isr_complete() local
1260 val = regs->clr_intr; in i2c_isr_complete()
1272 sedi_i2c_regs_t *regs = (void *)context->base; in sedi_i2c_isr_handler() local
1281 stat = regs->intr_stat; in sedi_i2c_isr_handler()
1303 val = regs->clr_stop_det; in sedi_i2c_isr_handler()
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