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Searched refs:SEDI_CCU_BASE (Results 1 – 2 of 2) sorted by relevance

/hal_intel-3.5.0/bsp_sedi/soc/intel_ish/pm/
Dpm_regs.h92 #define CCU_TCG_EN (SEDI_CCU_BASE + 0x0)
93 #define CCU_BCG_EN (SEDI_CCU_BASE + 0x4)
94 #define CCU_WDT_CD (SEDI_CCU_BASE + 0x7c)
95 #define CCU_RST_HST (SEDI_CCU_BASE + 0x3c)
96 #define CCU_TCG_ENABLE (SEDI_CCU_BASE + 0x40)
97 #define CCU_BCG_ENABLE (SEDI_CCU_BASE + 0x44)
98 #define CCU_BCG_MIA (SEDI_CCU_BASE + 0x4)
99 #define CCU_BCG_UART (SEDI_CCU_BASE + 0x8)
100 #define CCU_BCG_I2C (SEDI_CCU_BASE + 0xc)
101 #define CCU_BCG_SPI (SEDI_CCU_BASE + 0x10)
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/hal_intel-3.5.0/bsp_sedi/soc/intel_ish/include/
Dsedi_soc_regs.h112 #define SEDI_CCU_BASE 0x04300000 macro