1 /*
2  * Copyright (c) 2023 Intel Corporation
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef _SPI_BSP_H_
8 #define _SPI_BSP_H_
9 
10 #include <sedi_driver_spi.h>
11 #include "sedi_driver_dma.h"
12 
13 #define BITMASK(b, a) ((BIT(b - a + 1) - 1) << a)
14 
15 /******************************************************************************
16  * RTL configuration
17  *****************************************************************************/
18 
19 #define SSI_NUM_SLAVES (1)
20 #define SSI_TX_ABW (16)
21 #define SSI_PRESCALE_MIN (2)
22 #define SSI_FIFO_DEPTH_MIN (2)
23 #define SSI_FIFO_DEPTH (64)
24 
25 /******************************************************************************
26  * LLD interface
27  *****************************************************************************/
28 
29 #define REG_VERSION (0x3430312A)
30 
31 #define REG_INT_ERROR (BIT(1) | BIT(2) | BIT(3))
32 #define REG_INT_TX BIT(0)
33 #define REG_INT_RX BIT(4)
34 #define REG_INT_NONE (0)
35 
36 #define REG_SR_BUSY BIT(0)
37 #define REG_SR_TX_EMPTY BIT(2)
38 #define REG_SR_TX_NOT_FULL BIT(1)
39 #define REG_SR_RX_NOT_EMPTY BIT(3)
40 #define REG_SR_ERROR BIT(5)
41 
42 #define REG_DMA_ENABLE (BIT(0) | BIT(1))
43 #define REG_INT_ENABLE (0x1F)
44 
45 #ifdef SPI_DW_2_0
46 #define REG_CTRL0_CPHA BIT(8)
47 #define REG_CTRL0_CPOL BIT(9)
48 #define REG_CTRL0_LOOPBACK BIT(13)
49 #define REG_CTRL0_SSTE BIT(14)
50 #define SPI_CTRL0_TMOD_MASK (0xC00)
51 #define REG_CTRL0_FRF_MASK (0xC0)
52 #define REG_CTRL0_FRF_TI_SSP (0x40)
53 #define REG_CTRL0_FRF_MICROWIRE (0x80)
54 
55 #define SPI_CTRL0_BOTH_MODE (0)
56 #define SPI_CTRL0_SEND_MODE (1 << 10U)
57 #define SPI_CTRL0_RECEIVE_MODE (2 << 10U)
58 #define SPI_CTRL0_EEPROM_MODE (0)
59 #define SPI_FRAME_FORMAT_MASK (BIT(22) | BIT(23))
60 #define SPI_FRAME_FORMAT_SHIFT (22)
61 #define SPI_TXFTLR_TXFTHR_MASK (0xFFFF0000)
62 #define SPI_TXFTLR_TXFTHR_SHIFT (16)
63 #define MASK_CTRL0_WIDTH (0x1F)
64 #define SSI_IC_FREQ (100000000)
65 #else
66 #define REG_CTRL0_CPHA BIT(6)
67 #define REG_CTRL0_CPOL BIT(7)
68 #define REG_CTRL0_LOOPBACK BIT(11)
69 #define REG_CTRL0_SSTE BIT(24)
70 #define SPI_CTRL0_TMOD_MASK (0x300)
71 #define REG_CTRL0_FRF_MASK (0x30)
72 #define REG_CTRL0_FRF_TI_SSP (0x10)
73 #define REG_CTRL0_FRF_MICROWIRE (0x20)
74 
75 #define SPI_CTRL0_BOTH_MODE (0)
76 #define SPI_CTRL0_SEND_MODE (1 << 8U)
77 #define SPI_CTRL0_RECEIVE_MODE (2 << 8U)
78 #define SPI_CTRL0_EEPROM_MODE (0)
79 #define SPI_FRAME_FORMAT_MASK (BIT(21) | BIT(22))
80 #define SPI_FRAME_FORMAT_SHIFT (21)
81 #define MASK_CTRL0_WIDTH (0xF)
82 #define SSI_IC_FREQ (sedi_pm_get_lbw_clock())
83 #endif
84 
85 #define REG_MWCR_MWMOD_SHIFT (0)
86 #define REG_MWCR_MDD_SHIFT (1)
87 #define REG_MWCR_MHS_SHIFT (2)
88 
89 #define OFFSET_CTRL0_WIDTH 0
90 
91 #define SEDI_SPI_DRV_VERSION SEDI_DRIVER_VERSION_MAJOR_MINOR(1, 0)
92 
93 #define SPI_CS_MODE_UNUSED 0
94 #define SPI_CS_MODE_HW 1
95 #define SPI_CS_MODE_SW 2
96 
97 #define SPI_CS_MASK_DEFAULT BIT(0)
98 
99 #define SPI_BITWIDTH_4BITS (4)
100 #define SPI_BITWIDTH_8BITS (8)
101 #define SPI_BITWIDTH_16BITS (16)
102 
103 #define SPI_FRAME_SIZE_1_BYTE (1)
104 #define SPI_FRAME_SIZE_2_BYTES (2)
105 
106 #define SPI_RECEIVE_MODE_MAX_SIZE (65536)
107 #define DEFAULT_PRESCALE (20)
108 
109 #define SPI_CTRLR0_ADDR_L_MASK (0x3C)
110 #define SPI_CTRLR0_ADDR_L_SHIFT (2)
111 #define SPI_CTRLR0_INST_L_MASK (0x300)
112 #define SPI_CTRLR0_INST_L_SHIFT (8)
113 #define SPI_CTRLR0_WAIT_CYCLE_MASK (0xF800)
114 #define SPI_CTRLR0_WAIT_CYCLE_SHIFT (11)
115 
116 #define SPI_DMA_MAX_SIZE (4096)
117 #define SPI_DMA_MAX_SIZE_SHIFT (12)
118 
119 /* SPI transfer mode */
120 typedef enum {
121 	SPI_TRANSFER_MODE_BOTH = 0,
122 	SPI_TRANSFER_MODE_SEND,
123 	SPI_TRANSFER_MODE_RECEIVE,
124 	SPI_TRANSFER_MODE_EEPROM
125 } spi_transfer_mode_t;
126 
127 typedef struct spi_registers {
128 	__IO_RW uint32_t ctrl0;
129 	__IO_RW uint32_t ctrl1;
130 	__IO_RW uint32_t ssienr;
131 	__IO_RW uint32_t mwcr;
132 	__IO_RW uint32_t ser;
133 	__IO_RW uint32_t baudr;
134 	__IO_RW uint32_t txftlr;
135 	__IO_RW uint32_t rxftlr;
136 	__IO_RW uint32_t txflr;
137 	__IO_RW uint32_t rxflr;
138 	__IO_RW uint32_t sr;
139 	__IO_RW uint32_t imr;
140 	__IO_RW uint32_t isr;
141 	__IO_RW uint32_t risr;
142 	__IO_RW uint32_t txoicr;
143 	__IO_RW uint32_t rxoicr;
144 	__IO_RW uint32_t rxuicr;
145 	__IO_RW uint32_t msticr;
146 	__IO_RW uint32_t icr;
147 	__IO_RW uint32_t dmacr;
148 	__IO_RW uint32_t dmatdlr;
149 	__IO_RW uint32_t dmardlr;
150 	__IO_RW uint32_t idr;
151 	__IO_RW uint32_t ssic_version_id;
152 	__IO_RW uint32_t dr;
153 	__IO_RW uint32_t dr_rsvd[35];
154 	__IO_RW uint32_t rx_sample_delay;
155 	__IO_RW uint32_t spi_ctrl0;
156 	__IO_RW uint32_t txd_drive_edge;
157 	__IO_RW uint32_t rsvd;
158 } spi_reg_t;
159 
160 struct spi_context {
161 	/* hardware config */
162 	spi_reg_t *base;
163 	uint32_t dma_handshake;
164 	uint32_t rx_handshake;
165 
166 	/* sedi required */
167 	sedi_spi_capabilities_t capability;
168 	sedi_spi_status_t status;
169 	sedi_spi_event_cb_t cb_event;
170 	void *cb_param;
171 
172 	/* ioctl info */
173 	uint8_t frame_size; /* Frame size in byte */
174 	uint8_t tx_watermark;
175 	uint8_t rx_watermark;
176 	uint32_t prescale;
177 	uint32_t dummy_data;
178 	bool is_lsb;
179 	bool is_cs_continuous;
180 
181 	/* transfer info */
182 	spi_transfer_mode_t transfer_mode;
183 	uint8_t *data_tx;
184 	uint8_t *data_rx;
185 	uint32_t tx_data_len;
186 	uint32_t rx_data_len;
187 	uint32_t data_tx_idx;
188 	uint32_t data_rx_idx;
189 
190 	/* For dma transfer */
191 	bool dma_tx_finished;
192 	bool dma_rx_finished;
193 	uint32_t tx_dma;
194 	uint32_t rx_dma;
195 	uint8_t tx_channel;
196 	uint8_t rx_channel;
197 	uint32_t dma_cycles; /* For large data DMA transfer */
198 	uint32_t dma_idx; /* For large data DMA transfer */
199 	uint32_t last_dma_counts; /* For large data DMA transfer */
200 
201 	/* For qspi */
202 	bool is_quad;
203 	const sedi_spi_enhanced_config_t *quad_config;
204 };
205 
206 #endif
207