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Searched refs:PMU_D3_STATUS (Results 1 – 3 of 3) sorted by relevance

/hal_intel-3.5.0/bsp_sedi/soc/intel_ish/pm/
Dish_pm.c503 write32(PMU_D3_STATUS, read32(PMU_D3_STATUS)); in handle_d3()
505 if (read32(PMU_D3_STATUS) & (PMU_D3_BIT_RISING_EDGE_STATUS | PMU_D3_BIT_SET)) { in handle_d3()
580 write32(PMU_D3_STATUS, read32(PMU_D3_STATUS) & (PMU_D3_BIT_SET | PMU_BME_BIT_SET)); in sedi_pm_init()
582 if ((!(read32(PMU_D3_STATUS) & PMU_D3_BIT_SET)) && in sedi_pm_init()
583 (read32(PMU_D3_STATUS) & PMU_BME_BIT_SET)) in sedi_pm_init()
584 write32(PMU_D3_STATUS, read32(PMU_D3_STATUS)); in sedi_pm_init()
Dpm_regs.h24 #define PMU_D3_STATUS (SEDI_PMU_BASE + 0x100) macro
/hal_intel-3.5.0/bsp_sedi/soc/intel_ish/pm/aon/
Daon_task.c491 power_ctrl_enabled = read32(PMU_D3_STATUS); in is_ipapg_allowed()
505 write32(PMU_D3_STATUS, (read32(PMU_D3_STATUS) & (PMU_D0I3_ENABLE_MASK | in is_ipapg_allowed()
508 power_ctrl_enabled = read32(PMU_D3_STATUS); in is_ipapg_allowed()
851 if (read32(PMU_D3_STATUS) & in ish_aon_main()