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Searched refs:LCR (Results 1 – 3 of 3) sorted by relevance

/hal_intel-3.5.0/bsp_sedi/soc/common/include/
Dsedi_uart_regs.h127 SEDI_REG_DEFINE(UART, LCR, 0xc, RW, (uint32_t)0xff, (uint32_t)0x0);
137 SEDI_RBF_DEFINE(UART, LCR, DLS, 0, 2, RW, (uint32_t)0x0);
138 SEDI_RBFV_DEFINE(UART, LCR, DLS, CHAR_5BITS, 0x0);
139 SEDI_RBFV_DEFINE(UART, LCR, DLS, CHAR_6BITS, 0x1);
140 SEDI_RBFV_DEFINE(UART, LCR, DLS, CHAR_7BITS, 0x2);
141 SEDI_RBFV_DEFINE(UART, LCR, DLS, CHAR_8BITS, 0x3);
151 SEDI_RBF_DEFINE(UART, LCR, STOP, 2, 1, RW, (uint32_t)0x0);
152 SEDI_RBFV_DEFINE(UART, LCR, STOP, STOP_1BIT, 0x0);
153 SEDI_RBFV_DEFINE(UART, LCR, STOP, STOP_1_5BIT_OR_2BIT, 0x1);
163 SEDI_RBF_DEFINE(UART, LCR, PEN, 3, 1, RW, (uint32_t)0x0);
[all …]
/hal_intel-3.5.0/bsp_sedi/soc/intel_ish/pm/
Dish_pm.c35 #define LCR 0xC macro
43 write32(SEDI_IREG_BASE(UART, 0) + LCR, 0x80); in uart_to_idle()
46 write32(SEDI_IREG_BASE(UART, 0) + LCR, 0); in uart_to_idle()
49 write32(SEDI_IREG_BASE(UART, 1) + LCR, 0x80); in uart_to_idle()
52 write32(SEDI_IREG_BASE(UART, 1) + LCR, 0); in uart_to_idle()
55 write32(SEDI_IREG_BASE(UART, 2) + LCR, 0x80); in uart_to_idle()
58 write32(SEDI_IREG_BASE(UART, 2) + LCR, 0); in uart_to_idle()
/hal_intel-3.5.0/bsp_sedi/drivers/usart/
Dsedi_dw_uart.c1251 regs->lcr |= SEDI_RBFVM(UART, LCR, DLAB, ENABLED); in sedi_uart_save_context()
1254 regs->lcr &= ~SEDI_RBFVM(UART, LCR, DLAB, ENABLED); in sedi_uart_save_context()
1466 regs->lcr = SEDI_RBFVM(UART, LCR, DLAB, ENABLED); in sedi_uart_set_baud_rate()
1535 regs->lcr |= SEDI_RBFVM(UART, LCR, BC, ENABLED); in sedi_uart_set_break_con()
1545 regs->lcr &= ~SEDI_RBFVM(UART, LCR, BC, ENABLED); in sedi_uart_clr_break_con()