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Searched refs:ISH_SRAM_CTRL_CSFGR (Results 1 – 2 of 2) sorted by relevance

/hal_intel-3.5.0/bsp_sedi/soc/intel_ish/pm/aon/
Daon_task.c402 #define BANK_DISABLE_STATUS(i) (read32(ISH_SRAM_CTRL_CSFGR) & (0x1 << ((i) + 4)))
406 (write32(ISH_SRAM_CTRL_CSFGR, \
407 (read32(ISH_SRAM_CTRL_CSFGR) & (~(0x1 << ((i) + 4))))))
411 (write32(ISH_SRAM_CTRL_CSFGR, \
412 (read32(ISH_SRAM_CTRL_CSFGR) | (0x1 << ((i) + 4)))))
636 sram_cfg_reg = read32(ISH_SRAM_CTRL_CSFGR); in handle_d0i2()
641 write32(ISH_SRAM_CTRL_CSFGR, sram_cfg_reg); in handle_d0i2()
694 sram_cfg_reg = read32(ISH_SRAM_CTRL_CSFGR); in handle_d0i3()
699 write32(ISH_SRAM_CTRL_CSFGR, sram_cfg_reg); in handle_d0i3()
/hal_intel-3.5.0/bsp_sedi/soc/intel_ish/pm/
Dpm_regs.h192 #define ISH_SRAM_CTRL_CSFGR (ISH_SRAM_CTRL_BASE + 0x00) macro