Searched refs:DMA_CHANNEL_NUM (Results 1 – 3 of 3) sorted by relevance
21 #define DMA_WRITE_ENABLE(i) (BIT(i) | BIT(DMA_CHANNEL_NUM + i))22 #define DMA_WRITE_DISABLE(i) BIT(DMA_CHANNEL_NUM + i)70 channel_config_t channel_config[DMA_CHANNEL_NUM];71 sedi_dma_event_cb_t cb_event[DMA_CHANNEL_NUM]; /*event callback*/72 void *cb_param[DMA_CHANNEL_NUM]; /*event callback*/73 sedi_dma_status_t status[DMA_CHANNEL_NUM]; /*status flags*/74 uint32_t done_byte[DMA_CHANNEL_NUM]; /*the transferred byte*/75 dma_linked_list_item_t *next_llp[DMA_CHANNEL_NUM];76 uint32_t flags[DMA_CHANNEL_NUM]; /*control and state flags*/186 DBG_CHECK(channel_id < DMA_CHANNEL_NUM, SEDI_DRIVER_ERROR_PARAMETER); in sedi_dma_init()[all …]
114 __IO_RW uint32_t dma_ctl_ch[DMA_CHANNEL_NUM]; /**< DMA_CTL_CH> */116 __IO_RW uint32_t iosf_addr_fillin_dma_ch[DMA_CHANNEL_NUM];119 __IO_RW uint32_t iosf_dest_addr_fillin_dma_ch[DMA_CHANNEL_NUM];122 __IO_RW uint32_t dma_xbar_sel[DMA_CHANNEL_NUM]; /**< DMA_XBAR_SEL>*/134 __IO_RW dma_chan_reg_t chan_reg[DMA_CHANNEL_NUM];
23 #define DMA_CHANNEL_NUM 8 macro
