Searched refs:writeMask (Results 1 – 2 of 2) sorted by relevance
| /hal_infineon-latest/mtb-pdl-cat1/drivers/source/ |
| D | cy_pra.c | 122 regIndexToAddr[i].writeMask = CY_PRA_REG_POLICY_WRITE_ALL; in Cy_PRA_Init()
137 …regIndexToAddr[CY_PRA_INDX_SRSS_PWR_HIBERNATE].writeMask = (uint32_t) ~ (SRSS_PWR_HIBERNATE_TOKE… in Cy_PRA_Init()
145 regIndexToAddr[CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK].writeMask= CY_PRA_REG_POLICY_WRITE_NONE; in Cy_PRA_Init()
156 regIndexToAddr[CY_PRA_INDX_PROT_MPU_MS_CTL + i].writeMask= CY_PRA_REG_POLICY_WRITE_NONE; in Cy_PRA_Init()
297 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, OUT), 4U)].writeMask = (CY_GPIO_OUT_… in Cy_PRA_InitGpioPort()
298 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, OUT_CLR), 4U)].writeMask = (CY_GPIO_… in Cy_PRA_InitGpioPort()
299 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, OUT_SET), 4U)].writeMask = (CY_GPIO_… in Cy_PRA_InitGpioPort()
300 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, OUT_INV), 4U)].writeMask = (CY_GPIO_… in Cy_PRA_InitGpioPort()
301 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, IN), 4U)].writeMask = (CY_GPIO_IN_MA… in Cy_PRA_InitGpioPort()
302 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, INTR), 4U)].writeMask = (CY_GPIO_INT… in Cy_PRA_InitGpioPort()
[all …]
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| /hal_infineon-latest/mtb-pdl-cat1/drivers/include/ |
| D | cy_pra.h | 681 uint32_t writeMask; /**< The write mask. Zero grants access, one - no access. */ member
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