Home
last modified time | relevance | path

Searched refs:width (Results 1 – 25 of 30) sorted by relevance

12

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_crypto_core_crc_v1.c202 uint32_t width, in Cy_Crypto_Core_V1_Crc_CalcInit() argument
210 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V1_Crc_CalcInit()
227 …int32_t)(_VAL2FLD(CRYPTO_CRC_POL_CTL_POLYNOMIAL, polynomial << (CY_CRYPTO_HW_REGS_WIDTH - width))); in Cy_Crypto_Core_V1_Crc_CalcInit()
232 … (uint32_t)(_VAL2FLD(CRYPTO_CRC_REM_CTL_REM_XOR, remXor << (CY_CRYPTO_HW_REGS_WIDTH - width))); in Cy_Crypto_Core_V1_Crc_CalcInit()
236 …int32_t)(_VAL2FLD(CRYPTO_CRC_LFSR_CTL_LFSR32, lfsrInitState << (CY_CRYPTO_HW_REGS_WIDTH - width))); in Cy_Crypto_Core_V1_Crc_CalcInit()
260 cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcStart(CRYPTO_Type *base, uint32_t width, uint32_t … in Cy_Crypto_Core_V1_Crc_CalcStart() argument
262 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V1_Crc_CalcStart()
266 …int32_t)(_VAL2FLD(CRYPTO_CRC_LFSR_CTL_LFSR32, lfsrInitState << (CY_CRYPTO_HW_REGS_WIDTH - width))); in Cy_Crypto_Core_V1_Crc_CalcStart()
336 cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t … in Cy_Crypto_Core_V1_Crc_CalcFinish() argument
338 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V1_Crc_CalcFinish()
[all …]
Dcy_crypto_core_crc_v2.c200 uint32_t width, in Cy_Crypto_Core_V2_Crc_CalcInit() argument
208 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V2_Crc_CalcInit()
224 …32_t)(_VAL2FLD(CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL, polynomial << (CY_CRYPTO_HW_REGS_WIDTH - width))); in Cy_Crypto_Core_V2_Crc_CalcInit()
229 … (uint32_t)(_VAL2FLD(CRYPTO_V2_CRC_REM_CTL_REM_XOR, remXor << (CY_CRYPTO_HW_REGS_WIDTH - width))); in Cy_Crypto_Core_V2_Crc_CalcInit()
233 … (uint32_t)(_VAL2FLD(CRYPTO_V2_RESULT_DATA, lfsrInitState << (CY_CRYPTO_HW_REGS_WIDTH - width))); in Cy_Crypto_Core_V2_Crc_CalcInit()
257 cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcStart(CRYPTO_Type *base, uint32_t width, uint32_t … in Cy_Crypto_Core_V2_Crc_CalcStart() argument
259 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V2_Crc_CalcStart()
262 … = (uint32_t)(_VAL2FLD(CRYPTO_V2_RESULT_DATA, lfsrInitState << (CY_CRYPTO_HW_REGS_WIDTH - width))); in Cy_Crypto_Core_V2_Crc_CalcStart()
332 cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t … in Cy_Crypto_Core_V2_Crc_CalcFinish() argument
334 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V2_Crc_CalcFinish()
[all …]
Dcy_sd_host.c290 #define CY_SD_HOST_IS_SD_BUS_WIDTH_VALID(width) ((CY_SD_HOST_BUS_WIDTH_1_BIT == (width)) ||… argument
291 (CY_SD_HOST_BUS_WIDTH_4_BIT == (width)))
293 #define CY_SD_HOST_IS_EMMC_BUS_WIDTH_VALID(width) ((CY_SD_HOST_BUS_WIDTH_1_BIT == (width)) ||… argument
294 … (CY_SD_HOST_BUS_WIDTH_4_BIT == (width)) || \
295 (CY_SD_HOST_BUS_WIDTH_8_BIT == (width)))
297 #define CY_SD_HOST_IS_BUS_WIDTH_VALID(width, cardType) ((CY_SD_HOST_EMMC == (cardType)) ? \ argument
298 … CY_SD_HOST_IS_EMMC_BUS_WIDTH_VALID(width) : \
299 CY_SD_HOST_IS_SD_BUS_WIDTH_VALID(width))
1817 cy_en_sd_host_bus_width_t width, in Cy_SD_Host_SetBusWidth() argument
1827 switch (width) in Cy_SD_Host_SetBusWidth()
[all …]
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_crypto_core_crc.h281 uint32_t width, in Cy_Crypto_Core_Crc_CalcInit() argument
294 tmpResult = Cy_Crypto_Core_V1_Crc_CalcInit(base, width, polynomial, dataReverse, dataXor, in Cy_Crypto_Core_Crc_CalcInit()
301 tmpResult = Cy_Crypto_Core_V2_Crc_CalcInit(base, width, polynomial, dataReverse, dataXor, in Cy_Crypto_Core_Crc_CalcInit()
329 … uint32_t width, uint32_t lfsrInitState) in Cy_Crypto_Core_Crc_CalcStart() argument
336 tmpResult = Cy_Crypto_Core_V1_Crc_CalcStart(base, width, lfsrInitState); in Cy_Crypto_Core_Crc_CalcStart()
342 tmpResult = Cy_Crypto_Core_V2_Crc_CalcStart(base, width, lfsrInitState); in Cy_Crypto_Core_Crc_CalcStart()
408 …_en_crypto_status_t Cy_Crypto_Core_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t *crc) in Cy_Crypto_Core_Crc_CalcFinish() argument
415 tmpResult = Cy_Crypto_Core_V1_Crc_CalcFinish(base, width, crc); in Cy_Crypto_Core_Crc_CalcFinish()
421 tmpResult = Cy_Crypto_Core_V2_Crc_CalcFinish(base, width, crc); in Cy_Crypto_Core_Crc_CalcFinish()
457 uint32_t width, uint32_t *crc, in Cy_Crypto_Core_Crc_Calc() argument
[all …]
Dcy_scb_uart.h964 #define CY_SCB_UART_IS_DATA_WIDTH_VALID(width) ( ((width) >= 5UL) && ((width) <= 9UL) ) argument
969 #define CY_SCB_UART_IS_RX_BREAK_WIDTH_VALID(base, width) ( ((width) >= (_FLD2VAL(SCB_RX_CTRL_DAT… argument
970 ((width) <= 16UL) )
971 #define CY_SCB_UART_IS_TX_BREAK_WIDTH_VALID(width) ( ((width) >= 4UL) && ((width) <= 16UL)… argument
973 …_SCB_UART_IS_MUTLI_PROC_VALID(mp, mode, width, parity) ( (mp) ? ((CY_SCB_UART_STANDARD == (mod… argument
Dcy_crypto_core_crc_v1.h57 uint32_t width,
65 cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcStart(CRYPTO_Type *base, uint32_t width, uint32_t …
69 cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t …
72 uint32_t width,
Dcy_crypto_core_crc_v2.h57 uint32_t width,
65 cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcStart(CRYPTO_Type *base, uint32_t width, uint32_t …
69 cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t …
72 uint32_t width,
Dcy_smif.h764 #define CY_SMIF_TXFR_WIDTH_VALID(width) ((CY_SMIF_WIDTH_SINGLE == (width)) || \ argument
765 (CY_SMIF_WIDTH_DUAL == (width)) || \
766 (CY_SMIF_WIDTH_QUAD == (width)) || \
767 (CY_SMIF_WIDTH_OCTAL == (width)) || \
768 (CY_SMIF_WIDTH_NA == (width)))
Dcy_scb_spi.h916 #define CY_SCB_SPI_IS_DATA_WIDTH_VALID(width) ( ((width) >= 4UL) && ((width) <= 32UL) ) argument
/hal_infineon-latest/mtb-hal-cat1/include_pvt/
Dcyhal_crc_impl.h41 #define _cyhal_crc_calcinit(base, width, polynomial, data_reverse, data_xor, rem_reverse, rem_xor, … argument
42 …Cy_Crypto_Core_Crc_CalcInit((base), (width), (polynomial), (data_reverse) ? 1u : 0u, (data_xor), (…
54 #define _cyhal_crc_calcinit(base, width, polynomial, data_reverse, data_xor, rem_reverse, rem_xor, …
55 …Cy_Crypto_Crc_CalcInit((base), (width), (polynomial), (data_reverse), (data_xor), (rem_reverse), (…
75 obj->crc_width = algorithm->width; in _cyhal_crc_start()
77 algorithm->width, in _cyhal_crc_start()
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_pwm.c472 …uint32_t width = (uint32_t)((uint64_t)pulse_width_us * obj->tcpwm.clock_hz / _CYHAL_PWM_US_PER_SEC… in cyhal_pwm_set_period() local
473 result = cyhal_pwm_set_period_and_compare(obj, period, width); in cyhal_pwm_set_period()
489 uint32_t width = (uint32_t)(duty_cycle * 0.01f * period); in cyhal_pwm_set_duty_cycle() local
490 result = cyhal_pwm_set_period_and_compare(obj, period, width); in cyhal_pwm_set_duty_cycle()
/hal_infineon-latest/mtb-hal-cat1/include/
Dcyhal_crc.h104 uint32_t width; //!< Bit width of the CRC member
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/
Dxmc7100_x1088_cm0plus.icf48 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
88 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7100_x2112_cm0plus.icf48 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
88 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7100_x4160_cm0plus.icf48 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
88 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7100d_x2112_cm0plus.icf48 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
88 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7100d_x4160_cm0plus.icf48 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
88 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7200_x8384_cm0plus.icf48 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
88 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7200d_x8384_cm0plus.icf48 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
88 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
/hal_infineon-latest/core-lib/
DRELEASE.md53 * Add typedefs to convey width in scenarios where there are no standard fixed-width types.
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM7/TOOLCHAIN_IAR/
Dxmc7100_x1088_cm7.icf55 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
115 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7100_x2112_cm7.icf55 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
115 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7100_x4160_cm7.icf55 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
115 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7200_x8384_cm7.icf55 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
114 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
Dxmc7100d_x2112_cm7.icf55 define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "n…
114 …init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */

12