Searched refs:txFifoTriggerLevel (Results 1 – 9 of 9) sorted by relevance
| /hal_infineon-latest/mtb-pdl-cat1/drivers/source/ |
| D | cy_i2s.c | 105 CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->txFifoTriggerLevel, channels)); in Cy_I2S_Init()
177 … REG_I2S_TX_FIFO_CTL(base) = _VAL2FLD(I2S_TX_FIFO_CTL_TRIGGER_LEVEL, config->txFifoTriggerLevel); in Cy_I2S_Init()
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| D | cy_scb_spi.c | 123 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->txFifoTriggerLevel)); in Cy_SCB_SPI_Init()
165 SCB_TX_FIFO_CTRL(base) = _VAL2FLD(SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, config->txFifoTriggerLevel); in Cy_SCB_SPI_Init()
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| D | cy_scb_uart.c | 315 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->txFifoTriggerLevel)); in Cy_SCB_UART_Init()
365 SCB_TX_FIFO_CTRL(base) = _VAL2FLD(SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, config->txFifoTriggerLevel); in Cy_SCB_UART_Init()
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| /hal_infineon-latest/mtb-pdl-cat1/drivers/include/ |
| D | cy_i2s.h | 370 …uint8_t txFifoTriggerLevel; /**< TX FIFO interrupt trigger level (0, 1, ..., 255). */ member
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| D | cy_scb_spi.h | 585 uint32_t txFifoTriggerLevel; member
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| D | cy_scb_uart.h | 534 uint32_t txFifoTriggerLevel; member
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| /hal_infineon-latest/mtb-hal-cat1/source/ |
| D | cyhal_audio_common.c | 1634 pdl_config->txFifoTriggerLevel = _cyhal_audioss_fifo_trigger_level(obj, true); in _cyhal_audioss_reconstruct_pdl_config()
1772 … pdl_config->txFifoTriggerLevel = _CYHAL_AUDIOSS_FIFO_DEPTH / 2 + 1; /* Trigger at half empty */ in _cyhal_audioss_populate_pdl_config()
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| D | cyhal_spi.c | 129 .txFifoTriggerLevel = 0,
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| D | cyhal_uart.c | 142 ….txFifoTriggerLevel = (CY_SCB_FIFO_SIZE/2 - 1), /* Level triggers when half-fifo is half e…
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