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Searched refs:rxFifoTriggerLevel (Results 1 – 14 of 14) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_pdm_pcm.c71 CY_ASSERT_L3(CY_PDM_PCM_IS_TRIG_LEVEL(config->rxFifoTriggerLevel, config->chanSelect)); in Cy_PDM_PCM_Init()
100 … PDM_PCM_RX_FIFO_CTL(base) = _VAL2FLD(PDM_RX_FIFO_CTL_TRIGGER_LEVEL, config->rxFifoTriggerLevel); in Cy_PDM_PCM_Init()
Dcy_i2s.c146 CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->rxFifoTriggerLevel, channels)); in Cy_I2S_Init()
184 … REG_I2S_RX_FIFO_CTL(base) = _VAL2FLD(I2S_RX_FIFO_CTL_TRIGGER_LEVEL, config->rxFifoTriggerLevel); in Cy_I2S_Init()
Dcy_pdm_pcm_v2.c67 CY_ASSERT_L2(CY_PDM_PCM_IS_TRIG_LEVEL(channel_config->rxFifoTriggerLevel)); in Cy_PDM_PCM_Channel_Init()
75 …ase, channel_num) = _VAL2FLD(PDM_CH_RX_FIFO_CTL_TRIGGER_LEVEL, channel_config->rxFifoTriggerLevel); in Cy_PDM_PCM_Channel_Init()
Dcy_scb_spi.c122 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->rxFifoTriggerLevel)); in Cy_SCB_SPI_Init()
152 SCB_RX_FIFO_CTRL(base) = _VAL2FLD(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, config->rxFifoTriggerLevel); in Cy_SCB_SPI_Init()
Dcy_scb_uart.c314 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->rxFifoTriggerLevel)); in Cy_SCB_UART_Init()
357 SCB_RX_FIFO_CTRL(base) = _VAL2FLD(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, config->rxFifoTriggerLevel); in Cy_SCB_UART_Init()
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_pdmpcm.c290 .rxFifoTriggerLevel = _CYHAL_PDM_PCM_HALF_FIFO - 1,
311 .rxFifoTriggerLevel = _CYHAL_PDM_PCM_HALF_FIFO - 1,
1328 obj->user_trigger_level = cfg->config->rxFifoTriggerLevel + 1; in cyhal_pdm_pcm_init_cfg()
1330 obj->user_trigger_level = cfg->chan_config->rxFifoTriggerLevel + 1; in cyhal_pdm_pcm_init_cfg()
Dcyhal_audio_common.c493 obj->user_fifo_level_rx = pdl_config->rxFifoTriggerLevel; in _cyhal_audioss_init_hw()
1598 pdl_config->rxFifoTriggerLevel = _cyhal_audioss_fifo_trigger_level(obj, false); in _cyhal_audioss_reconstruct_pdl_config()
1728 pdl_config->rxFifoTriggerLevel = _CYHAL_AUDIOSS_FIFO_DEPTH / 2 - 1; // Trigger at half full in _cyhal_audioss_populate_pdl_config()
Dcyhal_spi.c127 .rxFifoTriggerLevel = 0,
Dcyhal_uart.c139 .rxFifoTriggerLevel = 0UL, /* Level triggers when at least one element is in FIFO */
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_pdm_pcm.h366 uint8_t rxFifoTriggerLevel; /**< Fifo interrupt trigger level (in words), member
Dcy_i2s.h411 uint8_t rxFifoTriggerLevel; /**< RX FIFO interrupt trigger level member
Dcy_pdm_pcm_v2.h340 …uint8_t rxFifoTriggerLevel; /**< Fifo interrupt trigger level (in wo… member
Dcy_scb_spi.h571 uint32_t rxFifoTriggerLevel; member
Dcy_scb_uart.h520 uint32_t rxFifoTriggerLevel; member