Searched refs:rxFifoIntEnableMask (Results 1 – 6 of 6) sorted by relevance
88 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_SPI_RX_INTR_MASK)); in Cy_SCB_SPI_Init()176 SCB_INTR_RX_MASK(base) = (config->rxFifoIntEnableMask & CY_SCB_SPI_RX_INTR_MASK); in Cy_SCB_SPI_Init()
286 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_UART_RX_INTR_MASK)); in Cy_SCB_UART_Init()368 SCB_INTR_RX_MASK(base) = (config->rxFifoIntEnableMask & CY_SCB_UART_RX_INTR_MASK); in Cy_SCB_UART_Init()
577 uint32_t rxFifoIntEnableMask; member
526 uint32_t rxFifoIntEnableMask; member
128 .rxFifoIntEnableMask = 0,978 (cfg_local.rxFifoIntEnableMask != 0) || in cyhal_spi_init_cfg()
140 .rxFifoIntEnableMask = 0x0UL,
