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Searched refs:refDiv (Results 1 – 10 of 10) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_evtgen.c80 uint32_t refDiv; in Cy_EvtGen_Init() local
83 refDiv = config->frequencyRef / config->frequencyTick; in Cy_EvtGen_Init()
85 CY_ASSERT_L1(CY_EVTGEN_IS_DIVIDER_VALID_RANGE(refDiv)); in Cy_EvtGen_Init()
87 …f(((config->frequencyRef % config->frequencyTick) == 0UL) && ((refDiv <= 256UL) && (refDiv > 0UL)… in Cy_EvtGen_Init()
90 … base->REF_CLOCK_CTL = _VAL2FLD(EVTGEN_REF_CLOCK_CTL_INT_DIV, (uint8_t)(refDiv - 1UL)); in Cy_EvtGen_Init()
Dcy_sysclk.c1503 …config.refDiv = wcoSource ? 19U : (uint16_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)inputFreq * 250ULL, (u… in Cy_SysClk_FllConfigure()
1507 …t = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uint64_t)inputFr… in Cy_SysClk_FllConfigure()
1523 …B_DIV_ROUND(850ULL * CY_SYSCLK_FLL_INT_COEF * inputFreq, (uint64_t)kcco * (uint64_t)config.refDiv); in Cy_SysClk_FllConfigure()
1585 … uint64_t fref = CY_SYSLIB_DIV_ROUND(6000ULL * (uint64_t)inputFreq, (uint64_t)config.refDiv); in Cy_SysClk_FllConfigure()
1629 …CY_ASSERT_L1(config->refDiv <= (SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk >> SRSS_CLK_FLL_CONFIG2_FLL_R… in Cy_SysClk_FllManualConfigure()
1632 SRSS_CLK_FLL_CONFIG2 = _VAL2FLD(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, config->refDiv) | in Cy_SysClk_FllManualConfigure()
1671 config->refDiv = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, tempReg); in Cy_SysClk_FllGetConfiguration()
2821 rDiv = fllCfg.refDiv; in Cy_SysClk_FllGetFrequency()
Dcy_sysclk_v2.c3477 …config.refDiv = wcoSource ? 19U : (uint16_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)inputFreq * 250ULL, (u… in Cy_SysClk_FllConfigure()
3481 …t = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uint64_t)inputFr… in Cy_SysClk_FllConfigure()
3497 …B_DIV_ROUND(850ULL * CY_SYSCLK_FLL_INT_COEF * inputFreq, (uint64_t)kcco * (uint64_t)config.refDiv); in Cy_SysClk_FllConfigure()
3555 … uint64_t fref = CY_SYSLIB_DIV_ROUND(6000ULL * (uint64_t)inputFreq, (uint64_t)config.refDiv); in Cy_SysClk_FllConfigure()
3601 …CY_ASSERT_L1(config->refDiv <= (SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk >> SRSS_CLK_FLL_CONFIG2_FLL_R… in Cy_SysClk_FllManualConfigure()
3604 SRSS_CLK_FLL_CONFIG2 = _VAL2FLD(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, config->refDiv) | in Cy_SysClk_FllManualConfigure()
3647 config->refDiv = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, tempReg); in Cy_SysClk_FllGetConfiguration()
3735 rDiv = fllCfg.refDiv; in Cy_SysClk_FllGetFrequency()
Dcy_pra_cfg.c332 .refDiv = devConfig->fllRefDiv, in Cy_PRA_FllInit()
Dcy_pra.c2230 … structCpy.fllRefDiv = ((cy_stc_fll_manual_config_t *) message->praData1)->refDiv; in Cy_PRA_ProcessCmd()
/hal_infineon-latest/mtb-pdl-cat1/device-info/personalities_9.0/platform/
Dfll_solver-2.0.tcl269 proc calculate_fll_accuracy {targetCcoFreq sourceRefFreq trimStep refDiv lockTolerance} {
270 set measure [expr {(1.0 / $refDiv) * ($sourceRefFreq / $targetCcoFreq)}]
/hal_infineon-latest/mtb-pdl-cat1/device-info/personalities/platform/
Dfll_solver-2.0.tcl269 proc calculate_fll_accuracy {targetCcoFreq sourceRefFreq trimStep refDiv lockTolerance} {
270 set measure [expr {(1.0 / $refDiv) * ($sourceRefFreq / $targetCcoFreq)}]
/hal_infineon-latest/mtb-pdl-cat1/device-info/personalities_8.0/platform/
Dfll_solver-2.0.tcl269 proc calculate_fll_accuracy {targetCcoFreq sourceRefFreq trimStep refDiv lockTolerance} {
270 set measure [expr {(1.0 / $refDiv) * ($sourceRefFreq / $targetCcoFreq)}]
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h2206 uint16_t refDiv; /**< CLK_FLL_CONFIG2 register, FLL_REF_DIV bits */ member
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_clock.c1490 …SLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.refDiv * ((cfg.enableOutp… in _cyhal_clock_set_enabled_fll()
1539 …SLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.refDiv * ((cfg.enableOutp… in _cyhal_clock_set_frequency_fll()