Searched refs:memory (Results 1 – 25 of 171) sorted by relevance
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| /hal_infineon-latest/mtb-template-cat1/files/templates/cat1a/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| D | cyb06xx7_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
70 ; You can assign sections to this memory region for only one of the cores.
71 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
72 ; Therefore, repurposing this memory region will prevent such middleware from operation.
76 ; The following defines describe device specific memory regions and must not be changed.
77 ; External memory
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| D | cyb06xxa_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
70 ; You can assign sections to this memory region for only one of the cores.
71 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
72 ; Therefore, repurposing this memory region will prevent such middleware from operation.
76 ; The following defines describe device specific memory regions and must not be changed.
77 ; External memory
|
| D | cy8c6xx7_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
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| D | cy8c6xx5_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx6_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
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| D | cy8c6xx7_cm4_dual_cm0p_bless.sct | 12 ;* input files should be mapped into the output file, and to control the memory
47 ; The defines below describe the location and size of blocks of memory in the target.
48 ; Use these defines to specify the memory regions available for allocation.
50 ; The following defines control RAM and flash memory allocation for the CM4 core.
51 ; You can change the memory allocation by editing RAM and Flash defines.
53 ; Using this memory region for other purposes will lead to unexpected behavior.
75 ; You can assign sections to this memory region for only one of the cores.
76 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
77 ; Therefore, repurposing this memory region will prevent such middleware from operation.
81 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx8_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xxa_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx5_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| D | cy8c6xx6_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| D | cy8c6xx7_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| D | cy8c6xx8_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| D | cy8c6xxa_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| D | cys06xxa_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
64 ; You can assign sections to this memory region for only one of the cores.
65 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
66 ; Therefore, repurposing this memory region will prevent such middleware from operation.
70 ; The following defines describe device specific memory regions and must not be changed.
71 ; External memory
|
| D | cyb06xx7_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
64 ; You can assign sections to this memory region for only one of the cores.
65 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
66 ; Therefore, repurposing this memory region will prevent such middleware from operation.
70 ; The following defines describe device specific memory regions and must not be changed.
71 ; External memory
|
| D | cyb06xxa_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
64 ; You can assign sections to this memory region for only one of the cores.
65 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
66 ; Therefore, repurposing this memory region will prevent such middleware from operation.
70 ; The following defines describe device specific memory regions and must not be changed.
71 ; External memory
|
| /hal_infineon-latest/mtb-template-cat1/files/templates/cat1a/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| D | cy8c6xx5_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx6_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx7_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx8_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xxa_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cyb06xxa_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
67 ; You can assign sections to this memory region for only one of the cores.
68 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
69 ; Therefore, repurposing this memory region will prevent such middleware from operation.
73 ; The following defines describe device specific memory regions and must not be changed.
94 ; External memory
|
| D | cyb06xx7_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
67 ; You can assign sections to this memory region for only one of the cores.
68 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
69 ; Therefore, repurposing this memory region will prevent such middleware from operation.
73 ; The following defines describe device specific memory regions and must not be changed.
94 ; External memory
|
| /hal_infineon-latest/mtb-template-cat1/files/templates/cat1a/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/ |
| D | cyb06xx7_cm4_dual.ld | 8 * input files should be mapped into the output file, and to control the memory
60 /* The MEMORY section below describes the location and size of blocks of memory in the target.
61 * Use this section to specify the memory regions available for allocation.
65 /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
66 * You can change the memory allocation by editing the 'ram' and 'flash' regions.
67 …* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.…
74 * You can assign sections to this memory region for only one of the cores.
75 … * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
76 * Therefore, repurposing this memory region will prevent such middleware from operation.
80 /* The following regions define device specific memory regions and must not be changed. */
[all …]
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| D | cyb06xxa_cm4_dual.ld | 8 * input files should be mapped into the output file, and to control the memory
60 /* The MEMORY section below describes the location and size of blocks of memory in the target.
61 * Use this section to specify the memory regions available for allocation.
65 /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
66 * You can change the memory allocation by editing the 'ram' and 'flash' regions.
67 …* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.…
74 * You can assign sections to this memory region for only one of the cores.
75 … * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
76 * Therefore, repurposing this memory region will prevent such middleware from operation.
80 /* The following regions define device specific memory regions and must not be changed. */
[all …]
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