Searched refs:kDiv (Results 1 – 3 of 3) sorted by relevance
5108 uint32_t pDiv, kDiv, nDiv; in Cy_SysClk_DpllHpConfigure() local5122 … for (kDiv = CY_SYSCLK_DPLL_HP_MIN_KDIV; kDiv <= CY_SYSCLK_DPLL_HP_MAX_KDIV; kDiv++) in Cy_SysClk_DpllHpConfigure()5124 uint64_t tempVco = ((uint64_t)config->outputFreq) * ((uint64_t)kDiv); in Cy_SysClk_DpllHpConfigure()5129 …AC_BIT_COUNT) + (uint64_t)feedBackFracDiv)) / ((uint64_t)pDiv * (uint64_t)kDiv)) >> SRSS_DPLL_HP_F… in Cy_SysClk_DpllHpConfigure()5142 manualConfig.hpPllCfg->kDiv = (uint8_t)(kDiv - 1U); in Cy_SysClk_DpllHpConfigure()5206 …) < config->hpPllCfg->pDiv) || ((CY_SYSCLK_DPLL_HP_MAX_KDIV - 1U) < config->hpPllCfg->kDiv)) in Cy_SysClk_DpllHpManualConfigure()5219 _VAL2FLD(CLK_DPLL_HP_CONFIG_PLL_FREQ_KDIV_SEL, config->hpPllCfg->kDiv) | in Cy_SysClk_DpllHpManualConfigure()5296 …config->hpPllCfg->kDiv = (uint8_t)_FLD2VAL(CLK_DPLL_HP_CONFIG_PLL_FREQ_KDIV_SEL, tempReg); in Cy_SysClk_DpllHpGetConfiguration()5412 uint32_t kDiv; in Cy_SysClk_DpllHpGetFrequency() local5426 kDiv = (uint32_t)pllcfg.hpPllCfg->kDiv + 1U; in Cy_SysClk_DpllHpGetFrequency()[all …]
2585 uint8_t kDiv; /**< CONFIG register, KDIV bits, Post-Divider */ member
1621 *outputDiv = cfg->hpPllCfg->kDiv + 1; in _cyhal_clock_extract_pll_params()
