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Searched refs:interrupt (Results 1 – 25 of 72) sorted by relevance

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/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_tdm.h441 #define CY_I2S_TDM_INTR_TX_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_TDM_INTR_TX… argument
443 #define CY_I2S_TDM_INTR_RX_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_TDM_INTR_RX… argument
497 …IC_INLINE void Cy_AudioTDM_ClearTxInterrupt( TDM_TX_STRUCT_Type * base, uint32_t interrupt);
498 …ATIC_INLINE void Cy_AudioTDM_SetTxInterrupt( TDM_TX_STRUCT_Type * base, uint32_t interrupt);
500 …_INLINE void Cy_AudioTDM_SetTxInterruptMask( TDM_TX_STRUCT_Type * base, uint32_t interrupt);
505 …IC_INLINE void Cy_AudioTDM_ClearRxInterrupt( TDM_RX_STRUCT_Type * base, uint32_t interrupt);
506 …ATIC_INLINE void Cy_AudioTDM_SetRxInterrupt( TDM_RX_STRUCT_Type * base, uint32_t interrupt);
508 …_INLINE void Cy_AudioTDM_SetRxInterruptMask( TDM_RX_STRUCT_Type * base, uint32_t interrupt);
1084 __STATIC_INLINE void Cy_AudioTDM_ClearTxInterrupt( TDM_TX_STRUCT_Type * base, uint32_t interrupt) in Cy_AudioTDM_ClearTxInterrupt() argument
1086 CY_ASSERT_L2(CY_I2S_TDM_INTR_TX_MASK_VALID(interrupt)); in Cy_AudioTDM_ClearTxInterrupt()
[all …]
Dcy_pdm_pcm.h456 #define CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_PDM_PCM_IN… argument
484 __STATIC_INLINE void Cy_PDM_PCM_SetInterruptMask(PDM_Type * base, uint32_t interrupt);
488 __STATIC_INLINE void Cy_PDM_PCM_ClearInterrupt(PDM_Type * base, uint32_t interrupt);
489 __STATIC_INLINE void Cy_PDM_PCM_SetInterrupt(PDM_Type * base, uint32_t interrupt);
562 __STATIC_INLINE void Cy_PDM_PCM_SetInterruptMask(PDM_Type * base, uint32_t interrupt) in Cy_PDM_PCM_SetInterruptMask() argument
564 CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); in Cy_PDM_PCM_SetInterruptMask()
565 PDM_PCM_INTR_MASK(base) = interrupt; in Cy_PDM_PCM_SetInterruptMask()
629 __STATIC_INLINE void Cy_PDM_PCM_ClearInterrupt(PDM_Type * base, uint32_t interrupt) in Cy_PDM_PCM_ClearInterrupt() argument
631 CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); in Cy_PDM_PCM_ClearInterrupt()
632 PDM_PCM_INTR(base) = interrupt; in Cy_PDM_PCM_ClearInterrupt()
[all …]
Dcy_i2s.h500 #define CY_I2S_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_I2S_INTR_MASK))) argument
551 __STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt);
552 __STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt);
554 __STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt);
1028 __STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt) in Cy_I2S_ClearInterrupt() argument
1030 CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt)); in Cy_I2S_ClearInterrupt()
1031 REG_I2S_INTR(base) = interrupt; in Cy_I2S_ClearInterrupt()
1051 __STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt) in Cy_I2S_SetInterrupt() argument
1053 CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt)); in Cy_I2S_SetInterrupt()
1054 REG_I2S_INTR_SET(base) = interrupt; in Cy_I2S_SetInterrupt()
[all …]
Dcy_lpcomp.h535 __STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interrupt);
536 __STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrupt);
538 __STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt);
688 __STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt) in Cy_LPComp_SetInterruptMask() argument
690 CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt)); in Cy_LPComp_SetInterruptMask()
692 LPCOMP_INTR_MASK(base) |= interrupt; in Cy_LPComp_SetInterruptMask()
774 __STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interrupt) in Cy_LPComp_ClearInterrupt() argument
776 CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt)); in Cy_LPComp_ClearInterrupt()
777 LPCOMP_INTR(base) |= interrupt; in Cy_LPComp_ClearInterrupt()
802 __STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrupt) in Cy_LPComp_SetInterrupt() argument
[all …]
Dcy_pdm_pcm_v2.h512 #define CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_PDM_PCM_IN… argument
540 … Cy_PDM_PCM_Channel_SetInterruptMask(PDM_Type * base, uint8_t channel_num, uint32_t interrupt);
544 …id Cy_PDM_PCM_Channel_ClearInterrupt(PDM_Type * base, uint8_t channel_num, uint32_t interrupt);
545 …void Cy_PDM_PCM_Channel_SetInterrupt(PDM_Type * base, uint8_t channel_num, uint32_t interrupt);
783 … void Cy_PDM_PCM_Channel_SetInterruptMask(PDM_Type * base, uint8_t channel_num, uint32_t interrupt) in Cy_PDM_PCM_Channel_SetInterruptMask() argument
785 CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); in Cy_PDM_PCM_Channel_SetInterruptMask()
786 PDM_PCM_INTR_RX_MASK(base, channel_num) = interrupt; in Cy_PDM_PCM_Channel_SetInterruptMask()
863 …NE void Cy_PDM_PCM_Channel_ClearInterrupt(PDM_Type * base, uint8_t channel_num, uint32_t interrupt) in Cy_PDM_PCM_Channel_ClearInterrupt() argument
865 CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); in Cy_PDM_PCM_Channel_ClearInterrupt()
866 PDM_PCM_INTR_RX(base, channel_num) = interrupt; in Cy_PDM_PCM_Channel_ClearInterrupt()
[all …]
Dcy_axidmac.h461 …hannel_ClearInterrupt (AXI_DMAC_Type * base, uint32_t channel, uint32_t interrupt);
462 …hannel_SetInterrupt (AXI_DMAC_Type * base, uint32_t channel, uint32_t interrupt);
464 …hannel_SetInterruptMask (AXI_DMAC_Type * base, uint32_t channel, uint32_t interrupt);
1875 … void Cy_AXIDMAC_Channel_ClearInterrupt(AXI_DMAC_Type * base, uint32_t channel, uint32_t interrupt) in Cy_AXIDMAC_Channel_ClearInterrupt() argument
1878 CY_ASSERT_L2(CY_AXIDMAC_IS_INTR_MASK_VALID(interrupt)); in Cy_AXIDMAC_Channel_ClearInterrupt()
1880 AXIDMAC_CH_INTR(base, channel) = interrupt; in Cy_AXIDMAC_Channel_ClearInterrupt()
1905 …NE void Cy_AXIDMAC_Channel_SetInterrupt(AXI_DMAC_Type * base, uint32_t channel, uint32_t interrupt) in Cy_AXIDMAC_Channel_SetInterrupt() argument
1908 CY_ASSERT_L2(CY_AXIDMAC_IS_INTR_MASK_VALID(interrupt)); in Cy_AXIDMAC_Channel_SetInterrupt()
1910 AXIDMAC_CH_INTR_SET(base, channel) = interrupt; in Cy_AXIDMAC_Channel_SetInterrupt()
1960 …oid Cy_AXIDMAC_Channel_SetInterruptMask(AXI_DMAC_Type * base, uint32_t channel, uint32_t interrupt) in Cy_AXIDMAC_Channel_SetInterruptMask() argument
[all …]
Dcy_dmac.h497 …MAC_Channel_ClearInterrupt (DMAC_Type * base, uint32_t channel, uint32_t interrupt);
498 …MAC_Channel_SetInterrupt (DMAC_Type * base, uint32_t channel, uint32_t interrupt);
500 …MAC_Channel_SetInterruptMask (DMAC_Type * base, uint32_t channel, uint32_t interrupt);
1720 …_INLINE void Cy_DMAC_Channel_ClearInterrupt(DMAC_Type * base, uint32_t channel, uint32_t interrupt) in Cy_DMAC_Channel_ClearInterrupt() argument
1723 CY_ASSERT_L2(CY_DMAC_IS_INTR_MASK_VALID(interrupt)); in Cy_DMAC_Channel_ClearInterrupt()
1725 DMAC_CH_INTR(base, channel) = interrupt; in Cy_DMAC_Channel_ClearInterrupt()
1750 …IC_INLINE void Cy_DMAC_Channel_SetInterrupt(DMAC_Type * base, uint32_t channel, uint32_t interrupt) in Cy_DMAC_Channel_SetInterrupt() argument
1753 CY_ASSERT_L2(CY_DMAC_IS_INTR_MASK_VALID(interrupt)); in Cy_DMAC_Channel_SetInterrupt()
1755 DMAC_CH_INTR_SET(base, channel) = interrupt; in Cy_DMAC_Channel_SetInterrupt()
1805 …NLINE void Cy_DMAC_Channel_SetInterruptMask(DMAC_Type * base, uint32_t channel, uint32_t interrupt) in Cy_DMAC_Channel_SetInterruptMask() argument
[all …]
Dcy_smif.h1394 __STATIC_INLINE void Cy_SMIF_SetInterruptMask(SMIF_Type *base, uint32_t interrupt);
1398 __STATIC_INLINE void Cy_SMIF_SetInterrupt(SMIF_Type *base, uint32_t interrupt);
1399 __STATIC_INLINE void Cy_SMIF_ClearInterrupt(SMIF_Type *base, uint32_t interrupt);
1499 __STATIC_INLINE void Cy_SMIF_SetInterruptMask(SMIF_Type *base, uint32_t interrupt) in Cy_SMIF_SetInterruptMask() argument
1501 SMIF_INTR_MASK(base) = interrupt; in Cy_SMIF_SetInterruptMask()
1583 __STATIC_INLINE void Cy_SMIF_SetInterrupt(SMIF_Type *base, uint32_t interrupt) in Cy_SMIF_SetInterrupt() argument
1585 SMIF_INTR_SET(base) = interrupt; in Cy_SMIF_SetInterrupt()
1605 __STATIC_INLINE void Cy_SMIF_ClearInterrupt(SMIF_Type *base, uint32_t interrupt) in Cy_SMIF_ClearInterrupt() argument
1607 SMIF_INTR(base) = interrupt; in Cy_SMIF_ClearInterrupt()
1610 interrupt = SMIF_INTR(base); in Cy_SMIF_ClearInterrupt()
Dcy_sd_host.h1627 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptEnable(SDHC_Type *base, uint32_t interrupt);
1633 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptEnable(SDHC_Type *base, uint32_t interrupt);
2019 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptEnable(SDHC_Type *base, uint32_t interrupt) in Cy_SD_Host_SetNormalInterruptEnable() argument
2021 SDHC_CORE_NORMAL_INT_STAT_EN_R(base) = (uint16_t)interrupt; in Cy_SD_Host_SetNormalInterruptEnable()
2146 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptEnable(SDHC_Type *base, uint32_t interrupt) in Cy_SD_Host_SetErrorInterruptEnable() argument
2148 SDHC_CORE_ERROR_INT_STAT_EN_R(base) = (uint16_t)interrupt; in Cy_SD_Host_SetErrorInterruptEnable()
Dcy_dma.h561 …y_DMA_Channel_SetInterruptMask (DW_Type * base, uint32_t channel, uint32_t interrupt);
1950 …C_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t channel, uint32_t interrupt) in Cy_DMA_Channel_SetInterruptMask() argument
1953 CY_ASSERT_L2(CY_DMA_IS_INTR_MASK_VALID(interrupt)); in Cy_DMA_Channel_SetInterruptMask()
1954 DW_CH_INTR_MASK(base, channel) = interrupt; in Cy_DMA_Channel_SetInterruptMask()
Dcy_canfd.h1150 __STATIC_INLINE void Cy_CANFD_SetInterruptMask(CANFD_Type *base, uint32_t chan, uint32_t interrupt);
1697 __STATIC_INLINE void Cy_CANFD_SetInterruptMask(CANFD_Type *base, uint32_t chan, uint32_t interrupt) in Cy_CANFD_SetInterruptMask() argument
1699 CANFD_IE(base, chan) = interrupt; in Cy_CANFD_SetInterruptMask()
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/
Dcy_syslib_ext.s66 ; enable bit with interrupts still enabled. The test and set of the interrupt
68 ; be the policy that all interrupt routines restore the interrupt enable bits as
80 MRS r0, PRIMASK ; Save and return an interrupt state.
97 ; The saved interrupt status returned by the Cy_SysLib_EnterCriticalSection
104 MSR PRIMASK, r0 ; Restore the interrupt state.
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1a/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/
Dstartup_psoc6_02_cm4.s78 … DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
79 … DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
80 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
110 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
214 DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
215 DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
216 DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
217 DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
218 DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
219 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
[all …]
Dstartup_psoc6_01_cm4.s78 … DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
79 … DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
80 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
83 DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt
108 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
197 DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
198 DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt
199 DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt
200 DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
201 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
Dstartup_psoc6_04_cm4.s78 … DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
79 … DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
80 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
98 DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt
99 DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt
100 DCD pass_interrupt_ctbs_IRQHandler ; individual interrupt per CTB
110 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
219 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
227 DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0
Dstartup_psoc6_03_cm4.s78 … DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
79 … DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
80 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
110 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
214 DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
219 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
223 DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc
224 …DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything e…
227 DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0
/hal_infineon-latest/XMCLib/drivers/inc/
Dxmc_ccu4.h169 #define XMC_CCU4_SLICE_CHECK_INTERRUPT(interrupt) \ argument
170 ((interrupt == XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH) || \
171 (interrupt == XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH) || \
172 (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP) || \
173 (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN)|| \
174 (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT0) || \
175 (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT1) || \
176 (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT2) || \
177 (interrupt == XMC_CCU4_SLICE_IRQ_ID_TRAP))
Dxmc_ccu8.h189 #define XMC_CCU8_SLICE_CHECK_INTERRUPT(interrupt) \ argument
190 ((interrupt == XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH) || \
191 (interrupt == XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH) || \
192 (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1) || \
193 (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1)|| \
194 (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2) || \
195 (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2)|| \
196 (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT0) || \
197 (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT1) || \
198 (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT2) || \
[all …]
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1a/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/
Dstartup_psoc6_02_cm4.s103 DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
104 DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
105 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
135 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
239 DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
240 DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
241 DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
242 DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
243 DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
244 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
[all …]
Dstartup_psoc6_01_cm4.s103 DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
104 DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
105 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
108 DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt
133 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
222 DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
223 DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt
224 DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt
225 DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
226 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
[all …]
Dstartup_psoc6_03_cm4.s103 DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
104 DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
105 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
135 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
239 DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
244 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
248 DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc
249 …DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything e…
252 DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0
318 ;; Default interrupt handlers.
Dstartup_psoc6_04_cm4.s103 DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
104 DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
105 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
123 DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt
124 DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt
125 DCD pass_interrupt_ctbs_IRQHandler ; individual interrupt per CTB
135 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
244 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
252 DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0
319 ;; Default interrupt handlers.
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/TOOLCHAIN_IAR/
Dcy_syslib_ext.s76 MRS r0, PRIMASK ; Save and return an interrupt state.
96 MSR PRIMASK, r0 ; Restore the interrupt state.
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/
Dstartup_cm0plus.s187 ; Macro to define default exception/interrupt handlers.
199 ; Default exception/interrupt handler
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/
Dstartup_cm0plus.s234 ;* Default and weak implementation of interrupt handlers
303 … ; Traveo II CPU User Interrupts 0-7 handlers are defined in the project interrupt mapping file

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