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Searched refs:fllMult (Results 1 – 7 of 7) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c327 .fllMult = devConfig->fllMult, in Cy_PRA_FllInit()
1268 …if ((devConfig->fllMult < CY_PRA_FLL_MIN_MULTIPLIER) || (devConfig->fllMult > CY_PRA_FLL_MAX_MULTI… in Cy_PRA_ValidateFLL()
2447 …outFreq = ((srcFreq * devConfig->fllMult) / devConfig->fllRefDiv) / (devConfig->enableOutputDiv ? … in Cy_PRA_CalculateFLLOutFreq()
Dcy_sysclk.c1507 …config.fllMult = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uin… in Cy_SysClk_FllConfigure()
1513 … config.lockTolerance = (uint16_t)CY_SYSLIB_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL); in Cy_SysClk_FllConfigure()
1622 …CY_ASSERT_L1(config->fllMult <= (SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk >> SRSS_CLK_FLL_CONFIG_FLL_MULT_… in Cy_SysClk_FllManualConfigure()
1624 SRSS_CLK_FLL_CONFIG = _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_MULT, config->fllMult) | in Cy_SysClk_FllManualConfigure()
1667 config->fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, tempReg); in Cy_SysClk_FllGetConfiguration()
2820 fDiv = fllCfg.fllMult; in Cy_SysClk_FllGetFrequency()
Dcy_sysclk_v2.c3481 …config.fllMult = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uin… in Cy_SysClk_FllConfigure()
3487 … config.lockTolerance = (uint16_t)CY_SYSLIB_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL); in Cy_SysClk_FllConfigure()
3594 …CY_ASSERT_L1(config->fllMult <= (SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk >> SRSS_CLK_FLL_CONFIG_FLL_MULT_… in Cy_SysClk_FllManualConfigure()
3596 SRSS_CLK_FLL_CONFIG = _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_MULT, config->fllMult) | in Cy_SysClk_FllManualConfigure()
3643 config->fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, tempReg); in Cy_SysClk_FllGetConfiguration()
3734 fDiv = fllCfg.fllMult; in Cy_SysClk_FllGetFrequency()
Dcy_pra.c2229 … structCpy.fllMult = ((cy_stc_fll_manual_config_t *) message->praData1)->fllMult; in Cy_PRA_ProcessCmd()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_pra_cfg.h215 …uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */ member
Dcy_sysclk.h2205 uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */ member
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_clock.c1490 …uint32_t fll_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.… in _cyhal_clock_set_enabled_fll()
1539 …uint32_t old_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.… in _cyhal_clock_set_frequency_fll()