1 /***************************************************************************//** 2 * \file tviic2d6m_config.h 3 * 4 * \brief 5 * TVIIC2D6M device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _TVIIC2D6M_CONFIG_H_ 28 #define _TVIIC2D6M_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_CPUSS_CLOCK_TRACE_IN = 0x0000u, /* cpuss.clock_trace_in */ 34 PCLK_SMARTIO7_CLOCK = 0x0001u, /* smartio[7].clock */ 35 PCLK_TCPWM0_CLOCKS0 = 0x0002u, /* tcpwm[0].clocks[0] */ 36 PCLK_TCPWM0_CLOCKS1 = 0x0003u, /* tcpwm[0].clocks[1] */ 37 PCLK_TCPWM0_CLOCKS2 = 0x0004u, /* tcpwm[0].clocks[2] */ 38 PCLK_TCPWM0_CLOCKS3 = 0x0005u, /* tcpwm[0].clocks[3] */ 39 PCLK_TCPWM0_CLOCKS4 = 0x0006u, /* tcpwm[0].clocks[4] */ 40 PCLK_TCPWM0_CLOCKS5 = 0x0007u, /* tcpwm[0].clocks[5] */ 41 PCLK_TCPWM0_CLOCKS6 = 0x0008u, /* tcpwm[0].clocks[6] */ 42 PCLK_TCPWM0_CLOCKS7 = 0x0009u, /* tcpwm[0].clocks[7] */ 43 PCLK_TCPWM0_CLOCKS8 = 0x000Au, /* tcpwm[0].clocks[8] */ 44 PCLK_TCPWM0_CLOCKS9 = 0x000Bu, /* tcpwm[0].clocks[9] */ 45 PCLK_TCPWM0_CLOCKS10 = 0x000Cu, /* tcpwm[0].clocks[10] */ 46 PCLK_TCPWM0_CLOCKS11 = 0x000Du, /* tcpwm[0].clocks[11] */ 47 PCLK_TCPWM0_CLOCKS12 = 0x000Eu, /* tcpwm[0].clocks[12] */ 48 PCLK_TCPWM0_CLOCKS13 = 0x000Fu, /* tcpwm[0].clocks[13] */ 49 PCLK_TCPWM0_CLOCKS14 = 0x0010u, /* tcpwm[0].clocks[14] */ 50 PCLK_TCPWM0_CLOCKS15 = 0x0011u, /* tcpwm[0].clocks[15] */ 51 PCLK_TCPWM0_CLOCKS16 = 0x0012u, /* tcpwm[0].clocks[16] */ 52 PCLK_TCPWM0_CLOCKS17 = 0x0013u, /* tcpwm[0].clocks[17] */ 53 PCLK_TCPWM0_CLOCKS18 = 0x0014u, /* tcpwm[0].clocks[18] */ 54 PCLK_TCPWM0_CLOCKS19 = 0x0015u, /* tcpwm[0].clocks[19] */ 55 PCLK_TCPWM0_CLOCKS20 = 0x0016u, /* tcpwm[0].clocks[20] */ 56 PCLK_TCPWM0_CLOCKS21 = 0x0017u, /* tcpwm[0].clocks[21] */ 57 PCLK_TCPWM0_CLOCKS22 = 0x0018u, /* tcpwm[0].clocks[22] */ 58 PCLK_TCPWM0_CLOCKS23 = 0x0019u, /* tcpwm[0].clocks[23] */ 59 PCLK_TCPWM0_CLOCKS24 = 0x001Au, /* tcpwm[0].clocks[24] */ 60 PCLK_TCPWM0_CLOCKS25 = 0x001Bu, /* tcpwm[0].clocks[25] */ 61 PCLK_TCPWM0_CLOCKS26 = 0x001Cu, /* tcpwm[0].clocks[26] */ 62 PCLK_TCPWM0_CLOCKS27 = 0x001Du, /* tcpwm[0].clocks[27] */ 63 PCLK_TCPWM0_CLOCKS28 = 0x001Eu, /* tcpwm[0].clocks[28] */ 64 PCLK_TCPWM0_CLOCKS29 = 0x001Fu, /* tcpwm[0].clocks[29] */ 65 PCLK_TCPWM0_CLOCKS30 = 0x0020u, /* tcpwm[0].clocks[30] */ 66 PCLK_TCPWM0_CLOCKS31 = 0x0021u, /* tcpwm[0].clocks[31] */ 67 PCLK_TCPWM0_CLOCKS32 = 0x0022u, /* tcpwm[0].clocks[32] */ 68 PCLK_TCPWM0_CLOCKS33 = 0x0023u, /* tcpwm[0].clocks[33] */ 69 PCLK_TCPWM0_CLOCKS34 = 0x0024u, /* tcpwm[0].clocks[34] */ 70 PCLK_TCPWM0_CLOCKS35 = 0x0025u, /* tcpwm[0].clocks[35] */ 71 PCLK_TCPWM0_CLOCKS36 = 0x0026u, /* tcpwm[0].clocks[36] */ 72 PCLK_TCPWM0_CLOCKS37 = 0x0027u, /* tcpwm[0].clocks[37] */ 73 PCLK_TCPWM0_CLOCKS256 = 0x0028u, /* tcpwm[0].clocks[256] */ 74 PCLK_TCPWM0_CLOCKS257 = 0x0029u, /* tcpwm[0].clocks[257] */ 75 PCLK_TCPWM0_CLOCKS258 = 0x002Au, /* tcpwm[0].clocks[258] */ 76 PCLK_TCPWM0_CLOCKS259 = 0x002Bu, /* tcpwm[0].clocks[259] */ 77 PCLK_TCPWM0_CLOCKS260 = 0x002Cu, /* tcpwm[0].clocks[260] */ 78 PCLK_TCPWM0_CLOCKS261 = 0x002Du, /* tcpwm[0].clocks[261] */ 79 PCLK_TCPWM0_CLOCKS262 = 0x002Eu, /* tcpwm[0].clocks[262] */ 80 PCLK_TCPWM0_CLOCKS263 = 0x002Fu, /* tcpwm[0].clocks[263] */ 81 PCLK_TCPWM0_CLOCKS264 = 0x0030u, /* tcpwm[0].clocks[264] */ 82 PCLK_TCPWM0_CLOCKS265 = 0x0031u, /* tcpwm[0].clocks[265] */ 83 PCLK_TCPWM0_CLOCKS266 = 0x0032u, /* tcpwm[0].clocks[266] */ 84 PCLK_TCPWM0_CLOCKS267 = 0x0033u, /* tcpwm[0].clocks[267] */ 85 PCLK_TCPWM0_CLOCKS512 = 0x0034u, /* tcpwm[0].clocks[512] */ 86 PCLK_TCPWM0_CLOCKS513 = 0x0035u, /* tcpwm[0].clocks[513] */ 87 PCLK_TCPWM0_CLOCKS514 = 0x0036u, /* tcpwm[0].clocks[514] */ 88 PCLK_TCPWM0_CLOCKS515 = 0x0037u, /* tcpwm[0].clocks[515] */ 89 PCLK_TCPWM0_CLOCKS516 = 0x0038u, /* tcpwm[0].clocks[516] */ 90 PCLK_TCPWM0_CLOCKS517 = 0x0039u, /* tcpwm[0].clocks[517] */ 91 PCLK_TCPWM0_CLOCKS518 = 0x003Au, /* tcpwm[0].clocks[518] */ 92 PCLK_TCPWM0_CLOCKS519 = 0x003Bu, /* tcpwm[0].clocks[519] */ 93 PCLK_TCPWM0_CLOCKS520 = 0x003Cu, /* tcpwm[0].clocks[520] */ 94 PCLK_TCPWM0_CLOCKS521 = 0x003Du, /* tcpwm[0].clocks[521] */ 95 PCLK_TCPWM0_CLOCKS522 = 0x003Eu, /* tcpwm[0].clocks[522] */ 96 PCLK_TCPWM0_CLOCKS523 = 0x003Fu, /* tcpwm[0].clocks[523] */ 97 PCLK_TCPWM0_CLOCKS524 = 0x0040u, /* tcpwm[0].clocks[524] */ 98 PCLK_TCPWM0_CLOCKS525 = 0x0041u, /* tcpwm[0].clocks[525] */ 99 PCLK_TCPWM0_CLOCKS526 = 0x0042u, /* tcpwm[0].clocks[526] */ 100 PCLK_TCPWM0_CLOCKS527 = 0x0043u, /* tcpwm[0].clocks[527] */ 101 PCLK_TCPWM0_CLOCKS528 = 0x0044u, /* tcpwm[0].clocks[528] */ 102 PCLK_TCPWM0_CLOCKS529 = 0x0045u, /* tcpwm[0].clocks[529] */ 103 PCLK_TCPWM0_CLOCKS530 = 0x0046u, /* tcpwm[0].clocks[530] */ 104 PCLK_TCPWM0_CLOCKS531 = 0x0047u, /* tcpwm[0].clocks[531] */ 105 PCLK_TCPWM0_CLOCKS532 = 0x0048u, /* tcpwm[0].clocks[532] */ 106 PCLK_TCPWM0_CLOCKS533 = 0x0049u, /* tcpwm[0].clocks[533] */ 107 PCLK_TCPWM0_CLOCKS534 = 0x004Au, /* tcpwm[0].clocks[534] */ 108 PCLK_TCPWM0_CLOCKS535 = 0x004Bu, /* tcpwm[0].clocks[535] */ 109 PCLK_TCPWM0_CLOCKS536 = 0x004Cu, /* tcpwm[0].clocks[536] */ 110 PCLK_TCPWM0_CLOCKS537 = 0x004Du, /* tcpwm[0].clocks[537] */ 111 PCLK_TCPWM0_CLOCKS538 = 0x004Eu, /* tcpwm[0].clocks[538] */ 112 PCLK_TCPWM0_CLOCKS539 = 0x004Fu, /* tcpwm[0].clocks[539] */ 113 PCLK_TCPWM0_CLOCKS540 = 0x0050u, /* tcpwm[0].clocks[540] */ 114 PCLK_TCPWM0_CLOCKS541 = 0x0051u, /* tcpwm[0].clocks[541] */ 115 PCLK_TCPWM0_CLOCKS542 = 0x0052u, /* tcpwm[0].clocks[542] */ 116 PCLK_TCPWM0_CLOCKS543 = 0x0053u, /* tcpwm[0].clocks[543] */ 117 PCLK_CANFD0_CLOCK_CAN0 = 0x0100u, /* canfd[0].clock_can[0] */ 118 PCLK_CANFD0_CLOCK_CAN1 = 0x0101u, /* canfd[0].clock_can[1] */ 119 PCLK_CANFD1_CLOCK_CAN0 = 0x0102u, /* canfd[1].clock_can[0] */ 120 PCLK_CANFD1_CLOCK_CAN1 = 0x0103u, /* canfd[1].clock_can[1] */ 121 PCLK_LIN0_CLOCK_CH_EN0 = 0x0104u, /* lin[0].clock_ch_en[0] */ 122 PCLK_LIN0_CLOCK_CH_EN1 = 0x0105u, /* lin[0].clock_ch_en[1] */ 123 PCLK_CXPI0_CLOCK_CH_EN0 = 0x0106u, /* cxpi[0].clock_ch_en[0] */ 124 PCLK_CXPI0_CLOCK_CH_EN1 = 0x0107u, /* cxpi[0].clock_ch_en[1] */ 125 PCLK_SCB0_CLOCK = 0x0108u, /* scb[0].clock */ 126 PCLK_SCB1_CLOCK = 0x0109u, /* scb[1].clock */ 127 PCLK_SCB2_CLOCK = 0x010Au, /* scb[2].clock */ 128 PCLK_SCB3_CLOCK = 0x010Bu, /* scb[3].clock */ 129 PCLK_SCB4_CLOCK = 0x010Cu, /* scb[4].clock */ 130 PCLK_SCB5_CLOCK = 0x010Du, /* scb[5].clock */ 131 PCLK_SCB6_CLOCK = 0x010Eu, /* scb[6].clock */ 132 PCLK_SCB7_CLOCK = 0x010Fu, /* scb[7].clock */ 133 PCLK_SCB8_CLOCK = 0x0110u, /* scb[8].clock */ 134 PCLK_SCB9_CLOCK = 0x0111u, /* scb[9].clock */ 135 PCLK_SCB10_CLOCK = 0x0112u, /* scb[10].clock */ 136 PCLK_SCB11_CLOCK = 0x0113u, /* scb[11].clock */ 137 PCLK_PASS0_CLOCK_SAR0 = 0x0114u /* pass[0].clock_sar[0] */ 138 } en_clk_dst_t; 139 140 /* Trigger Group */ 141 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 142 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 143 */ 144 /* Trigger Group Inputs */ 145 /* Trigger Input Group 0 - P-DMA0[0:15] Request Assignments */ 146 typedef enum 147 { 148 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 149 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 150 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 151 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 152 TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ 153 TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ 154 TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ 155 TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ 156 TRIG_IN_MUX_0_PDMA0_TR_OUT8 = 0x00000009u, /* cpuss.dw0_tr_out[8] */ 157 TRIG_IN_MUX_0_PDMA0_TR_OUT9 = 0x0000000Au, /* cpuss.dw0_tr_out[9] */ 158 TRIG_IN_MUX_0_PDMA0_TR_OUT10 = 0x0000000Bu, /* cpuss.dw0_tr_out[10] */ 159 TRIG_IN_MUX_0_PDMA0_TR_OUT11 = 0x0000000Cu, /* cpuss.dw0_tr_out[11] */ 160 TRIG_IN_MUX_0_PDMA0_TR_OUT12 = 0x0000000Du, /* cpuss.dw0_tr_out[12] */ 161 TRIG_IN_MUX_0_PDMA0_TR_OUT13 = 0x0000000Eu, /* cpuss.dw0_tr_out[13] */ 162 TRIG_IN_MUX_0_PDMA0_TR_OUT14 = 0x0000000Fu, /* cpuss.dw0_tr_out[14] */ 163 TRIG_IN_MUX_0_PDMA0_TR_OUT15 = 0x00000010u, /* cpuss.dw0_tr_out[15] */ 164 TRIG_IN_MUX_0_PDMA0_TR_OUT16 = 0x00000011u, /* cpuss.dw0_tr_out[16] */ 165 TRIG_IN_MUX_0_PDMA0_TR_OUT17 = 0x00000012u, /* cpuss.dw0_tr_out[17] */ 166 TRIG_IN_MUX_0_PDMA0_TR_OUT18 = 0x00000013u, /* cpuss.dw0_tr_out[18] */ 167 TRIG_IN_MUX_0_PDMA0_TR_OUT19 = 0x00000014u, /* cpuss.dw0_tr_out[19] */ 168 TRIG_IN_MUX_0_PDMA0_TR_OUT20 = 0x00000015u, /* cpuss.dw0_tr_out[20] */ 169 TRIG_IN_MUX_0_PDMA0_TR_OUT21 = 0x00000016u, /* cpuss.dw0_tr_out[21] */ 170 TRIG_IN_MUX_0_PDMA0_TR_OUT22 = 0x00000017u, /* cpuss.dw0_tr_out[22] */ 171 TRIG_IN_MUX_0_PDMA0_TR_OUT23 = 0x00000018u, /* cpuss.dw0_tr_out[23] */ 172 TRIG_IN_MUX_0_PDMA0_TR_OUT24 = 0x00000019u, /* cpuss.dw0_tr_out[24] */ 173 TRIG_IN_MUX_0_PDMA0_TR_OUT25 = 0x0000001Au, /* cpuss.dw0_tr_out[25] */ 174 TRIG_IN_MUX_0_PDMA0_TR_OUT26 = 0x0000001Bu, /* cpuss.dw0_tr_out[26] */ 175 TRIG_IN_MUX_0_PDMA0_TR_OUT27 = 0x0000001Cu, /* cpuss.dw0_tr_out[27] */ 176 TRIG_IN_MUX_0_PDMA0_TR_OUT28 = 0x0000001Du, /* cpuss.dw0_tr_out[28] */ 177 TRIG_IN_MUX_0_PDMA0_TR_OUT29 = 0x0000001Eu, /* cpuss.dw0_tr_out[29] */ 178 TRIG_IN_MUX_0_PDMA0_TR_OUT30 = 0x0000001Fu, /* cpuss.dw0_tr_out[30] */ 179 TRIG_IN_MUX_0_PDMA0_TR_OUT31 = 0x00000020u, /* cpuss.dw0_tr_out[31] */ 180 TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000021u, /* cpuss.dw1_tr_out[0] */ 181 TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x00000022u, /* cpuss.dw1_tr_out[1] */ 182 TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x00000023u, /* cpuss.dw1_tr_out[2] */ 183 TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x00000024u, /* cpuss.dw1_tr_out[3] */ 184 TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x00000025u, /* cpuss.dw1_tr_out[4] */ 185 TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x00000026u, /* cpuss.dw1_tr_out[5] */ 186 TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x00000027u, /* cpuss.dw1_tr_out[6] */ 187 TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000028u, /* cpuss.dw1_tr_out[7] */ 188 TRIG_IN_MUX_0_PDMA1_TR_OUT8 = 0x00000029u, /* cpuss.dw1_tr_out[8] */ 189 TRIG_IN_MUX_0_PDMA1_TR_OUT9 = 0x0000002Au, /* cpuss.dw1_tr_out[9] */ 190 TRIG_IN_MUX_0_PDMA1_TR_OUT10 = 0x0000002Bu, /* cpuss.dw1_tr_out[10] */ 191 TRIG_IN_MUX_0_PDMA1_TR_OUT11 = 0x0000002Cu, /* cpuss.dw1_tr_out[11] */ 192 TRIG_IN_MUX_0_PDMA1_TR_OUT12 = 0x0000002Du, /* cpuss.dw1_tr_out[12] */ 193 TRIG_IN_MUX_0_PDMA1_TR_OUT13 = 0x0000002Eu, /* cpuss.dw1_tr_out[13] */ 194 TRIG_IN_MUX_0_PDMA1_TR_OUT14 = 0x0000002Fu, /* cpuss.dw1_tr_out[14] */ 195 TRIG_IN_MUX_0_PDMA1_TR_OUT15 = 0x00000030u, /* cpuss.dw1_tr_out[15] */ 196 TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000031u, /* cpuss.dmac_tr_out[0] */ 197 TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000032u, /* cpuss.dmac_tr_out[1] */ 198 TRIG_IN_MUX_0_MDMA_TR_OUT2 = 0x00000033u, /* cpuss.dmac_tr_out[2] */ 199 TRIG_IN_MUX_0_MDMA_TR_OUT3 = 0x00000034u, /* cpuss.dmac_tr_out[3] */ 200 TRIG_IN_MUX_0_MDMA_TR_OUT4 = 0x00000035u, /* cpuss.dmac_tr_out[4] */ 201 TRIG_IN_MUX_0_MDMA_TR_OUT5 = 0x00000036u, /* cpuss.dmac_tr_out[5] */ 202 TRIG_IN_MUX_0_MDMA_TR_OUT6 = 0x00000037u, /* cpuss.dmac_tr_out[6] */ 203 TRIG_IN_MUX_0_MDMA_TR_OUT7 = 0x00000038u, /* cpuss.dmac_tr_out[7] */ 204 TRIG_IN_MUX_0_CAN0_TT_TR_OUT0 = 0x00000039u, /* canfd[0].tr_tmp_rtp_out[0] */ 205 TRIG_IN_MUX_0_CAN0_TT_TR_OUT1 = 0x0000003Au, /* canfd[0].tr_tmp_rtp_out[1] */ 206 TRIG_IN_MUX_0_CAN1_TT_TR_OUT0 = 0x0000003Bu, /* canfd[1].tr_tmp_rtp_out[0] */ 207 TRIG_IN_MUX_0_CAN1_TT_TR_OUT1 = 0x0000003Cu, /* canfd[1].tr_tmp_rtp_out[1] */ 208 TRIG_IN_MUX_0_HSIOM_IO_INPUT0 = 0x0000003Du, /* peri.tr_io_input[0] */ 209 TRIG_IN_MUX_0_HSIOM_IO_INPUT1 = 0x0000003Eu, /* peri.tr_io_input[1] */ 210 TRIG_IN_MUX_0_HSIOM_IO_INPUT2 = 0x0000003Fu, /* peri.tr_io_input[2] */ 211 TRIG_IN_MUX_0_HSIOM_IO_INPUT3 = 0x00000040u, /* peri.tr_io_input[3] */ 212 TRIG_IN_MUX_0_HSIOM_IO_INPUT4 = 0x00000041u, /* peri.tr_io_input[4] */ 213 TRIG_IN_MUX_0_HSIOM_IO_INPUT5 = 0x00000042u, /* peri.tr_io_input[5] */ 214 TRIG_IN_MUX_0_HSIOM_IO_INPUT6 = 0x00000043u, /* peri.tr_io_input[6] */ 215 TRIG_IN_MUX_0_HSIOM_IO_INPUT7 = 0x00000044u, /* peri.tr_io_input[7] */ 216 TRIG_IN_MUX_0_HSIOM_IO_INPUT8 = 0x00000045u, /* peri.tr_io_input[8] */ 217 TRIG_IN_MUX_0_HSIOM_IO_INPUT9 = 0x00000046u, /* peri.tr_io_input[9] */ 218 TRIG_IN_MUX_0_HSIOM_IO_INPUT10 = 0x00000047u, /* peri.tr_io_input[10] */ 219 TRIG_IN_MUX_0_HSIOM_IO_INPUT11 = 0x00000048u, /* peri.tr_io_input[11] */ 220 TRIG_IN_MUX_0_HSIOM_IO_INPUT12 = 0x00000049u, /* peri.tr_io_input[12] */ 221 TRIG_IN_MUX_0_HSIOM_IO_INPUT13 = 0x0000004Au, /* peri.tr_io_input[13] */ 222 TRIG_IN_MUX_0_HSIOM_IO_INPUT14 = 0x0000004Bu, /* peri.tr_io_input[14] */ 223 TRIG_IN_MUX_0_HSIOM_IO_INPUT15 = 0x0000004Cu, /* peri.tr_io_input[15] */ 224 TRIG_IN_MUX_0_HSIOM_IO_INPUT16 = 0x0000004Du, /* peri.tr_io_input[16] */ 225 TRIG_IN_MUX_0_HSIOM_IO_INPUT17 = 0x0000004Eu, /* peri.tr_io_input[17] */ 226 TRIG_IN_MUX_0_HSIOM_IO_INPUT18 = 0x0000004Fu, /* peri.tr_io_input[18] */ 227 TRIG_IN_MUX_0_HSIOM_IO_INPUT19 = 0x00000050u, /* peri.tr_io_input[19] */ 228 TRIG_IN_MUX_0_HSIOM_IO_INPUT20 = 0x00000051u, /* peri.tr_io_input[20] */ 229 TRIG_IN_MUX_0_HSIOM_IO_INPUT21 = 0x00000052u, /* peri.tr_io_input[21] */ 230 TRIG_IN_MUX_0_HSIOM_IO_INPUT22 = 0x00000053u, /* peri.tr_io_input[22] */ 231 TRIG_IN_MUX_0_HSIOM_IO_INPUT23 = 0x00000054u, /* peri.tr_io_input[23] */ 232 TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x00000055u, /* cpuss.tr_fault[0] */ 233 TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x00000056u, /* cpuss.tr_fault[1] */ 234 TRIG_IN_MUX_0_FAULT_TR_OUT2 = 0x00000057u, /* cpuss.tr_fault[2] */ 235 TRIG_IN_MUX_0_FAULT_TR_OUT3 = 0x00000058u /* cpuss.tr_fault[3] */ 236 } en_trig_input_pdma0_0_15_t; 237 238 /* Trigger Input Group 1 - P-DMA0[16:31] Request Assignments */ 239 typedef enum 240 { 241 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT00 = 0x00000101u, /* tcpwm[0].tr_out0[0] */ 242 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT01 = 0x00000102u, /* tcpwm[0].tr_out0[1] */ 243 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT02 = 0x00000103u, /* tcpwm[0].tr_out0[2] */ 244 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT03 = 0x00000104u, /* tcpwm[0].tr_out0[3] */ 245 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT04 = 0x00000105u, /* tcpwm[0].tr_out0[4] */ 246 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT05 = 0x00000106u, /* tcpwm[0].tr_out0[5] */ 247 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT06 = 0x00000107u, /* tcpwm[0].tr_out0[6] */ 248 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT07 = 0x00000108u, /* tcpwm[0].tr_out0[7] */ 249 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT08 = 0x00000109u, /* tcpwm[0].tr_out0[8] */ 250 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT09 = 0x0000010Au, /* tcpwm[0].tr_out0[9] */ 251 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT010 = 0x0000010Bu, /* tcpwm[0].tr_out0[10] */ 252 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT011 = 0x0000010Cu, /* tcpwm[0].tr_out0[11] */ 253 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT012 = 0x0000010Du, /* tcpwm[0].tr_out0[12] */ 254 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT013 = 0x0000010Eu, /* tcpwm[0].tr_out0[13] */ 255 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT014 = 0x0000010Fu, /* tcpwm[0].tr_out0[14] */ 256 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT015 = 0x00000110u, /* tcpwm[0].tr_out0[15] */ 257 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT016 = 0x00000111u, /* tcpwm[0].tr_out0[16] */ 258 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT017 = 0x00000112u, /* tcpwm[0].tr_out0[17] */ 259 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT018 = 0x00000113u, /* tcpwm[0].tr_out0[18] */ 260 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT019 = 0x00000114u, /* tcpwm[0].tr_out0[19] */ 261 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT020 = 0x00000115u, /* tcpwm[0].tr_out0[20] */ 262 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT021 = 0x00000116u, /* tcpwm[0].tr_out0[21] */ 263 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT022 = 0x00000117u, /* tcpwm[0].tr_out0[22] */ 264 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT023 = 0x00000118u, /* tcpwm[0].tr_out0[23] */ 265 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT024 = 0x00000119u, /* tcpwm[0].tr_out0[24] */ 266 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT025 = 0x0000011Au, /* tcpwm[0].tr_out0[25] */ 267 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT026 = 0x0000011Bu, /* tcpwm[0].tr_out0[26] */ 268 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT027 = 0x0000011Cu, /* tcpwm[0].tr_out0[27] */ 269 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT028 = 0x0000011Du, /* tcpwm[0].tr_out0[28] */ 270 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT029 = 0x0000011Eu, /* tcpwm[0].tr_out0[29] */ 271 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT030 = 0x0000011Fu, /* tcpwm[0].tr_out0[30] */ 272 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT031 = 0x00000120u, /* tcpwm[0].tr_out0[31] */ 273 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT032 = 0x00000121u, /* tcpwm[0].tr_out0[32] */ 274 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT033 = 0x00000122u, /* tcpwm[0].tr_out0[33] */ 275 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT034 = 0x00000123u, /* tcpwm[0].tr_out0[34] */ 276 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT035 = 0x00000124u, /* tcpwm[0].tr_out0[35] */ 277 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT036 = 0x00000125u, /* tcpwm[0].tr_out0[36] */ 278 TRIG_IN_MUX_1_TCPWM0_16_TR_OUT037 = 0x00000126u, /* tcpwm[0].tr_out0[37] */ 279 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT00 = 0x00000127u, /* tcpwm[0].tr_out0[256] */ 280 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT01 = 0x00000128u, /* tcpwm[0].tr_out0[257] */ 281 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT02 = 0x00000129u, /* tcpwm[0].tr_out0[258] */ 282 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT03 = 0x0000012Au, /* tcpwm[0].tr_out0[259] */ 283 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT04 = 0x0000012Bu, /* tcpwm[0].tr_out0[260] */ 284 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT05 = 0x0000012Cu, /* tcpwm[0].tr_out0[261] */ 285 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT06 = 0x0000012Du, /* tcpwm[0].tr_out0[262] */ 286 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT07 = 0x0000012Eu, /* tcpwm[0].tr_out0[263] */ 287 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT08 = 0x0000012Fu, /* tcpwm[0].tr_out0[264] */ 288 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT09 = 0x00000130u, /* tcpwm[0].tr_out0[265] */ 289 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT010 = 0x00000131u, /* tcpwm[0].tr_out0[266] */ 290 TRIG_IN_MUX_1_TCPWM0_16M_TR_OUT011 = 0x00000132u, /* tcpwm[0].tr_out0[267] */ 291 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT00 = 0x00000133u, /* tcpwm[0].tr_out0[512] */ 292 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT01 = 0x00000134u, /* tcpwm[0].tr_out0[513] */ 293 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT02 = 0x00000135u, /* tcpwm[0].tr_out0[514] */ 294 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT03 = 0x00000136u, /* tcpwm[0].tr_out0[515] */ 295 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT04 = 0x00000137u, /* tcpwm[0].tr_out0[516] */ 296 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT05 = 0x00000138u, /* tcpwm[0].tr_out0[517] */ 297 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT06 = 0x00000139u, /* tcpwm[0].tr_out0[518] */ 298 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT07 = 0x0000013Au, /* tcpwm[0].tr_out0[519] */ 299 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT08 = 0x0000013Bu, /* tcpwm[0].tr_out0[520] */ 300 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT09 = 0x0000013Cu, /* tcpwm[0].tr_out0[521] */ 301 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT010 = 0x0000013Du, /* tcpwm[0].tr_out0[522] */ 302 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT011 = 0x0000013Eu, /* tcpwm[0].tr_out0[523] */ 303 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT012 = 0x0000013Fu, /* tcpwm[0].tr_out0[524] */ 304 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT013 = 0x00000140u, /* tcpwm[0].tr_out0[525] */ 305 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT014 = 0x00000141u, /* tcpwm[0].tr_out0[526] */ 306 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT015 = 0x00000142u, /* tcpwm[0].tr_out0[527] */ 307 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT016 = 0x00000143u, /* tcpwm[0].tr_out0[528] */ 308 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT017 = 0x00000144u, /* tcpwm[0].tr_out0[529] */ 309 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT018 = 0x00000145u, /* tcpwm[0].tr_out0[530] */ 310 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT019 = 0x00000146u, /* tcpwm[0].tr_out0[531] */ 311 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT020 = 0x00000147u, /* tcpwm[0].tr_out0[532] */ 312 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT021 = 0x00000148u, /* tcpwm[0].tr_out0[533] */ 313 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT022 = 0x00000149u, /* tcpwm[0].tr_out0[534] */ 314 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT023 = 0x0000014Au, /* tcpwm[0].tr_out0[535] */ 315 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT024 = 0x0000014Bu, /* tcpwm[0].tr_out0[536] */ 316 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT025 = 0x0000014Cu, /* tcpwm[0].tr_out0[537] */ 317 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT026 = 0x0000014Du, /* tcpwm[0].tr_out0[538] */ 318 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT027 = 0x0000014Eu, /* tcpwm[0].tr_out0[539] */ 319 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT028 = 0x0000014Fu, /* tcpwm[0].tr_out0[540] */ 320 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT029 = 0x00000150u, /* tcpwm[0].tr_out0[541] */ 321 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT030 = 0x00000151u, /* tcpwm[0].tr_out0[542] */ 322 TRIG_IN_MUX_1_TCPWM0_32_TR_OUT031 = 0x00000152u, /* tcpwm[0].tr_out0[543] */ 323 TRIG_IN_MUX_1_PASS_GEN_TR_OUT0 = 0x00000153u, /* pass[0].tr_sar_gen_out[0] */ 324 TRIG_IN_MUX_1_PASS_GEN_TR_OUT1 = 0x00000154u, /* pass[0].tr_sar_gen_out[1] */ 325 TRIG_IN_MUX_1_CTI_TR_OUT0 = 0x00000155u, /* cpuss.cti_tr_out[0] */ 326 TRIG_IN_MUX_1_CTI_TR_OUT1 = 0x00000156u, /* cpuss.cti_tr_out[1] */ 327 TRIG_IN_MUX_1_EVTGEN_TR_OUT0 = 0x00000157u, /* evtgen[0].tr_out[0] */ 328 TRIG_IN_MUX_1_EVTGEN_TR_OUT1 = 0x00000158u, /* evtgen[0].tr_out[1] */ 329 TRIG_IN_MUX_1_EVTGEN_TR_OUT2 = 0x00000159u, /* evtgen[0].tr_out[2] */ 330 TRIG_IN_MUX_1_EVTGEN_TR_OUT3 = 0x0000015Au /* evtgen[0].tr_out[3] */ 331 } en_trig_input_pdma0_16_31_t; 332 333 /* Trigger Input Group 2 - P-DMA1[0:15] Request Assignments */ 334 typedef enum 335 { 336 TRIG_IN_MUX_2_PDMA1_TR_OUT0 = 0x00000201u, /* cpuss.dw1_tr_out[0] */ 337 TRIG_IN_MUX_2_PDMA1_TR_OUT1 = 0x00000202u, /* cpuss.dw1_tr_out[1] */ 338 TRIG_IN_MUX_2_PDMA1_TR_OUT2 = 0x00000203u, /* cpuss.dw1_tr_out[2] */ 339 TRIG_IN_MUX_2_PDMA1_TR_OUT3 = 0x00000204u, /* cpuss.dw1_tr_out[3] */ 340 TRIG_IN_MUX_2_PDMA1_TR_OUT4 = 0x00000205u, /* cpuss.dw1_tr_out[4] */ 341 TRIG_IN_MUX_2_PDMA1_TR_OUT5 = 0x00000206u, /* cpuss.dw1_tr_out[5] */ 342 TRIG_IN_MUX_2_PDMA1_TR_OUT6 = 0x00000207u, /* cpuss.dw1_tr_out[6] */ 343 TRIG_IN_MUX_2_PDMA1_TR_OUT7 = 0x00000208u, /* cpuss.dw1_tr_out[7] */ 344 TRIG_IN_MUX_2_PDMA1_TR_OUT8 = 0x00000209u, /* cpuss.dw1_tr_out[8] */ 345 TRIG_IN_MUX_2_PDMA1_TR_OUT9 = 0x0000020Au, /* cpuss.dw1_tr_out[9] */ 346 TRIG_IN_MUX_2_PDMA1_TR_OUT10 = 0x0000020Bu, /* cpuss.dw1_tr_out[10] */ 347 TRIG_IN_MUX_2_PDMA1_TR_OUT11 = 0x0000020Cu, /* cpuss.dw1_tr_out[11] */ 348 TRIG_IN_MUX_2_PDMA1_TR_OUT12 = 0x0000020Du, /* cpuss.dw1_tr_out[12] */ 349 TRIG_IN_MUX_2_PDMA1_TR_OUT13 = 0x0000020Eu, /* cpuss.dw1_tr_out[13] */ 350 TRIG_IN_MUX_2_PDMA1_TR_OUT14 = 0x0000020Fu, /* cpuss.dw1_tr_out[14] */ 351 TRIG_IN_MUX_2_PDMA1_TR_OUT15 = 0x00000210u, /* cpuss.dw1_tr_out[15] */ 352 TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000211u, /* cpuss.dw0_tr_out[0] */ 353 TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000212u, /* cpuss.dw0_tr_out[1] */ 354 TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000213u, /* cpuss.dw0_tr_out[2] */ 355 TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000214u, /* cpuss.dw0_tr_out[3] */ 356 TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000215u, /* cpuss.dw0_tr_out[4] */ 357 TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000216u, /* cpuss.dw0_tr_out[5] */ 358 TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000217u, /* cpuss.dw0_tr_out[6] */ 359 TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000218u, /* cpuss.dw0_tr_out[7] */ 360 TRIG_IN_MUX_2_PDMA0_TR_OUT8 = 0x00000219u, /* cpuss.dw0_tr_out[8] */ 361 TRIG_IN_MUX_2_PDMA0_TR_OUT9 = 0x0000021Au, /* cpuss.dw0_tr_out[9] */ 362 TRIG_IN_MUX_2_PDMA0_TR_OUT10 = 0x0000021Bu, /* cpuss.dw0_tr_out[10] */ 363 TRIG_IN_MUX_2_PDMA0_TR_OUT11 = 0x0000021Cu, /* cpuss.dw0_tr_out[11] */ 364 TRIG_IN_MUX_2_PDMA0_TR_OUT12 = 0x0000021Du, /* cpuss.dw0_tr_out[12] */ 365 TRIG_IN_MUX_2_PDMA0_TR_OUT13 = 0x0000021Eu, /* cpuss.dw0_tr_out[13] */ 366 TRIG_IN_MUX_2_PDMA0_TR_OUT14 = 0x0000021Fu, /* cpuss.dw0_tr_out[14] */ 367 TRIG_IN_MUX_2_PDMA0_TR_OUT15 = 0x00000220u, /* cpuss.dw0_tr_out[15] */ 368 TRIG_IN_MUX_2_PDMA0_TR_OUT16 = 0x00000221u, /* cpuss.dw0_tr_out[16] */ 369 TRIG_IN_MUX_2_PDMA0_TR_OUT17 = 0x00000222u, /* cpuss.dw0_tr_out[17] */ 370 TRIG_IN_MUX_2_PDMA0_TR_OUT18 = 0x00000223u, /* cpuss.dw0_tr_out[18] */ 371 TRIG_IN_MUX_2_PDMA0_TR_OUT19 = 0x00000224u, /* cpuss.dw0_tr_out[19] */ 372 TRIG_IN_MUX_2_PDMA0_TR_OUT20 = 0x00000225u, /* cpuss.dw0_tr_out[20] */ 373 TRIG_IN_MUX_2_PDMA0_TR_OUT21 = 0x00000226u, /* cpuss.dw0_tr_out[21] */ 374 TRIG_IN_MUX_2_PDMA0_TR_OUT22 = 0x00000227u, /* cpuss.dw0_tr_out[22] */ 375 TRIG_IN_MUX_2_PDMA0_TR_OUT23 = 0x00000228u, /* cpuss.dw0_tr_out[23] */ 376 TRIG_IN_MUX_2_PDMA0_TR_OUT24 = 0x00000229u, /* cpuss.dw0_tr_out[24] */ 377 TRIG_IN_MUX_2_PDMA0_TR_OUT25 = 0x0000022Au, /* cpuss.dw0_tr_out[25] */ 378 TRIG_IN_MUX_2_PDMA0_TR_OUT26 = 0x0000022Bu, /* cpuss.dw0_tr_out[26] */ 379 TRIG_IN_MUX_2_PDMA0_TR_OUT27 = 0x0000022Cu, /* cpuss.dw0_tr_out[27] */ 380 TRIG_IN_MUX_2_PDMA0_TR_OUT28 = 0x0000022Du, /* cpuss.dw0_tr_out[28] */ 381 TRIG_IN_MUX_2_PDMA0_TR_OUT29 = 0x0000022Eu, /* cpuss.dw0_tr_out[29] */ 382 TRIG_IN_MUX_2_PDMA0_TR_OUT30 = 0x0000022Fu, /* cpuss.dw0_tr_out[30] */ 383 TRIG_IN_MUX_2_PDMA0_TR_OUT31 = 0x00000230u, /* cpuss.dw0_tr_out[31] */ 384 TRIG_IN_MUX_2_HSIOM_IO_INPUT24 = 0x00000231u, /* peri.tr_io_input[24] */ 385 TRIG_IN_MUX_2_HSIOM_IO_INPUT25 = 0x00000232u, /* peri.tr_io_input[25] */ 386 TRIG_IN_MUX_2_HSIOM_IO_INPUT26 = 0x00000233u, /* peri.tr_io_input[26] */ 387 TRIG_IN_MUX_2_HSIOM_IO_INPUT27 = 0x00000234u, /* peri.tr_io_input[27] */ 388 TRIG_IN_MUX_2_HSIOM_IO_INPUT28 = 0x00000235u, /* peri.tr_io_input[28] */ 389 TRIG_IN_MUX_2_HSIOM_IO_INPUT29 = 0x00000236u, /* peri.tr_io_input[29] */ 390 TRIG_IN_MUX_2_HSIOM_IO_INPUT30 = 0x00000237u, /* peri.tr_io_input[30] */ 391 TRIG_IN_MUX_2_HSIOM_IO_INPUT31 = 0x00000238u, /* peri.tr_io_input[31] */ 392 TRIG_IN_MUX_2_HSIOM_IO_INPUT32 = 0x00000239u, /* peri.tr_io_input[32] */ 393 TRIG_IN_MUX_2_HSIOM_IO_INPUT33 = 0x0000023Au, /* peri.tr_io_input[33] */ 394 TRIG_IN_MUX_2_HSIOM_IO_INPUT34 = 0x0000023Bu, /* peri.tr_io_input[34] */ 395 TRIG_IN_MUX_2_HSIOM_IO_INPUT35 = 0x0000023Cu, /* peri.tr_io_input[35] */ 396 TRIG_IN_MUX_2_HSIOM_IO_INPUT36 = 0x0000023Du, /* peri.tr_io_input[36] */ 397 TRIG_IN_MUX_2_HSIOM_IO_INPUT37 = 0x0000023Eu, /* peri.tr_io_input[37] */ 398 TRIG_IN_MUX_2_HSIOM_IO_INPUT38 = 0x0000023Fu, /* peri.tr_io_input[38] */ 399 TRIG_IN_MUX_2_HSIOM_IO_INPUT39 = 0x00000240u, /* peri.tr_io_input[39] */ 400 TRIG_IN_MUX_2_HSIOM_IO_INPUT40 = 0x00000241u, /* peri.tr_io_input[40] */ 401 TRIG_IN_MUX_2_HSIOM_IO_INPUT41 = 0x00000242u, /* peri.tr_io_input[41] */ 402 TRIG_IN_MUX_2_HSIOM_IO_INPUT42 = 0x00000243u, /* peri.tr_io_input[42] */ 403 TRIG_IN_MUX_2_HSIOM_IO_INPUT43 = 0x00000244u, /* peri.tr_io_input[43] */ 404 TRIG_IN_MUX_2_HSIOM_IO_INPUT44 = 0x00000245u, /* peri.tr_io_input[44] */ 405 TRIG_IN_MUX_2_HSIOM_IO_INPUT45 = 0x00000246u, /* peri.tr_io_input[45] */ 406 TRIG_IN_MUX_2_HSIOM_IO_INPUT46 = 0x00000247u, /* peri.tr_io_input[46] */ 407 TRIG_IN_MUX_2_HSIOM_IO_INPUT47 = 0x00000248u /* peri.tr_io_input[47] */ 408 } en_trig_input_pdma1_0_15_t; 409 410 /* Trigger Input Group 3 - M-DMA Request Assignments */ 411 typedef enum 412 { 413 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT00 = 0x00000301u, /* tcpwm[0].tr_out0[0] */ 414 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT01 = 0x00000302u, /* tcpwm[0].tr_out0[1] */ 415 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT02 = 0x00000303u, /* tcpwm[0].tr_out0[2] */ 416 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT03 = 0x00000304u, /* tcpwm[0].tr_out0[3] */ 417 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT04 = 0x00000305u, /* tcpwm[0].tr_out0[4] */ 418 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT05 = 0x00000306u, /* tcpwm[0].tr_out0[5] */ 419 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT06 = 0x00000307u, /* tcpwm[0].tr_out0[6] */ 420 TRIG_IN_MUX_3_TCPWM0_16_TR_OUT07 = 0x00000308u, /* tcpwm[0].tr_out0[7] */ 421 TRIG_IN_MUX_3_TCPWM0_32_TR_OUT00 = 0x00000309u, /* tcpwm[0].tr_out0[512] */ 422 TRIG_IN_MUX_3_TCPWM0_32_TR_OUT01 = 0x0000030Au, /* tcpwm[0].tr_out0[513] */ 423 TRIG_IN_MUX_3_TCPWM0_32_TR_OUT02 = 0x0000030Bu, /* tcpwm[0].tr_out0[514] */ 424 TRIG_IN_MUX_3_TCPWM0_32_TR_OUT03 = 0x0000030Cu, /* tcpwm[0].tr_out0[515] */ 425 TRIG_IN_MUX_3_TCPWM0_32_TR_OUT04 = 0x0000030Du, /* tcpwm[0].tr_out0[516] */ 426 TRIG_IN_MUX_3_TCPWM0_32_TR_OUT05 = 0x0000030Eu, /* tcpwm[0].tr_out0[517] */ 427 TRIG_IN_MUX_3_TCPWM0_32_TR_OUT06 = 0x0000030Fu, /* tcpwm[0].tr_out0[518] */ 428 TRIG_IN_MUX_3_TCPWM0_32_TR_OUT07 = 0x00000310u, /* tcpwm[0].tr_out0[519] */ 429 TRIG_IN_MUX_3_AXIDMA_TR_OUT0 = 0x00000311u, /* axi_dmac[0].tr_out[0] */ 430 TRIG_IN_MUX_3_AXIDMA_TR_OUT1 = 0x00000312u, /* axi_dmac[0].tr_out[1] */ 431 TRIG_IN_MUX_3_AXIDMA_TR_OUT2 = 0x00000313u, /* axi_dmac[0].tr_out[2] */ 432 TRIG_IN_MUX_3_AXIDMA_TR_OUT3 = 0x00000314u /* axi_dmac[0].tr_out[3] */ 433 } en_trig_input_mdma_t; 434 435 /* Trigger Input Group 4 - */ 436 typedef enum 437 { 438 TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ 439 TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ 440 TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ 441 TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ 442 TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ 443 TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ 444 TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ 445 TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ 446 TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ 447 TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ 448 TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ 449 TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ 450 TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ 451 TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ 452 TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ 453 TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ 454 TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ 455 TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ 456 TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ 457 TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ 458 TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ 459 TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ 460 TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ 461 TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ 462 TRIG_IN_MUX_4_PDMA0_TR_OUT24 = 0x00000419u, /* cpuss.dw0_tr_out[24] */ 463 TRIG_IN_MUX_4_PDMA0_TR_OUT25 = 0x0000041Au, /* cpuss.dw0_tr_out[25] */ 464 TRIG_IN_MUX_4_PDMA0_TR_OUT26 = 0x0000041Bu, /* cpuss.dw0_tr_out[26] */ 465 TRIG_IN_MUX_4_PDMA0_TR_OUT27 = 0x0000041Cu, /* cpuss.dw0_tr_out[27] */ 466 TRIG_IN_MUX_4_PDMA0_TR_OUT28 = 0x0000041Du, /* cpuss.dw0_tr_out[28] */ 467 TRIG_IN_MUX_4_PDMA0_TR_OUT29 = 0x0000041Eu, /* cpuss.dw0_tr_out[29] */ 468 TRIG_IN_MUX_4_PDMA0_TR_OUT30 = 0x0000041Fu, /* cpuss.dw0_tr_out[30] */ 469 TRIG_IN_MUX_4_PDMA0_TR_OUT31 = 0x00000420u, /* cpuss.dw0_tr_out[31] */ 470 TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x00000421u, /* cpuss.dw1_tr_out[0] */ 471 TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x00000422u, /* cpuss.dw1_tr_out[1] */ 472 TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x00000423u, /* cpuss.dw1_tr_out[2] */ 473 TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x00000424u, /* cpuss.dw1_tr_out[3] */ 474 TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x00000425u, /* cpuss.dw1_tr_out[4] */ 475 TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x00000426u, /* cpuss.dw1_tr_out[5] */ 476 TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x00000427u, /* cpuss.dw1_tr_out[6] */ 477 TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000428u, /* cpuss.dw1_tr_out[7] */ 478 TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000429u, /* cpuss.dw1_tr_out[8] */ 479 TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x0000042Au, /* cpuss.dw1_tr_out[9] */ 480 TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x0000042Bu, /* cpuss.dw1_tr_out[10] */ 481 TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x0000042Cu, /* cpuss.dw1_tr_out[11] */ 482 TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x0000042Du, /* cpuss.dw1_tr_out[12] */ 483 TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x0000042Eu, /* cpuss.dw1_tr_out[13] */ 484 TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x0000042Fu, /* cpuss.dw1_tr_out[14] */ 485 TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x00000430u, /* cpuss.dw1_tr_out[15] */ 486 TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x00000431u, /* cpuss.dmac_tr_out[0] */ 487 TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x00000432u, /* cpuss.dmac_tr_out[1] */ 488 TRIG_IN_MUX_4_MDMA_TR_OUT2 = 0x00000433u, /* cpuss.dmac_tr_out[2] */ 489 TRIG_IN_MUX_4_MDMA_TR_OUT3 = 0x00000434u, /* cpuss.dmac_tr_out[3] */ 490 TRIG_IN_MUX_4_MDMA_TR_OUT4 = 0x00000435u, /* cpuss.dmac_tr_out[4] */ 491 TRIG_IN_MUX_4_MDMA_TR_OUT5 = 0x00000436u, /* cpuss.dmac_tr_out[5] */ 492 TRIG_IN_MUX_4_MDMA_TR_OUT6 = 0x00000437u, /* cpuss.dmac_tr_out[6] */ 493 TRIG_IN_MUX_4_MDMA_TR_OUT7 = 0x00000438u, /* cpuss.dmac_tr_out[7] */ 494 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT00 = 0x00000439u, /* tcpwm[0].tr_out0[0] */ 495 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT01 = 0x0000043Au, /* tcpwm[0].tr_out0[1] */ 496 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT02 = 0x0000043Bu, /* tcpwm[0].tr_out0[2] */ 497 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT03 = 0x0000043Cu, /* tcpwm[0].tr_out0[3] */ 498 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT04 = 0x0000043Du, /* tcpwm[0].tr_out0[4] */ 499 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT05 = 0x0000043Eu, /* tcpwm[0].tr_out0[5] */ 500 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT06 = 0x0000043Fu, /* tcpwm[0].tr_out0[6] */ 501 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT07 = 0x00000440u, /* tcpwm[0].tr_out0[7] */ 502 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT08 = 0x00000441u, /* tcpwm[0].tr_out0[8] */ 503 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT09 = 0x00000442u, /* tcpwm[0].tr_out0[9] */ 504 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT010 = 0x00000443u, /* tcpwm[0].tr_out0[10] */ 505 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT011 = 0x00000444u, /* tcpwm[0].tr_out0[11] */ 506 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT012 = 0x00000445u, /* tcpwm[0].tr_out0[12] */ 507 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT013 = 0x00000446u, /* tcpwm[0].tr_out0[13] */ 508 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT014 = 0x00000447u, /* tcpwm[0].tr_out0[14] */ 509 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT015 = 0x00000448u, /* tcpwm[0].tr_out0[15] */ 510 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT016 = 0x00000449u, /* tcpwm[0].tr_out0[16] */ 511 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT017 = 0x0000044Au, /* tcpwm[0].tr_out0[17] */ 512 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT018 = 0x0000044Bu, /* tcpwm[0].tr_out0[18] */ 513 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT019 = 0x0000044Cu, /* tcpwm[0].tr_out0[19] */ 514 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT020 = 0x0000044Du, /* tcpwm[0].tr_out0[20] */ 515 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT021 = 0x0000044Eu, /* tcpwm[0].tr_out0[21] */ 516 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT022 = 0x0000044Fu, /* tcpwm[0].tr_out0[22] */ 517 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT023 = 0x00000450u, /* tcpwm[0].tr_out0[23] */ 518 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT024 = 0x00000451u, /* tcpwm[0].tr_out0[24] */ 519 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT025 = 0x00000452u, /* tcpwm[0].tr_out0[25] */ 520 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT026 = 0x00000453u, /* tcpwm[0].tr_out0[26] */ 521 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT027 = 0x00000454u, /* tcpwm[0].tr_out0[27] */ 522 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT028 = 0x00000455u, /* tcpwm[0].tr_out0[28] */ 523 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT029 = 0x00000456u, /* tcpwm[0].tr_out0[29] */ 524 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT030 = 0x00000457u, /* tcpwm[0].tr_out0[30] */ 525 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT031 = 0x00000458u, /* tcpwm[0].tr_out0[31] */ 526 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT032 = 0x00000459u, /* tcpwm[0].tr_out0[32] */ 527 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT033 = 0x0000045Au, /* tcpwm[0].tr_out0[33] */ 528 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT034 = 0x0000045Bu, /* tcpwm[0].tr_out0[34] */ 529 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT035 = 0x0000045Cu, /* tcpwm[0].tr_out0[35] */ 530 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT036 = 0x0000045Du, /* tcpwm[0].tr_out0[36] */ 531 TRIG_IN_MUX_4_TCPWM0_16_TR_OUT037 = 0x0000045Eu, /* tcpwm[0].tr_out0[37] */ 532 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT00 = 0x0000045Fu, /* tcpwm[0].tr_out0[256] */ 533 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT01 = 0x00000460u, /* tcpwm[0].tr_out0[257] */ 534 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT02 = 0x00000461u, /* tcpwm[0].tr_out0[258] */ 535 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT03 = 0x00000462u, /* tcpwm[0].tr_out0[259] */ 536 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT04 = 0x00000463u, /* tcpwm[0].tr_out0[260] */ 537 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT05 = 0x00000464u, /* tcpwm[0].tr_out0[261] */ 538 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT06 = 0x00000465u, /* tcpwm[0].tr_out0[262] */ 539 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT07 = 0x00000466u, /* tcpwm[0].tr_out0[263] */ 540 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT08 = 0x00000467u, /* tcpwm[0].tr_out0[264] */ 541 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT09 = 0x00000468u, /* tcpwm[0].tr_out0[265] */ 542 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT010 = 0x00000469u, /* tcpwm[0].tr_out0[266] */ 543 TRIG_IN_MUX_4_TCPWM0_16M_TR_OUT011 = 0x0000046Au, /* tcpwm[0].tr_out0[267] */ 544 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT00 = 0x0000046Bu, /* tcpwm[0].tr_out0[512] */ 545 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT01 = 0x0000046Cu, /* tcpwm[0].tr_out0[513] */ 546 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT02 = 0x0000046Du, /* tcpwm[0].tr_out0[514] */ 547 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT03 = 0x0000046Eu, /* tcpwm[0].tr_out0[515] */ 548 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT04 = 0x0000046Fu, /* tcpwm[0].tr_out0[516] */ 549 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT05 = 0x00000470u, /* tcpwm[0].tr_out0[517] */ 550 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT06 = 0x00000471u, /* tcpwm[0].tr_out0[518] */ 551 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT07 = 0x00000472u, /* tcpwm[0].tr_out0[519] */ 552 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT08 = 0x00000473u, /* tcpwm[0].tr_out0[520] */ 553 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT09 = 0x00000474u, /* tcpwm[0].tr_out0[521] */ 554 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT010 = 0x00000475u, /* tcpwm[0].tr_out0[522] */ 555 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT011 = 0x00000476u, /* tcpwm[0].tr_out0[523] */ 556 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT012 = 0x00000477u, /* tcpwm[0].tr_out0[524] */ 557 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT013 = 0x00000478u, /* tcpwm[0].tr_out0[525] */ 558 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT014 = 0x00000479u, /* tcpwm[0].tr_out0[526] */ 559 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT015 = 0x0000047Au, /* tcpwm[0].tr_out0[527] */ 560 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT016 = 0x0000047Bu, /* tcpwm[0].tr_out0[528] */ 561 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT017 = 0x0000047Cu, /* tcpwm[0].tr_out0[529] */ 562 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT018 = 0x0000047Du, /* tcpwm[0].tr_out0[530] */ 563 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT019 = 0x0000047Eu, /* tcpwm[0].tr_out0[531] */ 564 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT020 = 0x0000047Fu, /* tcpwm[0].tr_out0[532] */ 565 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT021 = 0x00000480u, /* tcpwm[0].tr_out0[533] */ 566 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT022 = 0x00000481u, /* tcpwm[0].tr_out0[534] */ 567 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT023 = 0x00000482u, /* tcpwm[0].tr_out0[535] */ 568 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT024 = 0x00000483u, /* tcpwm[0].tr_out0[536] */ 569 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT025 = 0x00000484u, /* tcpwm[0].tr_out0[537] */ 570 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT026 = 0x00000485u, /* tcpwm[0].tr_out0[538] */ 571 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT027 = 0x00000486u, /* tcpwm[0].tr_out0[539] */ 572 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT028 = 0x00000487u, /* tcpwm[0].tr_out0[540] */ 573 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT029 = 0x00000488u, /* tcpwm[0].tr_out0[541] */ 574 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT030 = 0x00000489u, /* tcpwm[0].tr_out0[542] */ 575 TRIG_IN_MUX_4_TCPWM0_32_TR_OUT031 = 0x0000048Au, /* tcpwm[0].tr_out0[543] */ 576 TRIG_IN_MUX_4_SMIF0_TX_TR_OUT = 0x0000048Bu, /* smif[0].smif0_tr_tx_req */ 577 TRIG_IN_MUX_4_SMIF0_RX_TR_OUT = 0x0000048Cu, /* smif[0].smif0_tr_rx_req */ 578 TRIG_IN_MUX_4_SMIF1_TX_TR_OUT = 0x0000048Du, /* smif[0].smif1_tr_tx_req */ 579 TRIG_IN_MUX_4_SMIF1_RX_TR_OUT = 0x0000048Eu, /* smif[0].smif1_tr_rx_req */ 580 TRIG_IN_MUX_4_AXIDMA_TR_OUT0 = 0x0000048Fu, /* axi_dmac[0].tr_out[0] */ 581 TRIG_IN_MUX_4_AXIDMA_TR_OUT1 = 0x00000490u, /* axi_dmac[0].tr_out[1] */ 582 TRIG_IN_MUX_4_AXIDMA_TR_OUT2 = 0x00000491u, /* axi_dmac[0].tr_out[2] */ 583 TRIG_IN_MUX_4_AXIDMA_TR_OUT3 = 0x00000492u, /* axi_dmac[0].tr_out[3] */ 584 TRIG_IN_MUX_4_TDM0_TX_TR_OUT0 = 0x00000497u, /* tdm[0].tr_tx_req[0] */ 585 TRIG_IN_MUX_4_TDM0_TX_TR_OUT1 = 0x00000498u, /* tdm[0].tr_tx_req[1] */ 586 TRIG_IN_MUX_4_TDM0_TX_TR_OUT2 = 0x00000499u, /* tdm[0].tr_tx_req[2] */ 587 TRIG_IN_MUX_4_TDM0_TX_TR_OUT3 = 0x0000049Au, /* tdm[0].tr_tx_req[3] */ 588 TRIG_IN_MUX_4_TDM0_RX_TR_OUT0 = 0x0000049Bu, /* tdm[0].tr_rx_req[0] */ 589 TRIG_IN_MUX_4_TDM0_RX_TR_OUT1 = 0x0000049Cu, /* tdm[0].tr_rx_req[1] */ 590 TRIG_IN_MUX_4_TDM0_RX_TR_OUT2 = 0x0000049Du, /* tdm[0].tr_rx_req[2] */ 591 TRIG_IN_MUX_4_TDM0_RX_TR_OUT3 = 0x0000049Eu, /* tdm[0].tr_rx_req[3] */ 592 TRIG_IN_MUX_4_SG0_TR_COMPLETE0 = 0x0000049Fu, /* sg[0].tr_complete[0] */ 593 TRIG_IN_MUX_4_SG0_TR_COMPLETE1 = 0x000004A0u, /* sg[0].tr_complete[1] */ 594 TRIG_IN_MUX_4_SG0_TR_COMPLETE2 = 0x000004A1u, /* sg[0].tr_complete[2] */ 595 TRIG_IN_MUX_4_SG0_TR_COMPLETE3 = 0x000004A2u, /* sg[0].tr_complete[3] */ 596 TRIG_IN_MUX_4_SG0_TR_COMPLETE4 = 0x000004A3u, /* sg[0].tr_complete[4] */ 597 TRIG_IN_MUX_4_PWM0_TX_TR_OUT0 = 0x000004A4u, /* pwm[0].tr_tx_req[0] */ 598 TRIG_IN_MUX_4_PWM0_TX_TR_OUT1 = 0x000004A5u, /* pwm[0].tr_tx_req[1] */ 599 TRIG_IN_MUX_4_MIXER0_TR_SRC_REQ_OUT0 = 0x000004A6u, /* mixer[0].tr_src_req[0] */ 600 TRIG_IN_MUX_4_MIXER0_TR_SRC_REQ_OUT1 = 0x000004A7u, /* mixer[0].tr_src_req[1] */ 601 TRIG_IN_MUX_4_MIXER0_TR_SRC_REQ_OUT2 = 0x000004A8u, /* mixer[0].tr_src_req[2] */ 602 TRIG_IN_MUX_4_MIXER0_TR_SRC_REQ_OUT3 = 0x000004A9u, /* mixer[0].tr_src_req[3] */ 603 TRIG_IN_MUX_4_MIXER0_TR_SRC_REQ_OUT4 = 0x000004AAu, /* mixer[0].tr_src_req[4] */ 604 TRIG_IN_MUX_4_MIXER0_TR_DST_REQ_OUT = 0x000004ABu, /* mixer[0].tr_dst_req */ 605 TRIG_IN_MUX_4_MIXER1_TR_SRC_REQ_OUT0 = 0x000004ACu, /* mixer[1].tr_src_req[0] */ 606 TRIG_IN_MUX_4_MIXER1_TR_SRC_REQ_OUT1 = 0x000004ADu, /* mixer[1].tr_src_req[1] */ 607 TRIG_IN_MUX_4_MIXER1_TR_SRC_REQ_OUT2 = 0x000004AEu, /* mixer[1].tr_src_req[2] */ 608 TRIG_IN_MUX_4_MIXER1_TR_SRC_REQ_OUT3 = 0x000004AFu, /* mixer[1].tr_src_req[3] */ 609 TRIG_IN_MUX_4_MIXER1_TR_SRC_REQ_OUT4 = 0x000004B0u, /* mixer[1].tr_src_req[4] */ 610 TRIG_IN_MUX_4_MIXER1_TR_DST_REQ_OUT = 0x000004B1u, /* mixer[1].tr_dst_req */ 611 TRIG_IN_MUX_4_AUDIODAC0_TX_TR_OUT = 0x000004B2u /* dac[0].tr_tx_req */ 612 } en_trig_input_tcpwm0_t; 613 614 /* Trigger Input Group 5 - */ 615 typedef enum 616 { 617 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT0 = 0x00000501u, /* canfd[0].tr_dbg_dma_req[0] */ 618 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT1 = 0x00000502u, /* canfd[0].tr_dbg_dma_req[1] */ 619 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT0 = 0x00000503u, /* canfd[0].tr_fifo0[0] */ 620 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT1 = 0x00000504u, /* canfd[0].tr_fifo0[1] */ 621 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT0 = 0x00000505u, /* canfd[0].tr_fifo1[0] */ 622 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT1 = 0x00000506u, /* canfd[0].tr_fifo1[1] */ 623 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT0 = 0x00000507u, /* canfd[1].tr_dbg_dma_req[0] */ 624 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT1 = 0x00000508u, /* canfd[1].tr_dbg_dma_req[1] */ 625 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT0 = 0x00000509u, /* canfd[1].tr_fifo0[0] */ 626 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT1 = 0x0000050Au, /* canfd[1].tr_fifo0[1] */ 627 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT0 = 0x0000050Bu, /* canfd[1].tr_fifo1[0] */ 628 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT1 = 0x0000050Cu, /* canfd[1].tr_fifo1[1] */ 629 TRIG_IN_MUX_5_CAN0_TT_TR_OUT0 = 0x0000050Du, /* canfd[0].tr_tmp_rtp_out[0] */ 630 TRIG_IN_MUX_5_CAN0_TT_TR_OUT1 = 0x0000050Eu, /* canfd[0].tr_tmp_rtp_out[1] */ 631 TRIG_IN_MUX_5_CAN1_TT_TR_OUT0 = 0x0000050Fu, /* canfd[1].tr_tmp_rtp_out[0] */ 632 TRIG_IN_MUX_5_CAN1_TT_TR_OUT1 = 0x00000510u, /* canfd[1].tr_tmp_rtp_out[1] */ 633 TRIG_IN_MUX_5_EVTGEN_TR_OUT4 = 0x00000511u, /* evtgen[0].tr_out[4] */ 634 TRIG_IN_MUX_5_EVTGEN_TR_OUT5 = 0x00000512u, /* evtgen[0].tr_out[5] */ 635 TRIG_IN_MUX_5_EVTGEN_TR_OUT6 = 0x00000513u, /* evtgen[0].tr_out[6] */ 636 TRIG_IN_MUX_5_EVTGEN_TR_OUT7 = 0x00000514u, /* evtgen[0].tr_out[7] */ 637 TRIG_IN_MUX_5_EVTGEN_TR_OUT8 = 0x00000515u, /* evtgen[0].tr_out[8] */ 638 TRIG_IN_MUX_5_EVTGEN_TR_OUT9 = 0x00000516u, /* evtgen[0].tr_out[9] */ 639 TRIG_IN_MUX_5_EVTGEN_TR_OUT10 = 0x00000517u, /* evtgen[0].tr_out[10] */ 640 TRIG_IN_MUX_5_EVTGEN_TR_OUT11 = 0x00000518u /* evtgen[0].tr_out[11] */ 641 } en_trig_input_tcpwm0_20_31_t; 642 643 /* Trigger Input Group 6 - TCPWM trigger inputs */ 644 typedef enum 645 { 646 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT10 = 0x00000601u, /* tcpwm[0].tr_out1[0] */ 647 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT11 = 0x00000602u, /* tcpwm[0].tr_out1[1] */ 648 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT12 = 0x00000603u, /* tcpwm[0].tr_out1[2] */ 649 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT13 = 0x00000604u, /* tcpwm[0].tr_out1[3] */ 650 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT14 = 0x00000605u, /* tcpwm[0].tr_out1[4] */ 651 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT15 = 0x00000606u, /* tcpwm[0].tr_out1[5] */ 652 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT16 = 0x00000607u, /* tcpwm[0].tr_out1[6] */ 653 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT17 = 0x00000608u, /* tcpwm[0].tr_out1[7] */ 654 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT18 = 0x00000609u, /* tcpwm[0].tr_out1[8] */ 655 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT19 = 0x0000060Au, /* tcpwm[0].tr_out1[9] */ 656 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT110 = 0x0000060Bu, /* tcpwm[0].tr_out1[10] */ 657 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT111 = 0x0000060Cu, /* tcpwm[0].tr_out1[11] */ 658 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT112 = 0x0000060Du, /* tcpwm[0].tr_out1[12] */ 659 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT113 = 0x0000060Eu, /* tcpwm[0].tr_out1[13] */ 660 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT114 = 0x0000060Fu, /* tcpwm[0].tr_out1[14] */ 661 TRIG_IN_MUX_6_TCPWM0_16_TR_OUT115 = 0x00000610u, /* tcpwm[0].tr_out1[15] */ 662 TRIG_IN_MUX_6_SCB_TX_TR_OUT0 = 0x00000611u, /* scb[0].tr_tx_req */ 663 TRIG_IN_MUX_6_SCB_RX_TR_OUT0 = 0x00000612u, /* scb[0].tr_rx_req */ 664 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT0 = 0x00000613u, /* scb[0].tr_i2c_scl_filtered */ 665 TRIG_IN_MUX_6_SCB_TX_TR_OUT1 = 0x00000614u, /* scb[1].tr_tx_req */ 666 TRIG_IN_MUX_6_SCB_RX_TR_OUT1 = 0x00000615u, /* scb[1].tr_rx_req */ 667 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT1 = 0x00000616u, /* scb[1].tr_i2c_scl_filtered */ 668 TRIG_IN_MUX_6_SCB_TX_TR_OUT2 = 0x00000617u, /* scb[2].tr_tx_req */ 669 TRIG_IN_MUX_6_SCB_RX_TR_OUT2 = 0x00000618u, /* scb[2].tr_rx_req */ 670 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT2 = 0x00000619u, /* scb[2].tr_i2c_scl_filtered */ 671 TRIG_IN_MUX_6_SCB_TX_TR_OUT3 = 0x0000061Au, /* scb[3].tr_tx_req */ 672 TRIG_IN_MUX_6_SCB_RX_TR_OUT3 = 0x0000061Bu, /* scb[3].tr_rx_req */ 673 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT3 = 0x0000061Cu, /* scb[3].tr_i2c_scl_filtered */ 674 TRIG_IN_MUX_6_SCB_TX_TR_OUT4 = 0x0000061Du, /* scb[4].tr_tx_req */ 675 TRIG_IN_MUX_6_SCB_RX_TR_OUT4 = 0x0000061Eu, /* scb[4].tr_rx_req */ 676 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT4 = 0x0000061Fu, /* scb[4].tr_i2c_scl_filtered */ 677 TRIG_IN_MUX_6_SCB_TX_TR_OUT5 = 0x00000620u, /* scb[5].tr_tx_req */ 678 TRIG_IN_MUX_6_SCB_RX_TR_OUT5 = 0x00000621u, /* scb[5].tr_rx_req */ 679 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT5 = 0x00000622u, /* scb[5].tr_i2c_scl_filtered */ 680 TRIG_IN_MUX_6_SCB_TX_TR_OUT6 = 0x00000623u, /* scb[6].tr_tx_req */ 681 TRIG_IN_MUX_6_SCB_RX_TR_OUT6 = 0x00000624u, /* scb[6].tr_rx_req */ 682 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT6 = 0x00000625u, /* scb[6].tr_i2c_scl_filtered */ 683 TRIG_IN_MUX_6_SCB_TX_TR_OUT7 = 0x00000626u, /* scb[7].tr_tx_req */ 684 TRIG_IN_MUX_6_SCB_RX_TR_OUT7 = 0x00000627u, /* scb[7].tr_rx_req */ 685 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT7 = 0x00000628u, /* scb[7].tr_i2c_scl_filtered */ 686 TRIG_IN_MUX_6_SCB_TX_TR_OUT8 = 0x00000629u, /* scb[8].tr_tx_req */ 687 TRIG_IN_MUX_6_SCB_RX_TR_OUT8 = 0x0000062Au, /* scb[8].tr_rx_req */ 688 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT8 = 0x0000062Bu, /* scb[8].tr_i2c_scl_filtered */ 689 TRIG_IN_MUX_6_SCB_TX_TR_OUT9 = 0x0000062Cu, /* scb[9].tr_tx_req */ 690 TRIG_IN_MUX_6_CB_RX_TR_OUT9 = 0x0000062Du, /* scb[9].tr_rx_req */ 691 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT9 = 0x0000062Eu, /* scb[9].tr_i2c_scl_filtered */ 692 TRIG_IN_MUX_6_SCB_TX_TR_OUT10 = 0x0000062Fu, /* scb[10].tr_tx_req */ 693 TRIG_IN_MUX_6_SCB_RX_TR_OUT10 = 0x00000630u, /* scb[10].tr_rx_req */ 694 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT10 = 0x00000631u, /* scb[10].tr_i2c_scl_filtered */ 695 TRIG_IN_MUX_6_SCB_TX_TR_OUT11 = 0x00000632u, /* scb[11].tr_tx_req */ 696 TRIG_IN_MUX_6_SCB_RX_TR_OUT11 = 0x00000633u, /* scb[11].tr_rx_req */ 697 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT11 = 0x00000634u, /* scb[11].tr_i2c_scl_filtered */ 698 TRIG_IN_MUX_6_PASS_GEN_TR_OUT0 = 0x00000635u, /* pass[0].tr_sar_gen_out[0] */ 699 TRIG_IN_MUX_6_PASS_GEN_TR_OUT1 = 0x00000636u, /* pass[0].tr_sar_gen_out[1] */ 700 TRIG_IN_MUX_6_HSIOM_IO_INPUT0 = 0x00000637u, /* peri.tr_io_input[0] */ 701 TRIG_IN_MUX_6_HSIOM_IO_INPUT1 = 0x00000638u, /* peri.tr_io_input[1] */ 702 TRIG_IN_MUX_6_HSIOM_IO_INPUT2 = 0x00000639u, /* peri.tr_io_input[2] */ 703 TRIG_IN_MUX_6_HSIOM_IO_INPUT3 = 0x0000063Au, /* peri.tr_io_input[3] */ 704 TRIG_IN_MUX_6_HSIOM_IO_INPUT4 = 0x0000063Bu, /* peri.tr_io_input[4] */ 705 TRIG_IN_MUX_6_HSIOM_IO_INPUT5 = 0x0000063Cu, /* peri.tr_io_input[5] */ 706 TRIG_IN_MUX_6_HSIOM_IO_INPUT6 = 0x0000063Du, /* peri.tr_io_input[6] */ 707 TRIG_IN_MUX_6_HSIOM_IO_INPUT7 = 0x0000063Eu, /* peri.tr_io_input[7] */ 708 TRIG_IN_MUX_6_HSIOM_IO_INPUT8 = 0x0000063Fu, /* peri.tr_io_input[8] */ 709 TRIG_IN_MUX_6_HSIOM_IO_INPUT9 = 0x00000640u, /* peri.tr_io_input[9] */ 710 TRIG_IN_MUX_6_HSIOM_IO_INPUT10 = 0x00000641u, /* peri.tr_io_input[10] */ 711 TRIG_IN_MUX_6_HSIOM_IO_INPUT11 = 0x00000642u, /* peri.tr_io_input[11] */ 712 TRIG_IN_MUX_6_HSIOM_IO_INPUT12 = 0x00000643u, /* peri.tr_io_input[12] */ 713 TRIG_IN_MUX_6_HSIOM_IO_INPUT13 = 0x00000644u, /* peri.tr_io_input[13] */ 714 TRIG_IN_MUX_6_HSIOM_IO_INPUT14 = 0x00000645u, /* peri.tr_io_input[14] */ 715 TRIG_IN_MUX_6_HSIOM_IO_INPUT15 = 0x00000646u, /* peri.tr_io_input[15] */ 716 TRIG_IN_MUX_6_HSIOM_IO_INPUT16 = 0x00000647u, /* peri.tr_io_input[16] */ 717 TRIG_IN_MUX_6_HSIOM_IO_INPUT17 = 0x00000648u, /* peri.tr_io_input[17] */ 718 TRIG_IN_MUX_6_HSIOM_IO_INPUT18 = 0x00000649u, /* peri.tr_io_input[18] */ 719 TRIG_IN_MUX_6_HSIOM_IO_INPUT19 = 0x0000064Au, /* peri.tr_io_input[19] */ 720 TRIG_IN_MUX_6_HSIOM_IO_INPUT20 = 0x0000064Bu, /* peri.tr_io_input[20] */ 721 TRIG_IN_MUX_6_HSIOM_IO_INPUT21 = 0x0000064Cu, /* peri.tr_io_input[21] */ 722 TRIG_IN_MUX_6_HSIOM_IO_INPUT22 = 0x0000064Du, /* peri.tr_io_input[22] */ 723 TRIG_IN_MUX_6_HSIOM_IO_INPUT23 = 0x0000064Eu, /* peri.tr_io_input[23] */ 724 TRIG_IN_MUX_6_HSIOM_IO_INPUT24 = 0x0000064Fu, /* peri.tr_io_input[24] */ 725 TRIG_IN_MUX_6_HSIOM_IO_INPUT25 = 0x00000650u, /* peri.tr_io_input[25] */ 726 TRIG_IN_MUX_6_HSIOM_IO_INPUT26 = 0x00000651u, /* peri.tr_io_input[26] */ 727 TRIG_IN_MUX_6_HSIOM_IO_INPUT27 = 0x00000652u, /* peri.tr_io_input[27] */ 728 TRIG_IN_MUX_6_HSIOM_IO_INPUT28 = 0x00000653u, /* peri.tr_io_input[28] */ 729 TRIG_IN_MUX_6_HSIOM_IO_INPUT29 = 0x00000654u, /* peri.tr_io_input[29] */ 730 TRIG_IN_MUX_6_HSIOM_IO_INPUT30 = 0x00000655u, /* peri.tr_io_input[30] */ 731 TRIG_IN_MUX_6_HSIOM_IO_INPUT31 = 0x00000656u, /* peri.tr_io_input[31] */ 732 TRIG_IN_MUX_6_HSIOM_IO_INPUT32 = 0x00000657u, /* peri.tr_io_input[32] */ 733 TRIG_IN_MUX_6_HSIOM_IO_INPUT33 = 0x00000658u, /* peri.tr_io_input[33] */ 734 TRIG_IN_MUX_6_HSIOM_IO_INPUT34 = 0x00000659u, /* peri.tr_io_input[34] */ 735 TRIG_IN_MUX_6_HSIOM_IO_INPUT35 = 0x0000065Au, /* peri.tr_io_input[35] */ 736 TRIG_IN_MUX_6_HSIOM_IO_INPUT36 = 0x0000065Bu, /* peri.tr_io_input[36] */ 737 TRIG_IN_MUX_6_HSIOM_IO_INPUT37 = 0x0000065Cu, /* peri.tr_io_input[37] */ 738 TRIG_IN_MUX_6_HSIOM_IO_INPUT38 = 0x0000065Du, /* peri.tr_io_input[38] */ 739 TRIG_IN_MUX_6_HSIOM_IO_INPUT39 = 0x0000065Eu, /* peri.tr_io_input[39] */ 740 TRIG_IN_MUX_6_HSIOM_IO_INPUT40 = 0x0000065Fu, /* peri.tr_io_input[40] */ 741 TRIG_IN_MUX_6_HSIOM_IO_INPUT41 = 0x00000660u, /* peri.tr_io_input[41] */ 742 TRIG_IN_MUX_6_HSIOM_IO_INPUT42 = 0x00000661u, /* peri.tr_io_input[42] */ 743 TRIG_IN_MUX_6_HSIOM_IO_INPUT43 = 0x00000662u, /* peri.tr_io_input[43] */ 744 TRIG_IN_MUX_6_HSIOM_IO_INPUT44 = 0x00000663u, /* peri.tr_io_input[44] */ 745 TRIG_IN_MUX_6_HSIOM_IO_INPUT45 = 0x00000664u, /* peri.tr_io_input[45] */ 746 TRIG_IN_MUX_6_HSIOM_IO_INPUT46 = 0x00000665u, /* peri.tr_io_input[46] */ 747 TRIG_IN_MUX_6_HSIOM_IO_INPUT47 = 0x00000666u, /* peri.tr_io_input[47] */ 748 TRIG_IN_MUX_6_CTI_TR_OUT0 = 0x00000667u, /* cpuss.cti_tr_out[0] */ 749 TRIG_IN_MUX_6_CTI_TR_OUT1 = 0x00000668u, /* cpuss.cti_tr_out[1] */ 750 TRIG_IN_MUX_6_FAULT_TR_OUT0 = 0x00000669u, /* cpuss.tr_fault[0] */ 751 TRIG_IN_MUX_6_FAULT_TR_OUT1 = 0x0000066Au, /* cpuss.tr_fault[1] */ 752 TRIG_IN_MUX_6_FAULT_TR_OUT2 = 0x0000066Bu, /* cpuss.tr_fault[2] */ 753 TRIG_IN_MUX_6_FAULT_TR_OUT3 = 0x0000066Cu, /* cpuss.tr_fault[3] */ 754 TRIG_IN_MUX_6_CXPI_TX_TR_OUT0 = 0x0000066Du, /* cxpi[0].tr_tx_req[0] */ 755 TRIG_IN_MUX_6_CXPI_TX_TR_OUT1 = 0x0000066Eu, /* cxpi[0].tr_tx_req[1] */ 756 TRIG_IN_MUX_6_CXPI_RX_TR_OUT0 = 0x0000066Fu, /* cxpi[0].tr_rx_req[0] */ 757 TRIG_IN_MUX_6_CXPI_RX_TR_OUT1 = 0x00000670u /* cxpi[0].tr_rx_req[1] */ 758 } en_trig_input_tcpwm0_32_59_t; 759 760 /* Trigger Input Group 7 - PASS trigger multiplexer */ 761 typedef enum 762 { 763 TRIG_IN_MUX_7_PDMA0_TR_OUT0 = 0x00000701u, /* cpuss.dw0_tr_out[0] */ 764 TRIG_IN_MUX_7_PDMA0_TR_OUT1 = 0x00000702u, /* cpuss.dw0_tr_out[1] */ 765 TRIG_IN_MUX_7_PDMA0_TR_OUT2 = 0x00000703u, /* cpuss.dw0_tr_out[2] */ 766 TRIG_IN_MUX_7_PDMA0_TR_OUT3 = 0x00000704u, /* cpuss.dw0_tr_out[3] */ 767 TRIG_IN_MUX_7_PDMA0_TR_OUT4 = 0x00000705u, /* cpuss.dw0_tr_out[4] */ 768 TRIG_IN_MUX_7_PDMA0_TR_OUT5 = 0x00000706u, /* cpuss.dw0_tr_out[5] */ 769 TRIG_IN_MUX_7_PDMA0_TR_OUT6 = 0x00000707u, /* cpuss.dw0_tr_out[6] */ 770 TRIG_IN_MUX_7_PDMA0_TR_OUT7 = 0x00000708u, /* cpuss.dw0_tr_out[7] */ 771 TRIG_IN_MUX_7_PDMA0_TR_OUT8 = 0x00000709u, /* cpuss.dw0_tr_out[8] */ 772 TRIG_IN_MUX_7_PDMA0_TR_OUT9 = 0x0000070Au, /* cpuss.dw0_tr_out[9] */ 773 TRIG_IN_MUX_7_PDMA0_TR_OUT10 = 0x0000070Bu, /* cpuss.dw0_tr_out[10] */ 774 TRIG_IN_MUX_7_PDMA0_TR_OUT11 = 0x0000070Cu, /* cpuss.dw0_tr_out[11] */ 775 TRIG_IN_MUX_7_PDMA0_TR_OUT12 = 0x0000070Du, /* cpuss.dw0_tr_out[12] */ 776 TRIG_IN_MUX_7_PDMA0_TR_OUT13 = 0x0000070Eu, /* cpuss.dw0_tr_out[13] */ 777 TRIG_IN_MUX_7_PDMA0_TR_OUT14 = 0x0000070Fu, /* cpuss.dw0_tr_out[14] */ 778 TRIG_IN_MUX_7_PDMA0_TR_OUT15 = 0x00000710u, /* cpuss.dw0_tr_out[15] */ 779 TRIG_IN_MUX_7_PDMA0_TR_OUT16 = 0x00000711u, /* cpuss.dw0_tr_out[16] */ 780 TRIG_IN_MUX_7_PDMA0_TR_OUT17 = 0x00000712u, /* cpuss.dw0_tr_out[17] */ 781 TRIG_IN_MUX_7_PDMA0_TR_OUT18 = 0x00000713u, /* cpuss.dw0_tr_out[18] */ 782 TRIG_IN_MUX_7_PDMA0_TR_OUT19 = 0x00000714u, /* cpuss.dw0_tr_out[19] */ 783 TRIG_IN_MUX_7_PDMA0_TR_OUT20 = 0x00000715u, /* cpuss.dw0_tr_out[20] */ 784 TRIG_IN_MUX_7_PDMA0_TR_OUT21 = 0x00000716u, /* cpuss.dw0_tr_out[21] */ 785 TRIG_IN_MUX_7_PDMA0_TR_OUT22 = 0x00000717u, /* cpuss.dw0_tr_out[22] */ 786 TRIG_IN_MUX_7_PDMA0_TR_OUT23 = 0x00000718u, /* cpuss.dw0_tr_out[23] */ 787 TRIG_IN_MUX_7_PDMA0_TR_OUT24 = 0x00000719u, /* cpuss.dw0_tr_out[24] */ 788 TRIG_IN_MUX_7_PDMA0_TR_OUT25 = 0x0000071Au, /* cpuss.dw0_tr_out[25] */ 789 TRIG_IN_MUX_7_PDMA0_TR_OUT26 = 0x0000071Bu, /* cpuss.dw0_tr_out[26] */ 790 TRIG_IN_MUX_7_PDMA0_TR_OUT27 = 0x0000071Cu, /* cpuss.dw0_tr_out[27] */ 791 TRIG_IN_MUX_7_PDMA0_TR_OUT28 = 0x0000071Du, /* cpuss.dw0_tr_out[28] */ 792 TRIG_IN_MUX_7_PDMA0_TR_OUT29 = 0x0000071Eu, /* cpuss.dw0_tr_out[29] */ 793 TRIG_IN_MUX_7_PDMA0_TR_OUT30 = 0x0000071Fu, /* cpuss.dw0_tr_out[30] */ 794 TRIG_IN_MUX_7_PDMA0_TR_OUT31 = 0x00000720u, /* cpuss.dw0_tr_out[31] */ 795 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT00 = 0x00000721u, /* tcpwm[0].tr_out0[0] */ 796 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT01 = 0x00000722u, /* tcpwm[0].tr_out0[1] */ 797 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT02 = 0x00000723u, /* tcpwm[0].tr_out0[2] */ 798 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT03 = 0x00000724u, /* tcpwm[0].tr_out0[3] */ 799 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT04 = 0x00000725u, /* tcpwm[0].tr_out0[4] */ 800 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT05 = 0x00000726u, /* tcpwm[0].tr_out0[5] */ 801 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT06 = 0x00000727u, /* tcpwm[0].tr_out0[6] */ 802 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT07 = 0x00000728u, /* tcpwm[0].tr_out0[7] */ 803 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT08 = 0x00000729u, /* tcpwm[0].tr_out0[8] */ 804 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT09 = 0x0000072Au, /* tcpwm[0].tr_out0[9] */ 805 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT010 = 0x0000072Bu, /* tcpwm[0].tr_out0[10] */ 806 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT011 = 0x0000072Cu, /* tcpwm[0].tr_out0[11] */ 807 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT012 = 0x0000072Du, /* tcpwm[0].tr_out0[12] */ 808 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT013 = 0x0000072Eu, /* tcpwm[0].tr_out0[13] */ 809 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT014 = 0x0000072Fu, /* tcpwm[0].tr_out0[14] */ 810 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT015 = 0x00000730u, /* tcpwm[0].tr_out0[15] */ 811 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT016 = 0x00000731u, /* tcpwm[0].tr_out0[16] */ 812 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT017 = 0x00000732u, /* tcpwm[0].tr_out0[17] */ 813 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT018 = 0x00000733u, /* tcpwm[0].tr_out0[18] */ 814 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT019 = 0x00000734u, /* tcpwm[0].tr_out0[19] */ 815 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT020 = 0x00000735u, /* tcpwm[0].tr_out0[20] */ 816 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT021 = 0x00000736u, /* tcpwm[0].tr_out0[21] */ 817 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT022 = 0x00000737u, /* tcpwm[0].tr_out0[22] */ 818 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT023 = 0x00000738u, /* tcpwm[0].tr_out0[23] */ 819 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT024 = 0x00000739u, /* tcpwm[0].tr_out0[24] */ 820 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT025 = 0x0000073Au, /* tcpwm[0].tr_out0[25] */ 821 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT026 = 0x0000073Bu, /* tcpwm[0].tr_out0[26] */ 822 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT027 = 0x0000073Cu, /* tcpwm[0].tr_out0[27] */ 823 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT028 = 0x0000073Du, /* tcpwm[0].tr_out0[28] */ 824 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT029 = 0x0000073Eu, /* tcpwm[0].tr_out0[29] */ 825 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT030 = 0x0000073Fu, /* tcpwm[0].tr_out0[30] */ 826 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT031 = 0x00000740u, /* tcpwm[0].tr_out0[31] */ 827 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT032 = 0x00000741u, /* tcpwm[0].tr_out0[32] */ 828 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT033 = 0x00000742u, /* tcpwm[0].tr_out0[33] */ 829 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT034 = 0x00000743u, /* tcpwm[0].tr_out0[34] */ 830 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT035 = 0x00000744u, /* tcpwm[0].tr_out0[35] */ 831 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT036 = 0x00000745u, /* tcpwm[0].tr_out0[36] */ 832 TRIG_IN_MUX_7_TCPWM0_16_TR_OUT037 = 0x00000746u, /* tcpwm[0].tr_out0[37] */ 833 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT00 = 0x00000747u, /* tcpwm[0].tr_out0[256] */ 834 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT01 = 0x00000748u, /* tcpwm[0].tr_out0[257] */ 835 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT02 = 0x00000749u, /* tcpwm[0].tr_out0[258] */ 836 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT03 = 0x0000074Au, /* tcpwm[0].tr_out0[259] */ 837 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT04 = 0x0000074Bu, /* tcpwm[0].tr_out0[260] */ 838 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT05 = 0x0000074Cu, /* tcpwm[0].tr_out0[261] */ 839 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT06 = 0x0000074Du, /* tcpwm[0].tr_out0[262] */ 840 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT07 = 0x0000074Eu, /* tcpwm[0].tr_out0[263] */ 841 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT08 = 0x0000074Fu, /* tcpwm[0].tr_out0[264] */ 842 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT09 = 0x00000750u, /* tcpwm[0].tr_out0[265] */ 843 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT010 = 0x00000751u, /* tcpwm[0].tr_out0[266] */ 844 TRIG_IN_MUX_7_TCPWM0_16M_TR_OUT011 = 0x00000752u, /* tcpwm[0].tr_out0[267] */ 845 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT00 = 0x00000753u, /* tcpwm[0].tr_out0[512] */ 846 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT01 = 0x00000754u, /* tcpwm[0].tr_out0[513] */ 847 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT02 = 0x00000755u, /* tcpwm[0].tr_out0[514] */ 848 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT03 = 0x00000756u, /* tcpwm[0].tr_out0[515] */ 849 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT04 = 0x00000757u, /* tcpwm[0].tr_out0[516] */ 850 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT05 = 0x00000758u, /* tcpwm[0].tr_out0[517] */ 851 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT06 = 0x00000759u, /* tcpwm[0].tr_out0[518] */ 852 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT07 = 0x0000075Au, /* tcpwm[0].tr_out0[519] */ 853 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT08 = 0x0000075Bu, /* tcpwm[0].tr_out0[520] */ 854 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT09 = 0x0000075Cu, /* tcpwm[0].tr_out0[521] */ 855 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT010 = 0x0000075Du, /* tcpwm[0].tr_out0[522] */ 856 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT011 = 0x0000075Eu, /* tcpwm[0].tr_out0[523] */ 857 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT012 = 0x0000075Fu, /* tcpwm[0].tr_out0[524] */ 858 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT013 = 0x00000760u, /* tcpwm[0].tr_out0[525] */ 859 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT014 = 0x00000761u, /* tcpwm[0].tr_out0[526] */ 860 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT015 = 0x00000762u, /* tcpwm[0].tr_out0[527] */ 861 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT016 = 0x00000763u, /* tcpwm[0].tr_out0[528] */ 862 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT017 = 0x00000764u, /* tcpwm[0].tr_out0[529] */ 863 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT018 = 0x00000765u, /* tcpwm[0].tr_out0[530] */ 864 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT019 = 0x00000766u, /* tcpwm[0].tr_out0[531] */ 865 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT020 = 0x00000767u, /* tcpwm[0].tr_out0[532] */ 866 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT021 = 0x00000768u, /* tcpwm[0].tr_out0[533] */ 867 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT022 = 0x00000769u, /* tcpwm[0].tr_out0[534] */ 868 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT023 = 0x0000076Au, /* tcpwm[0].tr_out0[535] */ 869 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT024 = 0x0000076Bu, /* tcpwm[0].tr_out0[536] */ 870 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT025 = 0x0000076Cu, /* tcpwm[0].tr_out0[537] */ 871 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT026 = 0x0000076Du, /* tcpwm[0].tr_out0[538] */ 872 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT027 = 0x0000076Eu, /* tcpwm[0].tr_out0[539] */ 873 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT028 = 0x0000076Fu, /* tcpwm[0].tr_out0[540] */ 874 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT029 = 0x00000770u, /* tcpwm[0].tr_out0[541] */ 875 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT030 = 0x00000771u, /* tcpwm[0].tr_out0[542] */ 876 TRIG_IN_MUX_7_TCPWM0_32_TR_OUT031 = 0x00000772u, /* tcpwm[0].tr_out0[543] */ 877 TRIG_IN_MUX_7_HSIOM_IO_INPUT0 = 0x00000773u, /* peri.tr_io_input[0] */ 878 TRIG_IN_MUX_7_HSIOM_IO_INPUT1 = 0x00000774u, /* peri.tr_io_input[1] */ 879 TRIG_IN_MUX_7_HSIOM_IO_INPUT2 = 0x00000775u, /* peri.tr_io_input[2] */ 880 TRIG_IN_MUX_7_HSIOM_IO_INPUT3 = 0x00000776u, /* peri.tr_io_input[3] */ 881 TRIG_IN_MUX_7_HSIOM_IO_INPUT4 = 0x00000777u, /* peri.tr_io_input[4] */ 882 TRIG_IN_MUX_7_HSIOM_IO_INPUT5 = 0x00000778u, /* peri.tr_io_input[5] */ 883 TRIG_IN_MUX_7_HSIOM_IO_INPUT6 = 0x00000779u, /* peri.tr_io_input[6] */ 884 TRIG_IN_MUX_7_HSIOM_IO_INPUT7 = 0x0000077Au, /* peri.tr_io_input[7] */ 885 TRIG_IN_MUX_7_EVTGEN_TR_OUT12 = 0x0000077Bu /* evtgen[0].tr_out[12] */ 886 } en_trig_input_pass_t; 887 888 /* Trigger Input Group 8 - CAN TT Synchronization triggers */ 889 typedef enum 890 { 891 TRIG_IN_MUX_8_CAN0_TT_TR_OUT0 = 0x00000801u, /* canfd[0].tr_tmp_rtp_out[0] */ 892 TRIG_IN_MUX_8_CAN0_TT_TR_OUT1 = 0x00000802u, /* canfd[0].tr_tmp_rtp_out[1] */ 893 TRIG_IN_MUX_8_CAN1_TT_TR_OUT0 = 0x00000803u, /* canfd[1].tr_tmp_rtp_out[0] */ 894 TRIG_IN_MUX_8_CAN1_TT_TR_OUT1 = 0x00000804u /* canfd[1].tr_tmp_rtp_out[1] */ 895 } en_trig_input_can_t; 896 897 /* Trigger Input Group 9 - 2nd level MUX using input from MUX_11/12/13 */ 898 typedef enum 899 { 900 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT0 = 0x00000901u, /* tr_group[10].output[0] */ 901 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT1 = 0x00000902u, /* tr_group[10].output[1] */ 902 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT2 = 0x00000903u, /* tr_group[10].output[2] */ 903 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT3 = 0x00000904u, /* tr_group[10].output[3] */ 904 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT4 = 0x00000905u, /* tr_group[10].output[4] */ 905 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT0 = 0x00000906u, /* tr_group[11].output[0] */ 906 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT1 = 0x00000907u, /* tr_group[11].output[1] */ 907 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT2 = 0x00000908u, /* tr_group[11].output[2] */ 908 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT3 = 0x00000909u, /* tr_group[11].output[3] */ 909 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT4 = 0x0000090Au, /* tr_group[11].output[4] */ 910 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT0 = 0x0000090Bu, /* tr_group[12].output[0] */ 911 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT1 = 0x0000090Cu, /* tr_group[12].output[1] */ 912 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT2 = 0x0000090Du, /* tr_group[12].output[2] */ 913 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT3 = 0x0000090Eu, /* tr_group[12].output[3] */ 914 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT4 = 0x0000090Fu /* tr_group[12].output[4] */ 915 } en_trig_input_debugmain_t; 916 917 /* Trigger Input Group 10 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 918 typedef enum 919 { 920 TRIG_IN_MUX_10_PDMA0_TR_OUT0 = 0x00000A01u, /* cpuss.dw0_tr_out[0] */ 921 TRIG_IN_MUX_10_PDMA0_TR_OUT1 = 0x00000A02u, /* cpuss.dw0_tr_out[1] */ 922 TRIG_IN_MUX_10_PDMA0_TR_OUT2 = 0x00000A03u, /* cpuss.dw0_tr_out[2] */ 923 TRIG_IN_MUX_10_PDMA0_TR_OUT3 = 0x00000A04u, /* cpuss.dw0_tr_out[3] */ 924 TRIG_IN_MUX_10_PDMA0_TR_OUT4 = 0x00000A05u, /* cpuss.dw0_tr_out[4] */ 925 TRIG_IN_MUX_10_PDMA0_TR_OUT5 = 0x00000A06u, /* cpuss.dw0_tr_out[5] */ 926 TRIG_IN_MUX_10_PDMA0_TR_OUT6 = 0x00000A07u, /* cpuss.dw0_tr_out[6] */ 927 TRIG_IN_MUX_10_PDMA0_TR_OUT7 = 0x00000A08u, /* cpuss.dw0_tr_out[7] */ 928 TRIG_IN_MUX_10_PDMA0_TR_OUT8 = 0x00000A09u, /* cpuss.dw0_tr_out[8] */ 929 TRIG_IN_MUX_10_PDMA0_TR_OUT9 = 0x00000A0Au, /* cpuss.dw0_tr_out[9] */ 930 TRIG_IN_MUX_10_PDMA0_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw0_tr_out[10] */ 931 TRIG_IN_MUX_10_PDMA0_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw0_tr_out[11] */ 932 TRIG_IN_MUX_10_PDMA0_TR_OUT12 = 0x00000A0Du, /* cpuss.dw0_tr_out[12] */ 933 TRIG_IN_MUX_10_PDMA0_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw0_tr_out[13] */ 934 TRIG_IN_MUX_10_PDMA0_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw0_tr_out[14] */ 935 TRIG_IN_MUX_10_PDMA0_TR_OUT15 = 0x00000A10u, /* cpuss.dw0_tr_out[15] */ 936 TRIG_IN_MUX_10_PDMA0_TR_OUT16 = 0x00000A11u, /* cpuss.dw0_tr_out[16] */ 937 TRIG_IN_MUX_10_PDMA0_TR_OUT17 = 0x00000A12u, /* cpuss.dw0_tr_out[17] */ 938 TRIG_IN_MUX_10_PDMA0_TR_OUT18 = 0x00000A13u, /* cpuss.dw0_tr_out[18] */ 939 TRIG_IN_MUX_10_PDMA0_TR_OUT19 = 0x00000A14u, /* cpuss.dw0_tr_out[19] */ 940 TRIG_IN_MUX_10_PDMA0_TR_OUT20 = 0x00000A15u, /* cpuss.dw0_tr_out[20] */ 941 TRIG_IN_MUX_10_PDMA0_TR_OUT21 = 0x00000A16u, /* cpuss.dw0_tr_out[21] */ 942 TRIG_IN_MUX_10_PDMA0_TR_OUT22 = 0x00000A17u, /* cpuss.dw0_tr_out[22] */ 943 TRIG_IN_MUX_10_PDMA0_TR_OUT23 = 0x00000A18u, /* cpuss.dw0_tr_out[23] */ 944 TRIG_IN_MUX_10_PDMA0_TR_OUT24 = 0x00000A19u, /* cpuss.dw0_tr_out[24] */ 945 TRIG_IN_MUX_10_PDMA0_TR_OUT25 = 0x00000A1Au, /* cpuss.dw0_tr_out[25] */ 946 TRIG_IN_MUX_10_PDMA0_TR_OUT26 = 0x00000A1Bu, /* cpuss.dw0_tr_out[26] */ 947 TRIG_IN_MUX_10_PDMA0_TR_OUT27 = 0x00000A1Cu, /* cpuss.dw0_tr_out[27] */ 948 TRIG_IN_MUX_10_PDMA0_TR_OUT28 = 0x00000A1Du, /* cpuss.dw0_tr_out[28] */ 949 TRIG_IN_MUX_10_PDMA0_TR_OUT29 = 0x00000A1Eu, /* cpuss.dw0_tr_out[29] */ 950 TRIG_IN_MUX_10_PDMA0_TR_OUT30 = 0x00000A1Fu, /* cpuss.dw0_tr_out[30] */ 951 TRIG_IN_MUX_10_PDMA0_TR_OUT31 = 0x00000A20u, /* cpuss.dw0_tr_out[31] */ 952 TRIG_IN_MUX_10_PDMA0_TR_OUT32 = 0x00000A21u, /* cpuss.dw0_tr_out[32] */ 953 TRIG_IN_MUX_10_PDMA0_TR_OUT33 = 0x00000A22u, /* cpuss.dw0_tr_out[33] */ 954 TRIG_IN_MUX_10_PDMA0_TR_OUT34 = 0x00000A23u, /* cpuss.dw0_tr_out[34] */ 955 TRIG_IN_MUX_10_PDMA0_TR_OUT35 = 0x00000A24u, /* cpuss.dw0_tr_out[35] */ 956 TRIG_IN_MUX_10_PDMA0_TR_OUT36 = 0x00000A25u, /* cpuss.dw0_tr_out[36] */ 957 TRIG_IN_MUX_10_PDMA0_TR_OUT37 = 0x00000A26u, /* cpuss.dw0_tr_out[37] */ 958 TRIG_IN_MUX_10_PDMA0_TR_OUT38 = 0x00000A27u, /* cpuss.dw0_tr_out[38] */ 959 TRIG_IN_MUX_10_PDMA0_TR_OUT39 = 0x00000A28u, /* cpuss.dw0_tr_out[39] */ 960 TRIG_IN_MUX_10_PDMA0_TR_OUT40 = 0x00000A29u, /* cpuss.dw0_tr_out[40] */ 961 TRIG_IN_MUX_10_PDMA0_TR_OUT41 = 0x00000A2Au, /* cpuss.dw0_tr_out[41] */ 962 TRIG_IN_MUX_10_PDMA0_TR_OUT42 = 0x00000A2Bu, /* cpuss.dw0_tr_out[42] */ 963 TRIG_IN_MUX_10_PDMA0_TR_OUT43 = 0x00000A2Cu, /* cpuss.dw0_tr_out[43] */ 964 TRIG_IN_MUX_10_PDMA0_TR_OUT44 = 0x00000A2Du, /* cpuss.dw0_tr_out[44] */ 965 TRIG_IN_MUX_10_PDMA0_TR_OUT45 = 0x00000A2Eu, /* cpuss.dw0_tr_out[45] */ 966 TRIG_IN_MUX_10_PDMA0_TR_OUT46 = 0x00000A2Fu, /* cpuss.dw0_tr_out[46] */ 967 TRIG_IN_MUX_10_PDMA0_TR_OUT47 = 0x00000A30u, /* cpuss.dw0_tr_out[47] */ 968 TRIG_IN_MUX_10_PDMA0_TR_OUT48 = 0x00000A31u, /* cpuss.dw0_tr_out[48] */ 969 TRIG_IN_MUX_10_PDMA0_TR_OUT49 = 0x00000A32u, /* cpuss.dw0_tr_out[49] */ 970 TRIG_IN_MUX_10_PDMA0_TR_OUT50 = 0x00000A33u, /* cpuss.dw0_tr_out[50] */ 971 TRIG_IN_MUX_10_PDMA0_TR_OUT51 = 0x00000A34u, /* cpuss.dw0_tr_out[51] */ 972 TRIG_IN_MUX_10_PDMA0_TR_OUT52 = 0x00000A35u, /* cpuss.dw0_tr_out[52] */ 973 TRIG_IN_MUX_10_PDMA0_TR_OUT53 = 0x00000A36u, /* cpuss.dw0_tr_out[53] */ 974 TRIG_IN_MUX_10_PDMA0_TR_OUT54 = 0x00000A37u, /* cpuss.dw0_tr_out[54] */ 975 TRIG_IN_MUX_10_PDMA0_TR_OUT55 = 0x00000A38u, /* cpuss.dw0_tr_out[55] */ 976 TRIG_IN_MUX_10_PDMA0_TR_OUT56 = 0x00000A39u, /* cpuss.dw0_tr_out[56] */ 977 TRIG_IN_MUX_10_PDMA0_TR_OUT57 = 0x00000A3Au, /* cpuss.dw0_tr_out[57] */ 978 TRIG_IN_MUX_10_PDMA0_TR_OUT58 = 0x00000A3Bu, /* cpuss.dw0_tr_out[58] */ 979 TRIG_IN_MUX_10_PDMA0_TR_OUT59 = 0x00000A3Cu, /* cpuss.dw0_tr_out[59] */ 980 TRIG_IN_MUX_10_PDMA0_TR_OUT60 = 0x00000A3Du, /* cpuss.dw0_tr_out[60] */ 981 TRIG_IN_MUX_10_PDMA0_TR_OUT61 = 0x00000A3Eu, /* cpuss.dw0_tr_out[61] */ 982 TRIG_IN_MUX_10_PDMA0_TR_OUT62 = 0x00000A3Fu, /* cpuss.dw0_tr_out[62] */ 983 TRIG_IN_MUX_10_PDMA0_TR_OUT63 = 0x00000A40u, /* cpuss.dw0_tr_out[63] */ 984 TRIG_IN_MUX_10_PDMA0_TR_OUT64 = 0x00000A41u, /* cpuss.dw0_tr_out[64] */ 985 TRIG_IN_MUX_10_PDMA0_TR_OUT65 = 0x00000A42u, /* cpuss.dw0_tr_out[65] */ 986 TRIG_IN_MUX_10_PDMA0_TR_OUT66 = 0x00000A43u, /* cpuss.dw0_tr_out[66] */ 987 TRIG_IN_MUX_10_PDMA0_TR_OUT67 = 0x00000A44u, /* cpuss.dw0_tr_out[67] */ 988 TRIG_IN_MUX_10_PDMA0_TR_OUT68 = 0x00000A45u, /* cpuss.dw0_tr_out[68] */ 989 TRIG_IN_MUX_10_PDMA0_TR_OUT69 = 0x00000A46u, /* cpuss.dw0_tr_out[69] */ 990 TRIG_IN_MUX_10_PDMA0_TR_OUT70 = 0x00000A47u, /* cpuss.dw0_tr_out[70] */ 991 TRIG_IN_MUX_10_PDMA0_TR_OUT71 = 0x00000A48u, /* cpuss.dw0_tr_out[71] */ 992 TRIG_IN_MUX_10_PDMA0_TR_OUT72 = 0x00000A49u, /* cpuss.dw0_tr_out[72] */ 993 TRIG_IN_MUX_10_PDMA0_TR_OUT73 = 0x00000A4Au, /* cpuss.dw0_tr_out[73] */ 994 TRIG_IN_MUX_10_PDMA0_TR_OUT74 = 0x00000A4Bu, /* cpuss.dw0_tr_out[74] */ 995 TRIG_IN_MUX_10_PDMA0_TR_OUT75 = 0x00000A4Cu, /* cpuss.dw0_tr_out[75] */ 996 TRIG_IN_MUX_10_SCB_TX_TR_OUT0 = 0x00000A4Du, /* scb[0].tr_tx_req */ 997 TRIG_IN_MUX_10_SCB_TX_TR_OUT1 = 0x00000A4Eu, /* scb[1].tr_tx_req */ 998 TRIG_IN_MUX_10_SCB_TX_TR_OUT2 = 0x00000A4Fu, /* scb[2].tr_tx_req */ 999 TRIG_IN_MUX_10_SCB_TX_TR_OUT3 = 0x00000A50u, /* scb[3].tr_tx_req */ 1000 TRIG_IN_MUX_10_SCB_TX_TR_OUT4 = 0x00000A51u, /* scb[4].tr_tx_req */ 1001 TRIG_IN_MUX_10_SCB_TX_TR_OUT5 = 0x00000A52u, /* scb[5].tr_tx_req */ 1002 TRIG_IN_MUX_10_SCB_TX_TR_OUT6 = 0x00000A53u, /* scb[6].tr_tx_req */ 1003 TRIG_IN_MUX_10_SCB_TX_TR_OUT7 = 0x00000A54u, /* scb[7].tr_tx_req */ 1004 TRIG_IN_MUX_10_SCB_TX_TR_OUT8 = 0x00000A55u, /* scb[8].tr_tx_req */ 1005 TRIG_IN_MUX_10_SCB_TX_TR_OUT9 = 0x00000A56u, /* scb[9].tr_tx_req */ 1006 TRIG_IN_MUX_10_SCB_TX_TR_OUT10 = 0x00000A57u, /* scb[10].tr_tx_req */ 1007 TRIG_IN_MUX_10_SCB_TX_TR_OUT11 = 0x00000A58u, /* scb[11].tr_tx_req */ 1008 TRIG_IN_MUX_10_SCB_RX_TR_OUT0 = 0x00000A59u, /* scb[0].tr_rx_req */ 1009 TRIG_IN_MUX_10_SCB_RX_TR_OUT1 = 0x00000A5Au, /* scb[1].tr_rx_req */ 1010 TRIG_IN_MUX_10_SCB_RX_TR_OUT2 = 0x00000A5Bu, /* scb[2].tr_rx_req */ 1011 TRIG_IN_MUX_10_SCB_RX_TR_OUT3 = 0x00000A5Cu, /* scb[3].tr_rx_req */ 1012 TRIG_IN_MUX_10_SCB_RX_TR_OUT4 = 0x00000A5Du, /* scb[4].tr_rx_req */ 1013 TRIG_IN_MUX_10_SCB_RX_TR_OUT5 = 0x00000A5Eu, /* scb[5].tr_rx_req */ 1014 TRIG_IN_MUX_10_SCB_RX_TR_OUT6 = 0x00000A5Fu, /* scb[6].tr_rx_req */ 1015 TRIG_IN_MUX_10_SCB_RX_TR_OUT7 = 0x00000A60u, /* scb[7].tr_rx_req */ 1016 TRIG_IN_MUX_10_SCB_RX_TR_OUT8 = 0x00000A61u, /* scb[8].tr_rx_req */ 1017 TRIG_IN_MUX_10_SCB_RX_TR_OUT9 = 0x00000A62u, /* scb[9].tr_rx_req */ 1018 TRIG_IN_MUX_10_SCB_RX_TR_OUT10 = 0x00000A63u, /* scb[10].tr_rx_req */ 1019 TRIG_IN_MUX_10_SCB_RX_TR_OUT11 = 0x00000A64u, /* scb[11].tr_rx_req */ 1020 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT0 = 0x00000A65u, /* scb[0].tr_i2c_scl_filtered */ 1021 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT1 = 0x00000A66u, /* scb[1].tr_i2c_scl_filtered */ 1022 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT2 = 0x00000A67u, /* scb[2].tr_i2c_scl_filtered */ 1023 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT3 = 0x00000A68u, /* scb[3].tr_i2c_scl_filtered */ 1024 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT4 = 0x00000A69u, /* scb[4].tr_i2c_scl_filtered */ 1025 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT5 = 0x00000A6Au, /* scb[5].tr_i2c_scl_filtered */ 1026 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT6 = 0x00000A6Bu, /* scb[6].tr_i2c_scl_filtered */ 1027 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT7 = 0x00000A6Cu, /* scb[7].tr_i2c_scl_filtered */ 1028 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT8 = 0x00000A6Du, /* scb[8].tr_i2c_scl_filtered */ 1029 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT9 = 0x00000A6Eu, /* scb[9].tr_i2c_scl_filtered */ 1030 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT10 = 0x00000A6Fu, /* scb[10].tr_i2c_scl_filtered */ 1031 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT11 = 0x00000A70u, /* scb[11].tr_i2c_scl_filtered */ 1032 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT0 = 0x00000A71u, /* canfd[0].tr_dbg_dma_req[0] */ 1033 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT1 = 0x00000A72u, /* canfd[0].tr_dbg_dma_req[1] */ 1034 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT0 = 0x00000A73u, /* canfd[0].tr_fifo0[0] */ 1035 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT1 = 0x00000A74u, /* canfd[0].tr_fifo0[1] */ 1036 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT0 = 0x00000A75u, /* canfd[0].tr_fifo1[0] */ 1037 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT1 = 0x00000A76u, /* canfd[0].tr_fifo1[1] */ 1038 TRIG_IN_MUX_10_CAN0_TT_TR_OUT0 = 0x00000A77u, /* canfd[0].tr_tmp_rtp_out[0] */ 1039 TRIG_IN_MUX_10_CAN0_TT_TR_OUT1 = 0x00000A78u, /* canfd[0].tr_tmp_rtp_out[1] */ 1040 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT0 = 0x00000A79u, /* canfd[1].tr_dbg_dma_req[0] */ 1041 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT1 = 0x00000A7Au, /* canfd[1].tr_dbg_dma_req[1] */ 1042 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT0 = 0x00000A7Bu, /* canfd[1].tr_fifo0[0] */ 1043 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT1 = 0x00000A7Cu, /* canfd[1].tr_fifo0[1] */ 1044 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT0 = 0x00000A7Du, /* canfd[1].tr_fifo1[0] */ 1045 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT1 = 0x00000A7Eu, /* canfd[1].tr_fifo1[1] */ 1046 TRIG_IN_MUX_10_CAN1_TT_TR_OUT0 = 0x00000A7Fu, /* canfd[1].tr_tmp_rtp_out[0] */ 1047 TRIG_IN_MUX_10_CAN1_TT_TR_OUT1 = 0x00000A80u, /* canfd[1].tr_tmp_rtp_out[1] */ 1048 TRIG_IN_MUX_10_CTI_TR_OUT0 = 0x00000A81u, /* cpuss.cti_tr_out[0] */ 1049 TRIG_IN_MUX_10_CTI_TR_OUT1 = 0x00000A82u, /* cpuss.cti_tr_out[1] */ 1050 TRIG_IN_MUX_10_FAULT_TR_OU0 = 0x00000A83u, /* cpuss.tr_fault[0] */ 1051 TRIG_IN_MUX_10_FAULT_TR_OU1 = 0x00000A84u, /* cpuss.tr_fault[1] */ 1052 TRIG_IN_MUX_10_FAULT_TR_OU2 = 0x00000A85u, /* cpuss.tr_fault[2] */ 1053 TRIG_IN_MUX_10_FAULT_TR_OU3 = 0x00000A86u, /* cpuss.tr_fault[3] */ 1054 TRIG_IN_MUX_10_EVTGEN_TR_OUT0 = 0x00000A87u, /* evtgen[0].tr_out[0] */ 1055 TRIG_IN_MUX_10_EVTGEN_TR_OUT1 = 0x00000A88u, /* evtgen[0].tr_out[1] */ 1056 TRIG_IN_MUX_10_EVTGEN_TR_OUT2 = 0x00000A89u, /* evtgen[0].tr_out[2] */ 1057 TRIG_IN_MUX_10_EVTGEN_TR_OUT3 = 0x00000A8Au, /* evtgen[0].tr_out[3] */ 1058 TRIG_IN_MUX_10_EVTGEN_TR_OUT4 = 0x00000A8Bu, /* evtgen[0].tr_out[4] */ 1059 TRIG_IN_MUX_10_EVTGEN_TR_OUT5 = 0x00000A8Cu, /* evtgen[0].tr_out[5] */ 1060 TRIG_IN_MUX_10_EVTGEN_TR_OUT6 = 0x00000A8Du, /* evtgen[0].tr_out[6] */ 1061 TRIG_IN_MUX_10_EVTGEN_TR_OUT7 = 0x00000A8Eu, /* evtgen[0].tr_out[7] */ 1062 TRIG_IN_MUX_10_EVTGEN_TR_OUT8 = 0x00000A8Fu, /* evtgen[0].tr_out[8] */ 1063 TRIG_IN_MUX_10_EVTGEN_TR_OUT9 = 0x00000A90u, /* evtgen[0].tr_out[9] */ 1064 TRIG_IN_MUX_10_EVTGEN_TR_OUT10 = 0x00000A91u, /* evtgen[0].tr_out[10] */ 1065 TRIG_IN_MUX_10_EVTGEN_TR_OUT11 = 0x00000A92u, /* evtgen[0].tr_out[11] */ 1066 TRIG_IN_MUX_10_EVTGEN_TR_OUT12 = 0x00000A93u, /* evtgen[0].tr_out[12] */ 1067 TRIG_IN_MUX_10_EVTGEN_TR_OUT13 = 0x00000A94u, /* evtgen[0].tr_out[13] */ 1068 TRIG_IN_MUX_10_EVTGEN_TR_OUT14 = 0x00000A95u, /* evtgen[0].tr_out[14] */ 1069 TRIG_IN_MUX_10_EVTGEN_TR_OUT15 = 0x00000A96u /* evtgen[0].tr_out[15] */ 1070 } en_trig_input_debugreducation1_t; 1071 1072 /* Trigger Input Group 11 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1073 typedef enum 1074 { 1075 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT00 = 0x00000B01u, /* tcpwm[0].tr_out0[512] */ 1076 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT01 = 0x00000B02u, /* tcpwm[0].tr_out0[513] */ 1077 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT02 = 0x00000B03u, /* tcpwm[0].tr_out0[514] */ 1078 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT03 = 0x00000B04u, /* tcpwm[0].tr_out0[515] */ 1079 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT04 = 0x00000B05u, /* tcpwm[0].tr_out0[516] */ 1080 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT05 = 0x00000B06u, /* tcpwm[0].tr_out0[517] */ 1081 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT06 = 0x00000B07u, /* tcpwm[0].tr_out0[518] */ 1082 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT07 = 0x00000B08u, /* tcpwm[0].tr_out0[519] */ 1083 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT08 = 0x00000B09u, /* tcpwm[0].tr_out0[520] */ 1084 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT09 = 0x00000B0Au, /* tcpwm[0].tr_out0[521] */ 1085 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT010 = 0x00000B0Bu, /* tcpwm[0].tr_out0[522] */ 1086 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT011 = 0x00000B0Cu, /* tcpwm[0].tr_out0[523] */ 1087 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT012 = 0x00000B0Du, /* tcpwm[0].tr_out0[524] */ 1088 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT013 = 0x00000B0Eu, /* tcpwm[0].tr_out0[525] */ 1089 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT014 = 0x00000B0Fu, /* tcpwm[0].tr_out0[526] */ 1090 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT015 = 0x00000B10u, /* tcpwm[0].tr_out0[527] */ 1091 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT016 = 0x00000B11u, /* tcpwm[0].tr_out0[528] */ 1092 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT017 = 0x00000B12u, /* tcpwm[0].tr_out0[529] */ 1093 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT018 = 0x00000B13u, /* tcpwm[0].tr_out0[530] */ 1094 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT019 = 0x00000B14u, /* tcpwm[0].tr_out0[531] */ 1095 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT020 = 0x00000B15u, /* tcpwm[0].tr_out0[532] */ 1096 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT021 = 0x00000B16u, /* tcpwm[0].tr_out0[533] */ 1097 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT022 = 0x00000B17u, /* tcpwm[0].tr_out0[534] */ 1098 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT023 = 0x00000B18u, /* tcpwm[0].tr_out0[535] */ 1099 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT024 = 0x00000B19u, /* tcpwm[0].tr_out0[536] */ 1100 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT025 = 0x00000B1Au, /* tcpwm[0].tr_out0[537] */ 1101 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT026 = 0x00000B1Bu, /* tcpwm[0].tr_out0[538] */ 1102 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT027 = 0x00000B1Cu, /* tcpwm[0].tr_out0[539] */ 1103 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT028 = 0x00000B1Du, /* tcpwm[0].tr_out0[540] */ 1104 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT029 = 0x00000B1Eu, /* tcpwm[0].tr_out0[541] */ 1105 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT030 = 0x00000B1Fu, /* tcpwm[0].tr_out0[542] */ 1106 TRIG_IN_MUX_11_TCPWM0_32_TR_OUT031 = 0x00000B20u, /* tcpwm[0].tr_out0[543] */ 1107 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT00 = 0x00000B21u, /* tcpwm[0].tr_out0[256] */ 1108 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT01 = 0x00000B22u, /* tcpwm[0].tr_out0[257] */ 1109 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT02 = 0x00000B23u, /* tcpwm[0].tr_out0[258] */ 1110 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT03 = 0x00000B24u, /* tcpwm[0].tr_out0[259] */ 1111 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT04 = 0x00000B25u, /* tcpwm[0].tr_out0[260] */ 1112 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT05 = 0x00000B26u, /* tcpwm[0].tr_out0[261] */ 1113 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT06 = 0x00000B27u, /* tcpwm[0].tr_out0[262] */ 1114 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT07 = 0x00000B28u, /* tcpwm[0].tr_out0[263] */ 1115 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT08 = 0x00000B29u, /* tcpwm[0].tr_out0[264] */ 1116 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT09 = 0x00000B2Au, /* tcpwm[0].tr_out0[265] */ 1117 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT010 = 0x00000B2Bu, /* tcpwm[0].tr_out0[266] */ 1118 TRIG_IN_MUX_11_TCPWM0_16M_TR_OUT011 = 0x00000B2Cu, /* tcpwm[0].tr_out0[267] */ 1119 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT00 = 0x00000B2Du, /* tcpwm[0].tr_out0[0] */ 1120 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT01 = 0x00000B2Eu, /* tcpwm[0].tr_out0[1] */ 1121 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT02 = 0x00000B2Fu, /* tcpwm[0].tr_out0[2] */ 1122 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT03 = 0x00000B30u, /* tcpwm[0].tr_out0[3] */ 1123 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT04 = 0x00000B31u, /* tcpwm[0].tr_out0[4] */ 1124 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT05 = 0x00000B32u, /* tcpwm[0].tr_out0[5] */ 1125 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT06 = 0x00000B33u, /* tcpwm[0].tr_out0[6] */ 1126 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT07 = 0x00000B34u, /* tcpwm[0].tr_out0[7] */ 1127 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT08 = 0x00000B35u, /* tcpwm[0].tr_out0[8] */ 1128 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT09 = 0x00000B36u, /* tcpwm[0].tr_out0[9] */ 1129 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT010 = 0x00000B37u, /* tcpwm[0].tr_out0[10] */ 1130 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT011 = 0x00000B38u, /* tcpwm[0].tr_out0[11] */ 1131 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT012 = 0x00000B39u, /* tcpwm[0].tr_out0[12] */ 1132 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT013 = 0x00000B3Au, /* tcpwm[0].tr_out0[13] */ 1133 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT014 = 0x00000B3Bu, /* tcpwm[0].tr_out0[14] */ 1134 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT015 = 0x00000B3Cu, /* tcpwm[0].tr_out0[15] */ 1135 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT016 = 0x00000B3Du, /* tcpwm[0].tr_out0[16] */ 1136 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT017 = 0x00000B3Eu, /* tcpwm[0].tr_out0[17] */ 1137 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT018 = 0x00000B3Fu, /* tcpwm[0].tr_out0[18] */ 1138 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT019 = 0x00000B40u, /* tcpwm[0].tr_out0[19] */ 1139 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT020 = 0x00000B41u, /* tcpwm[0].tr_out0[20] */ 1140 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT021 = 0x00000B42u, /* tcpwm[0].tr_out0[21] */ 1141 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT022 = 0x00000B43u, /* tcpwm[0].tr_out0[22] */ 1142 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT023 = 0x00000B44u, /* tcpwm[0].tr_out0[23] */ 1143 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT024 = 0x00000B45u, /* tcpwm[0].tr_out0[24] */ 1144 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT025 = 0x00000B46u, /* tcpwm[0].tr_out0[25] */ 1145 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT026 = 0x00000B47u, /* tcpwm[0].tr_out0[26] */ 1146 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT027 = 0x00000B48u, /* tcpwm[0].tr_out0[27] */ 1147 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT028 = 0x00000B49u, /* tcpwm[0].tr_out0[28] */ 1148 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT029 = 0x00000B4Au, /* tcpwm[0].tr_out0[29] */ 1149 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT030 = 0x00000B4Bu, /* tcpwm[0].tr_out0[30] */ 1150 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT031 = 0x00000B4Cu, /* tcpwm[0].tr_out0[31] */ 1151 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT032 = 0x00000B4Du, /* tcpwm[0].tr_out0[32] */ 1152 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT033 = 0x00000B4Eu, /* tcpwm[0].tr_out0[33] */ 1153 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT034 = 0x00000B4Fu, /* tcpwm[0].tr_out0[34] */ 1154 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT035 = 0x00000B50u, /* tcpwm[0].tr_out0[35] */ 1155 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT036 = 0x00000B51u, /* tcpwm[0].tr_out0[36] */ 1156 TRIG_IN_MUX_11_TCPWM0_16_TR_OUT037 = 0x00000B52u, /* tcpwm[0].tr_out0[37] */ 1157 TRIG_IN_MUX_11_SMIF0_TX_TR_OUT = 0x00000B53u, /* smif[0].smif0_tr_tx_req */ 1158 TRIG_IN_MUX_11_SMIF0_RX_TR_OUT = 0x00000B54u, /* smif[0].smif0_tr_rx_req */ 1159 TRIG_IN_MUX_11_SMIF1_TX_TR_OUT = 0x00000B55u, /* smif[0].smif1_tr_tx_req */ 1160 TRIG_IN_MUX_11_SMIF1_RX_TR_OUT = 0x00000B56u, /* smif[0].smif1_tr_rx_req */ 1161 TRIG_IN_MUX_11_AXIDMA_TR_OUT0 = 0x00000B57u, /* axi_dmac[0].tr_out[0] */ 1162 TRIG_IN_MUX_11_AXIDMA_TR_OUT1 = 0x00000B58u, /* axi_dmac[0].tr_out[1] */ 1163 TRIG_IN_MUX_11_AXIDMA_TR_OUT2 = 0x00000B59u, /* axi_dmac[0].tr_out[2] */ 1164 TRIG_IN_MUX_11_AXIDMA_TR_OUT3 = 0x00000B5Au, /* axi_dmac[0].tr_out[3] */ 1165 TRIG_IN_MUX_11_TDM0_TX_TR_OUT0 = 0x00000B5Fu, /* tdm[0].tr_tx_req[0] */ 1166 TRIG_IN_MUX_11_TDM0_TX_TR_OUT1 = 0x00000B60u, /* tdm[0].tr_tx_req[1] */ 1167 TRIG_IN_MUX_11_TDM0_TX_TR_OUT2 = 0x00000B61u, /* tdm[0].tr_tx_req[2] */ 1168 TRIG_IN_MUX_11_TDM0_TX_TR_OUT3 = 0x00000B62u, /* tdm[0].tr_tx_req[3] */ 1169 TRIG_IN_MUX_11_TDM0_RX_TR_OUT0 = 0x00000B63u, /* tdm[0].tr_rx_req[0] */ 1170 TRIG_IN_MUX_11_TDM0_RX_TR_OUT1 = 0x00000B64u, /* tdm[0].tr_rx_req[1] */ 1171 TRIG_IN_MUX_11_TDM0_RX_TR_OUT2 = 0x00000B65u, /* tdm[0].tr_rx_req[2] */ 1172 TRIG_IN_MUX_11_TDM0_RX_TR_OUT3 = 0x00000B66u, /* tdm[0].tr_rx_req[3] */ 1173 TRIG_IN_MUX_11_SG0_TR_COMPLETE0 = 0x00000B67u, /* sg[0].tr_complete[0] */ 1174 TRIG_IN_MUX_11_SG0_TR_COMPLETE1 = 0x00000B68u, /* sg[0].tr_complete[1] */ 1175 TRIG_IN_MUX_11_SG0_TR_COMPLETE2 = 0x00000B69u, /* sg[0].tr_complete[2] */ 1176 TRIG_IN_MUX_11_SG0_TR_COMPLETE3 = 0x00000B6Au, /* sg[0].tr_complete[3] */ 1177 TRIG_IN_MUX_11_SG0_TR_COMPLETE4 = 0x00000B6Bu, /* sg[0].tr_complete[4] */ 1178 TRIG_IN_MUX_11_PWM0_TX_TR_OUT0 = 0x00000B6Cu, /* pwm[0].tr_tx_req[0] */ 1179 TRIG_IN_MUX_11_PWM0_TX_TR_OUT1 = 0x00000B6Du, /* pwm[0].tr_tx_req[1] */ 1180 TRIG_IN_MUX_11_AUDIODAC0_TX_TR_OUT = 0x00000B6Eu, /* dac[0].tr_tx_req */ 1181 TRIG_IN_MUX_11_MIXER0_TR_SRC_REQ_OUT0 = 0x00000B6Fu, /* mixer[0].tr_src_req[0] */ 1182 TRIG_IN_MUX_11_MIXER0_TR_SRC_REQ_OUT1 = 0x00000B70u, /* mixer[0].tr_src_req[1] */ 1183 TRIG_IN_MUX_11_MIXER0_TR_SRC_REQ_OUT2 = 0x00000B71u, /* mixer[0].tr_src_req[2] */ 1184 TRIG_IN_MUX_11_MIXER0_TR_SRC_REQ_OUT3 = 0x00000B72u, /* mixer[0].tr_src_req[3] */ 1185 TRIG_IN_MUX_11_MIXER0_TR_SRC_REQ_OUT4 = 0x00000B73u, /* mixer[0].tr_src_req[4] */ 1186 TRIG_IN_MUX_11_MIXER0_TR_DST_REQ_OUT = 0x00000B74u, /* mixer[0].tr_dst_req */ 1187 TRIG_IN_MUX_11_MIXER1_TR_SRC_REQ_OUT0 = 0x00000B75u, /* mixer[1].tr_src_req[0] */ 1188 TRIG_IN_MUX_11_MIXER1_TR_SRC_REQ_OUT1 = 0x00000B76u, /* mixer[1].tr_src_req[1] */ 1189 TRIG_IN_MUX_11_MIXER1_TR_SRC_REQ_OUT2 = 0x00000B77u, /* mixer[1].tr_src_req[2] */ 1190 TRIG_IN_MUX_11_MIXER1_TR_SRC_REQ_OUT3 = 0x00000B78u, /* mixer[1].tr_src_req[3] */ 1191 TRIG_IN_MUX_11_MIXER1_TR_SRC_REQ_OUT4 = 0x00000B79u, /* mixer[1].tr_src_req[4] */ 1192 TRIG_IN_MUX_11_MIXER1_TR_DST_REQ_OUT = 0x00000B7Au, /* mixer[1].tr_dst_req */ 1193 TRIG_IN_MUX_11_HSIOM_IO_INPUT0 = 0x00000B7Bu, /* peri.tr_io_input[0] */ 1194 TRIG_IN_MUX_11_HSIOM_IO_INPUT1 = 0x00000B7Cu, /* peri.tr_io_input[1] */ 1195 TRIG_IN_MUX_11_HSIOM_IO_INPUT2 = 0x00000B7Du, /* peri.tr_io_input[2] */ 1196 TRIG_IN_MUX_11_HSIOM_IO_INPUT3 = 0x00000B7Eu, /* peri.tr_io_input[3] */ 1197 TRIG_IN_MUX_11_HSIOM_IO_INPUT4 = 0x00000B7Fu, /* peri.tr_io_input[4] */ 1198 TRIG_IN_MUX_11_HSIOM_IO_INPUT5 = 0x00000B80u, /* peri.tr_io_input[5] */ 1199 TRIG_IN_MUX_11_HSIOM_IO_INPUT6 = 0x00000B81u, /* peri.tr_io_input[6] */ 1200 TRIG_IN_MUX_11_HSIOM_IO_INPUT7 = 0x00000B82u, /* peri.tr_io_input[7] */ 1201 TRIG_IN_MUX_11_HSIOM_IO_INPUT8 = 0x00000B83u, /* peri.tr_io_input[8] */ 1202 TRIG_IN_MUX_11_HSIOM_IO_INPUT9 = 0x00000B84u, /* peri.tr_io_input[9] */ 1203 TRIG_IN_MUX_11_HSIOM_IO_INPUT10 = 0x00000B85u, /* peri.tr_io_input[10] */ 1204 TRIG_IN_MUX_11_HSIOM_IO_INPUT11 = 0x00000B86u, /* peri.tr_io_input[11] */ 1205 TRIG_IN_MUX_11_HSIOM_IO_INPUT12 = 0x00000B87u, /* peri.tr_io_input[12] */ 1206 TRIG_IN_MUX_11_HSIOM_IO_INPUT13 = 0x00000B88u, /* peri.tr_io_input[13] */ 1207 TRIG_IN_MUX_11_HSIOM_IO_INPUT14 = 0x00000B89u, /* peri.tr_io_input[14] */ 1208 TRIG_IN_MUX_11_HSIOM_IO_INPUT15 = 0x00000B8Au, /* peri.tr_io_input[15] */ 1209 TRIG_IN_MUX_11_HSIOM_IO_INPUT16 = 0x00000B8Bu, /* peri.tr_io_input[16] */ 1210 TRIG_IN_MUX_11_HSIOM_IO_INPUT17 = 0x00000B8Cu, /* peri.tr_io_input[17] */ 1211 TRIG_IN_MUX_11_HSIOM_IO_INPUT18 = 0x00000B8Du, /* peri.tr_io_input[18] */ 1212 TRIG_IN_MUX_11_HSIOM_IO_INPUT19 = 0x00000B8Eu, /* peri.tr_io_input[19] */ 1213 TRIG_IN_MUX_11_HSIOM_IO_INPUT20 = 0x00000B8Fu, /* peri.tr_io_input[20] */ 1214 TRIG_IN_MUX_11_HSIOM_IO_INPUT21 = 0x00000B90u, /* peri.tr_io_input[21] */ 1215 TRIG_IN_MUX_11_HSIOM_IO_INPUT22 = 0x00000B91u, /* peri.tr_io_input[22] */ 1216 TRIG_IN_MUX_11_HSIOM_IO_INPUT23 = 0x00000B92u, /* peri.tr_io_input[23] */ 1217 TRIG_IN_MUX_11_HSIOM_IO_INPUT24 = 0x00000B93u, /* peri.tr_io_input[24] */ 1218 TRIG_IN_MUX_11_HSIOM_IO_INPUT25 = 0x00000B94u, /* peri.tr_io_input[25] */ 1219 TRIG_IN_MUX_11_HSIOM_IO_INPUT26 = 0x00000B95u, /* peri.tr_io_input[26] */ 1220 TRIG_IN_MUX_11_HSIOM_IO_INPUT27 = 0x00000B96u, /* peri.tr_io_input[27] */ 1221 TRIG_IN_MUX_11_HSIOM_IO_INPUT28 = 0x00000B97u, /* peri.tr_io_input[28] */ 1222 TRIG_IN_MUX_11_HSIOM_IO_INPUT29 = 0x00000B98u, /* peri.tr_io_input[29] */ 1223 TRIG_IN_MUX_11_HSIOM_IO_INPUT30 = 0x00000B99u, /* peri.tr_io_input[30] */ 1224 TRIG_IN_MUX_11_HSIOM_IO_INPUT31 = 0x00000B9Au, /* peri.tr_io_input[31] */ 1225 TRIG_IN_MUX_11_HSIOM_IO_INPUT32 = 0x00000B9Bu, /* peri.tr_io_input[32] */ 1226 TRIG_IN_MUX_11_HSIOM_IO_INPUT33 = 0x00000B9Cu, /* peri.tr_io_input[33] */ 1227 TRIG_IN_MUX_11_HSIOM_IO_INPUT34 = 0x00000B9Du, /* peri.tr_io_input[34] */ 1228 TRIG_IN_MUX_11_HSIOM_IO_INPUT35 = 0x00000B9Eu, /* peri.tr_io_input[35] */ 1229 TRIG_IN_MUX_11_HSIOM_IO_INPUT36 = 0x00000B9Fu, /* peri.tr_io_input[36] */ 1230 TRIG_IN_MUX_11_HSIOM_IO_INPUT37 = 0x00000BA0u, /* peri.tr_io_input[37] */ 1231 TRIG_IN_MUX_11_HSIOM_IO_INPUT38 = 0x00000BA1u, /* peri.tr_io_input[38] */ 1232 TRIG_IN_MUX_11_HSIOM_IO_INPUT39 = 0x00000BA2u, /* peri.tr_io_input[39] */ 1233 TRIG_IN_MUX_11_HSIOM_IO_INPUT40 = 0x00000BA3u, /* peri.tr_io_input[40] */ 1234 TRIG_IN_MUX_11_HSIOM_IO_INPUT41 = 0x00000BA4u, /* peri.tr_io_input[41] */ 1235 TRIG_IN_MUX_11_HSIOM_IO_INPUT42 = 0x00000BA5u, /* peri.tr_io_input[42] */ 1236 TRIG_IN_MUX_11_HSIOM_IO_INPUT43 = 0x00000BA6u, /* peri.tr_io_input[43] */ 1237 TRIG_IN_MUX_11_HSIOM_IO_INPUT44 = 0x00000BA7u, /* peri.tr_io_input[44] */ 1238 TRIG_IN_MUX_11_HSIOM_IO_INPUT45 = 0x00000BA8u, /* peri.tr_io_input[45] */ 1239 TRIG_IN_MUX_11_HSIOM_IO_INPUT46 = 0x00000BA9u, /* peri.tr_io_input[46] */ 1240 TRIG_IN_MUX_11_HSIOM_IO_INPUT47 = 0x00000BAAu, /* peri.tr_io_input[47] */ 1241 TRIG_IN_MUX_11_CXPI_TX_TR_OUT0 = 0x00000BABu, /* cxpi[0].tr_tx_req[0] */ 1242 TRIG_IN_MUX_11_CXPI_TX_TR_OUT1 = 0x00000BACu, /* cxpi[0].tr_tx_req[1] */ 1243 TRIG_IN_MUX_11_CXPI_RX_TR_OUT0 = 0x00000BADu, /* cxpi[0].tr_rx_req[0] */ 1244 TRIG_IN_MUX_11_CXPI_RX_TR_OUT1 = 0x00000BAEu /* cxpi[0].tr_rx_req[1] */ 1245 } en_trig_input_debugreduction2_t; 1246 1247 /* Trigger Input Group 12 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1248 typedef enum 1249 { 1250 TRIG_IN_MUX_12_PDMA1_TR_OUT0 = 0x00000C01u, /* cpuss.dw1_tr_out[0] */ 1251 TRIG_IN_MUX_12_PDMA1_TR_OUT1 = 0x00000C02u, /* cpuss.dw1_tr_out[1] */ 1252 TRIG_IN_MUX_12_PDMA1_TR_OUT2 = 0x00000C03u, /* cpuss.dw1_tr_out[2] */ 1253 TRIG_IN_MUX_12_PDMA1_TR_OUT3 = 0x00000C04u, /* cpuss.dw1_tr_out[3] */ 1254 TRIG_IN_MUX_12_PDMA1_TR_OUT4 = 0x00000C05u, /* cpuss.dw1_tr_out[4] */ 1255 TRIG_IN_MUX_12_PDMA1_TR_OUT5 = 0x00000C06u, /* cpuss.dw1_tr_out[5] */ 1256 TRIG_IN_MUX_12_PDMA1_TR_OUT6 = 0x00000C07u, /* cpuss.dw1_tr_out[6] */ 1257 TRIG_IN_MUX_12_PDMA1_TR_OUT7 = 0x00000C08u, /* cpuss.dw1_tr_out[7] */ 1258 TRIG_IN_MUX_12_PDMA1_TR_OUT8 = 0x00000C09u, /* cpuss.dw1_tr_out[8] */ 1259 TRIG_IN_MUX_12_PDMA1_TR_OUT9 = 0x00000C0Au, /* cpuss.dw1_tr_out[9] */ 1260 TRIG_IN_MUX_12_PDMA1_TR_OUT10 = 0x00000C0Bu, /* cpuss.dw1_tr_out[10] */ 1261 TRIG_IN_MUX_12_PDMA1_TR_OUT11 = 0x00000C0Cu, /* cpuss.dw1_tr_out[11] */ 1262 TRIG_IN_MUX_12_PDMA1_TR_OUT12 = 0x00000C0Du, /* cpuss.dw1_tr_out[12] */ 1263 TRIG_IN_MUX_12_PDMA1_TR_OUT13 = 0x00000C0Eu, /* cpuss.dw1_tr_out[13] */ 1264 TRIG_IN_MUX_12_PDMA1_TR_OUT14 = 0x00000C0Fu, /* cpuss.dw1_tr_out[14] */ 1265 TRIG_IN_MUX_12_PDMA1_TR_OUT15 = 0x00000C10u, /* cpuss.dw1_tr_out[15] */ 1266 TRIG_IN_MUX_12_PDMA1_TR_OUT16 = 0x00000C11u, /* cpuss.dw1_tr_out[16] */ 1267 TRIG_IN_MUX_12_PDMA1_TR_OUT17 = 0x00000C12u, /* cpuss.dw1_tr_out[17] */ 1268 TRIG_IN_MUX_12_PDMA1_TR_OUT18 = 0x00000C13u, /* cpuss.dw1_tr_out[18] */ 1269 TRIG_IN_MUX_12_PDMA1_TR_OUT19 = 0x00000C14u, /* cpuss.dw1_tr_out[19] */ 1270 TRIG_IN_MUX_12_PDMA1_TR_OUT20 = 0x00000C15u, /* cpuss.dw1_tr_out[20] */ 1271 TRIG_IN_MUX_12_PDMA1_TR_OUT21 = 0x00000C16u, /* cpuss.dw1_tr_out[21] */ 1272 TRIG_IN_MUX_12_PDMA1_TR_OUT22 = 0x00000C17u, /* cpuss.dw1_tr_out[22] */ 1273 TRIG_IN_MUX_12_PDMA1_TR_OUT23 = 0x00000C18u, /* cpuss.dw1_tr_out[23] */ 1274 TRIG_IN_MUX_12_PDMA1_TR_OUT24 = 0x00000C19u, /* cpuss.dw1_tr_out[24] */ 1275 TRIG_IN_MUX_12_PDMA1_TR_OUT25 = 0x00000C1Au, /* cpuss.dw1_tr_out[25] */ 1276 TRIG_IN_MUX_12_PDMA1_TR_OUT26 = 0x00000C1Bu, /* cpuss.dw1_tr_out[26] */ 1277 TRIG_IN_MUX_12_PDMA1_TR_OUT27 = 0x00000C1Cu, /* cpuss.dw1_tr_out[27] */ 1278 TRIG_IN_MUX_12_PDMA1_TR_OUT28 = 0x00000C1Du, /* cpuss.dw1_tr_out[28] */ 1279 TRIG_IN_MUX_12_PDMA1_TR_OUT29 = 0x00000C1Eu, /* cpuss.dw1_tr_out[29] */ 1280 TRIG_IN_MUX_12_PDMA1_TR_OUT30 = 0x00000C1Fu, /* cpuss.dw1_tr_out[30] */ 1281 TRIG_IN_MUX_12_PDMA1_TR_OUT31 = 0x00000C20u, /* cpuss.dw1_tr_out[31] */ 1282 TRIG_IN_MUX_12_PDMA1_TR_OUT32 = 0x00000C21u, /* cpuss.dw1_tr_out[32] */ 1283 TRIG_IN_MUX_12_PDMA1_TR_OUT33 = 0x00000C22u, /* cpuss.dw1_tr_out[33] */ 1284 TRIG_IN_MUX_12_PDMA1_TR_OUT34 = 0x00000C23u, /* cpuss.dw1_tr_out[34] */ 1285 TRIG_IN_MUX_12_PDMA1_TR_OUT35 = 0x00000C24u, /* cpuss.dw1_tr_out[35] */ 1286 TRIG_IN_MUX_12_PDMA1_TR_OUT36 = 0x00000C25u, /* cpuss.dw1_tr_out[36] */ 1287 TRIG_IN_MUX_12_PDMA1_TR_OUT37 = 0x00000C26u, /* cpuss.dw1_tr_out[37] */ 1288 TRIG_IN_MUX_12_PDMA1_TR_OUT38 = 0x00000C27u, /* cpuss.dw1_tr_out[38] */ 1289 TRIG_IN_MUX_12_PDMA1_TR_OUT39 = 0x00000C28u, /* cpuss.dw1_tr_out[39] */ 1290 TRIG_IN_MUX_12_PDMA1_TR_OUT40 = 0x00000C29u, /* cpuss.dw1_tr_out[40] */ 1291 TRIG_IN_MUX_12_PDMA1_TR_OUT41 = 0x00000C2Au, /* cpuss.dw1_tr_out[41] */ 1292 TRIG_IN_MUX_12_PDMA1_TR_OUT42 = 0x00000C2Bu, /* cpuss.dw1_tr_out[42] */ 1293 TRIG_IN_MUX_12_PDMA1_TR_OUT43 = 0x00000C2Cu, /* cpuss.dw1_tr_out[43] */ 1294 TRIG_IN_MUX_12_PDMA1_TR_OUT44 = 0x00000C2Du, /* cpuss.dw1_tr_out[44] */ 1295 TRIG_IN_MUX_12_PDMA1_TR_OUT45 = 0x00000C2Eu, /* cpuss.dw1_tr_out[45] */ 1296 TRIG_IN_MUX_12_PDMA1_TR_OUT46 = 0x00000C2Fu, /* cpuss.dw1_tr_out[46] */ 1297 TRIG_IN_MUX_12_PDMA1_TR_OUT47 = 0x00000C30u, /* cpuss.dw1_tr_out[47] */ 1298 TRIG_IN_MUX_12_PDMA1_TR_OUT48 = 0x00000C31u, /* cpuss.dw1_tr_out[48] */ 1299 TRIG_IN_MUX_12_PDMA1_TR_OUT49 = 0x00000C32u, /* cpuss.dw1_tr_out[49] */ 1300 TRIG_IN_MUX_12_PDMA1_TR_OUT50 = 0x00000C33u, /* cpuss.dw1_tr_out[50] */ 1301 TRIG_IN_MUX_12_PDMA1_TR_OUT51 = 0x00000C34u, /* cpuss.dw1_tr_out[51] */ 1302 TRIG_IN_MUX_12_PDMA1_TR_OUT52 = 0x00000C35u, /* cpuss.dw1_tr_out[52] */ 1303 TRIG_IN_MUX_12_PDMA1_TR_OUT53 = 0x00000C36u, /* cpuss.dw1_tr_out[53] */ 1304 TRIG_IN_MUX_12_PDMA1_TR_OUT54 = 0x00000C37u, /* cpuss.dw1_tr_out[54] */ 1305 TRIG_IN_MUX_12_PDMA1_TR_OUT55 = 0x00000C38u, /* cpuss.dw1_tr_out[55] */ 1306 TRIG_IN_MUX_12_PDMA1_TR_OUT56 = 0x00000C39u, /* cpuss.dw1_tr_out[56] */ 1307 TRIG_IN_MUX_12_PDMA1_TR_OUT57 = 0x00000C3Au, /* cpuss.dw1_tr_out[57] */ 1308 TRIG_IN_MUX_12_PDMA1_TR_OUT58 = 0x00000C3Bu, /* cpuss.dw1_tr_out[58] */ 1309 TRIG_IN_MUX_12_PDMA1_TR_OUT59 = 0x00000C3Cu, /* cpuss.dw1_tr_out[59] */ 1310 TRIG_IN_MUX_12_PDMA1_TR_OUT60 = 0x00000C3Du, /* cpuss.dw1_tr_out[60] */ 1311 TRIG_IN_MUX_12_PDMA1_TR_OUT61 = 0x00000C3Eu, /* cpuss.dw1_tr_out[61] */ 1312 TRIG_IN_MUX_12_PDMA1_TR_OUT62 = 0x00000C3Fu, /* cpuss.dw1_tr_out[62] */ 1313 TRIG_IN_MUX_12_PDMA1_TR_OUT63 = 0x00000C40u, /* cpuss.dw1_tr_out[63] */ 1314 TRIG_IN_MUX_12_PDMA1_TR_OUT64 = 0x00000C41u, /* cpuss.dw1_tr_out[64] */ 1315 TRIG_IN_MUX_12_PDMA1_TR_OUT65 = 0x00000C42u, /* cpuss.dw1_tr_out[65] */ 1316 TRIG_IN_MUX_12_PDMA1_TR_OUT66 = 0x00000C43u, /* cpuss.dw1_tr_out[66] */ 1317 TRIG_IN_MUX_12_PDMA1_TR_OUT67 = 0x00000C44u, /* cpuss.dw1_tr_out[67] */ 1318 TRIG_IN_MUX_12_PDMA1_TR_OUT68 = 0x00000C45u, /* cpuss.dw1_tr_out[68] */ 1319 TRIG_IN_MUX_12_PDMA1_TR_OUT69 = 0x00000C46u, /* cpuss.dw1_tr_out[69] */ 1320 TRIG_IN_MUX_12_PDMA1_TR_OUT70 = 0x00000C47u, /* cpuss.dw1_tr_out[70] */ 1321 TRIG_IN_MUX_12_PDMA1_TR_OUT71 = 0x00000C48u, /* cpuss.dw1_tr_out[71] */ 1322 TRIG_IN_MUX_12_PDMA1_TR_OUT72 = 0x00000C49u, /* cpuss.dw1_tr_out[72] */ 1323 TRIG_IN_MUX_12_PDMA1_TR_OUT73 = 0x00000C4Au, /* cpuss.dw1_tr_out[73] */ 1324 TRIG_IN_MUX_12_PDMA1_TR_OUT74 = 0x00000C4Bu, /* cpuss.dw1_tr_out[74] */ 1325 TRIG_IN_MUX_12_PDMA1_TR_OUT75 = 0x00000C4Cu, /* cpuss.dw1_tr_out[75] */ 1326 TRIG_IN_MUX_12_PDMA1_TR_OUT76 = 0x00000C4Du, /* cpuss.dw1_tr_out[76] */ 1327 TRIG_IN_MUX_12_PDMA1_TR_OUT77 = 0x00000C4Eu, /* cpuss.dw1_tr_out[77] */ 1328 TRIG_IN_MUX_12_PDMA1_TR_OUT78 = 0x00000C4Fu, /* cpuss.dw1_tr_out[78] */ 1329 TRIG_IN_MUX_12_PDMA1_TR_OUT79 = 0x00000C50u, /* cpuss.dw1_tr_out[79] */ 1330 TRIG_IN_MUX_12_PDMA1_TR_OUT80 = 0x00000C51u, /* cpuss.dw1_tr_out[80] */ 1331 TRIG_IN_MUX_12_PDMA1_TR_OUT81 = 0x00000C52u, /* cpuss.dw1_tr_out[81] */ 1332 TRIG_IN_MUX_12_PDMA1_TR_OUT82 = 0x00000C53u, /* cpuss.dw1_tr_out[82] */ 1333 TRIG_IN_MUX_12_PDMA1_TR_OUT83 = 0x00000C54u, /* cpuss.dw1_tr_out[83] */ 1334 TRIG_IN_MUX_12_MDMA_TR_OUT0 = 0x00000C55u, /* cpuss.dmac_tr_out[0] */ 1335 TRIG_IN_MUX_12_MDMA_TR_OUT1 = 0x00000C56u, /* cpuss.dmac_tr_out[1] */ 1336 TRIG_IN_MUX_12_MDMA_TR_OUT2 = 0x00000C57u, /* cpuss.dmac_tr_out[2] */ 1337 TRIG_IN_MUX_12_MDMA_TR_OUT3 = 0x00000C58u, /* cpuss.dmac_tr_out[3] */ 1338 TRIG_IN_MUX_12_MDMA_TR_OUT4 = 0x00000C59u, /* cpuss.dmac_tr_out[4] */ 1339 TRIG_IN_MUX_12_MDMA_TR_OUT5 = 0x00000C5Au, /* cpuss.dmac_tr_out[5] */ 1340 TRIG_IN_MUX_12_MDMA_TR_OUT6 = 0x00000C5Bu, /* cpuss.dmac_tr_out[6] */ 1341 TRIG_IN_MUX_12_MDMA_TR_OUT7 = 0x00000C5Cu, /* cpuss.dmac_tr_out[7] */ 1342 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT10 = 0x00000C5Du, /* tcpwm[0].tr_out1[512] */ 1343 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT11 = 0x00000C5Eu, /* tcpwm[0].tr_out1[513] */ 1344 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT12 = 0x00000C5Fu, /* tcpwm[0].tr_out1[514] */ 1345 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT13 = 0x00000C60u, /* tcpwm[0].tr_out1[515] */ 1346 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT14 = 0x00000C61u, /* tcpwm[0].tr_out1[516] */ 1347 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT15 = 0x00000C62u, /* tcpwm[0].tr_out1[517] */ 1348 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT16 = 0x00000C63u, /* tcpwm[0].tr_out1[518] */ 1349 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT17 = 0x00000C64u, /* tcpwm[0].tr_out1[519] */ 1350 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT18 = 0x00000C65u, /* tcpwm[0].tr_out1[520] */ 1351 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT19 = 0x00000C66u, /* tcpwm[0].tr_out1[521] */ 1352 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT110 = 0x00000C67u, /* tcpwm[0].tr_out1[522] */ 1353 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT111 = 0x00000C68u, /* tcpwm[0].tr_out1[523] */ 1354 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT112 = 0x00000C69u, /* tcpwm[0].tr_out1[524] */ 1355 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT113 = 0x00000C6Au, /* tcpwm[0].tr_out1[525] */ 1356 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT114 = 0x00000C6Bu, /* tcpwm[0].tr_out1[526] */ 1357 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT115 = 0x00000C6Cu, /* tcpwm[0].tr_out1[527] */ 1358 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT116 = 0x00000C6Du, /* tcpwm[0].tr_out1[528] */ 1359 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT117 = 0x00000C6Eu, /* tcpwm[0].tr_out1[529] */ 1360 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT118 = 0x00000C6Fu, /* tcpwm[0].tr_out1[530] */ 1361 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT119 = 0x00000C70u, /* tcpwm[0].tr_out1[531] */ 1362 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT120 = 0x00000C71u, /* tcpwm[0].tr_out1[532] */ 1363 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT121 = 0x00000C72u, /* tcpwm[0].tr_out1[533] */ 1364 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT122 = 0x00000C73u, /* tcpwm[0].tr_out1[534] */ 1365 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT123 = 0x00000C74u, /* tcpwm[0].tr_out1[535] */ 1366 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT124 = 0x00000C75u, /* tcpwm[0].tr_out1[536] */ 1367 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT125 = 0x00000C76u, /* tcpwm[0].tr_out1[537] */ 1368 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT126 = 0x00000C77u, /* tcpwm[0].tr_out1[538] */ 1369 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT127 = 0x00000C78u, /* tcpwm[0].tr_out1[539] */ 1370 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT128 = 0x00000C79u, /* tcpwm[0].tr_out1[540] */ 1371 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT129 = 0x00000C7Au, /* tcpwm[0].tr_out1[541] */ 1372 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT130 = 0x00000C7Bu, /* tcpwm[0].tr_out1[542] */ 1373 TRIG_IN_MUX_12_TCPWM0_32_TR_OUT131 = 0x00000C7Cu, /* tcpwm[0].tr_out1[543] */ 1374 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT10 = 0x00000C7Du, /* tcpwm[0].tr_out1[256] */ 1375 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT11 = 0x00000C7Eu, /* tcpwm[0].tr_out1[257] */ 1376 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT12 = 0x00000C7Fu, /* tcpwm[0].tr_out1[258] */ 1377 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT13 = 0x00000C80u, /* tcpwm[0].tr_out1[259] */ 1378 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT14 = 0x00000C81u, /* tcpwm[0].tr_out1[260] */ 1379 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT15 = 0x00000C82u, /* tcpwm[0].tr_out1[261] */ 1380 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT16 = 0x00000C83u, /* tcpwm[0].tr_out1[262] */ 1381 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT17 = 0x00000C84u, /* tcpwm[0].tr_out1[263] */ 1382 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT18 = 0x00000C85u, /* tcpwm[0].tr_out1[264] */ 1383 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT19 = 0x00000C86u, /* tcpwm[0].tr_out1[265] */ 1384 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT110 = 0x00000C87u, /* tcpwm[0].tr_out1[266] */ 1385 TRIG_IN_MUX_12_TCPWM0_16M_TR_OUT111 = 0x00000C88u, /* tcpwm[0].tr_out1[267] */ 1386 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT10 = 0x00000C89u, /* tcpwm[0].tr_out1[0] */ 1387 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT11 = 0x00000C8Au, /* tcpwm[0].tr_out1[1] */ 1388 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT12 = 0x00000C8Bu, /* tcpwm[0].tr_out1[2] */ 1389 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT13 = 0x00000C8Cu, /* tcpwm[0].tr_out1[3] */ 1390 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT14 = 0x00000C8Du, /* tcpwm[0].tr_out1[4] */ 1391 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT15 = 0x00000C8Eu, /* tcpwm[0].tr_out1[5] */ 1392 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT16 = 0x00000C8Fu, /* tcpwm[0].tr_out1[6] */ 1393 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT17 = 0x00000C90u, /* tcpwm[0].tr_out1[7] */ 1394 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT18 = 0x00000C91u, /* tcpwm[0].tr_out1[8] */ 1395 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT19 = 0x00000C92u, /* tcpwm[0].tr_out1[9] */ 1396 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT110 = 0x00000C93u, /* tcpwm[0].tr_out1[10] */ 1397 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT111 = 0x00000C94u, /* tcpwm[0].tr_out1[11] */ 1398 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT112 = 0x00000C95u, /* tcpwm[0].tr_out1[12] */ 1399 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT113 = 0x00000C96u, /* tcpwm[0].tr_out1[13] */ 1400 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT114 = 0x00000C97u, /* tcpwm[0].tr_out1[14] */ 1401 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT115 = 0x00000C98u, /* tcpwm[0].tr_out1[15] */ 1402 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT116 = 0x00000C99u, /* tcpwm[0].tr_out1[16] */ 1403 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT117 = 0x00000C9Au, /* tcpwm[0].tr_out1[17] */ 1404 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT118 = 0x00000C9Bu, /* tcpwm[0].tr_out1[18] */ 1405 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT119 = 0x00000C9Cu, /* tcpwm[0].tr_out1[19] */ 1406 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT120 = 0x00000C9Du, /* tcpwm[0].tr_out1[20] */ 1407 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT121 = 0x00000C9Eu, /* tcpwm[0].tr_out1[21] */ 1408 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT122 = 0x00000C9Fu, /* tcpwm[0].tr_out1[22] */ 1409 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT123 = 0x00000CA0u, /* tcpwm[0].tr_out1[23] */ 1410 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT124 = 0x00000CA1u, /* tcpwm[0].tr_out1[24] */ 1411 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT125 = 0x00000CA2u, /* tcpwm[0].tr_out1[25] */ 1412 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT126 = 0x00000CA3u, /* tcpwm[0].tr_out1[26] */ 1413 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT127 = 0x00000CA4u, /* tcpwm[0].tr_out1[27] */ 1414 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT128 = 0x00000CA5u, /* tcpwm[0].tr_out1[28] */ 1415 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT129 = 0x00000CA6u, /* tcpwm[0].tr_out1[29] */ 1416 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT130 = 0x00000CA7u, /* tcpwm[0].tr_out1[30] */ 1417 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT131 = 0x00000CA8u, /* tcpwm[0].tr_out1[31] */ 1418 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT132 = 0x00000CA9u, /* tcpwm[0].tr_out1[32] */ 1419 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT133 = 0x00000CAAu, /* tcpwm[0].tr_out1[33] */ 1420 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT134 = 0x00000CABu, /* tcpwm[0].tr_out1[34] */ 1421 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT135 = 0x00000CACu, /* tcpwm[0].tr_out1[35] */ 1422 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT136 = 0x00000CADu, /* tcpwm[0].tr_out1[36] */ 1423 TRIG_IN_MUX_12_TCPWM0_16_TR_OUT137 = 0x00000CAEu, /* tcpwm[0].tr_out1[37] */ 1424 TRIG_IN_MUX_12_PASS_GEN_TR_OUT0 = 0x00000CAFu, /* pass[0].tr_sar_gen_out[0] */ 1425 TRIG_IN_MUX_12_PASS_GEN_TR_OUT1 = 0x00000CB0u /* pass[0].tr_sar_gen_out[1] */ 1426 } en_trig_input_debugreduction3_t; 1427 1428 /* Trigger Input Group 13 - AXI-DMA Request Assignments */ 1429 typedef enum 1430 { 1431 TRIG_IN_MUX_13_TCPWM0_16_TR_OUT00 = 0x00000D01u, /* tcpwm[0].tr_out0[0] */ 1432 TRIG_IN_MUX_13_TCPWM0_16_TR_OUT01 = 0x00000D02u, /* tcpwm[0].tr_out0[1] */ 1433 TRIG_IN_MUX_13_TCPWM0_16_TR_OUT02 = 0x00000D03u, /* tcpwm[0].tr_out0[2] */ 1434 TRIG_IN_MUX_13_TCPWM0_16_TR_OUT03 = 0x00000D04u, /* tcpwm[0].tr_out0[3] */ 1435 TRIG_IN_MUX_13_TCPWM0_32_TR_OUT00 = 0x00000D05u, /* tcpwm[0].tr_out0[512] */ 1436 TRIG_IN_MUX_13_TCPWM0_32_TR_OUT01 = 0x00000D06u, /* tcpwm[0].tr_out0[513] */ 1437 TRIG_IN_MUX_13_TCPWM0_32_TR_OUT02 = 0x00000D07u, /* tcpwm[0].tr_out0[514] */ 1438 TRIG_IN_MUX_13_TCPWM0_32_TR_OUT03 = 0x00000D08u, /* tcpwm[0].tr_out0[515] */ 1439 TRIG_IN_MUX_13_AXIDMA_TR_OUT0 = 0x00000D09u, /* axi_dmac[0].tr_out[0] */ 1440 TRIG_IN_MUX_13_AXIDMA_TR_OUT1 = 0x00000D0Au, /* axi_dmac[0].tr_out[1] */ 1441 TRIG_IN_MUX_13_AXIDMA_TR_OUT2 = 0x00000D0Bu, /* axi_dmac[0].tr_out[2] */ 1442 TRIG_IN_MUX_13_AXIDMA_TR_OUT3 = 0x00000D0Cu /* axi_dmac[0].tr_out[3] */ 1443 } en_trig_input_axidma_t; 1444 1445 /* Trigger Group Outputs */ 1446 /* Trigger Output Group 0 - P-DMA0[0:15] Request Assignments */ 1447 typedef enum 1448 { 1449 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 1450 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 1451 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 1452 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ 1453 TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ 1454 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ 1455 TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ 1456 TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u, /* cpuss.dw0_tr_in[7] */ 1457 TRIG_OUT_MUX_0_PDMA0_TR_IN8 = 0x40000008u, /* cpuss.dw0_tr_in[8] */ 1458 TRIG_OUT_MUX_0_PDMA0_TR_IN9 = 0x40000009u, /* cpuss.dw0_tr_in[9] */ 1459 TRIG_OUT_MUX_0_PDMA0_TR_IN10 = 0x4000000Au, /* cpuss.dw0_tr_in[10] */ 1460 TRIG_OUT_MUX_0_PDMA0_TR_IN11 = 0x4000000Bu, /* cpuss.dw0_tr_in[11] */ 1461 TRIG_OUT_MUX_0_PDMA0_TR_IN12 = 0x4000000Cu, /* cpuss.dw0_tr_in[12] */ 1462 TRIG_OUT_MUX_0_PDMA0_TR_IN13 = 0x4000000Du, /* cpuss.dw0_tr_in[13] */ 1463 TRIG_OUT_MUX_0_PDMA0_TR_IN14 = 0x4000000Eu, /* cpuss.dw0_tr_in[14] */ 1464 TRIG_OUT_MUX_0_PDMA0_TR_IN15 = 0x4000000Fu /* cpuss.dw0_tr_in[15] */ 1465 } en_trig_output_pdma0_0_15_t; 1466 1467 /* Trigger Output Group 1 - P-DMA0[16:31] Request Assignments */ 1468 typedef enum 1469 { 1470 TRIG_OUT_MUX_1_PDMA0_TR_IN16 = 0x40000100u, /* cpuss.dw0_tr_in[16] */ 1471 TRIG_OUT_MUX_1_PDMA0_TR_IN17 = 0x40000101u, /* cpuss.dw0_tr_in[17] */ 1472 TRIG_OUT_MUX_1_PDMA0_TR_IN18 = 0x40000102u, /* cpuss.dw0_tr_in[18] */ 1473 TRIG_OUT_MUX_1_PDMA0_TR_IN19 = 0x40000103u, /* cpuss.dw0_tr_in[19] */ 1474 TRIG_OUT_MUX_1_PDMA0_TR_IN20 = 0x40000104u, /* cpuss.dw0_tr_in[20] */ 1475 TRIG_OUT_MUX_1_PDMA0_TR_IN21 = 0x40000105u, /* cpuss.dw0_tr_in[21] */ 1476 TRIG_OUT_MUX_1_PDMA0_TR_IN22 = 0x40000106u, /* cpuss.dw0_tr_in[22] */ 1477 TRIG_OUT_MUX_1_PDMA0_TR_IN23 = 0x40000107u, /* cpuss.dw0_tr_in[23] */ 1478 TRIG_OUT_MUX_1_PDMA0_TR_IN24 = 0x40000108u, /* cpuss.dw0_tr_in[24] */ 1479 TRIG_OUT_MUX_1_PDMA0_TR_IN25 = 0x40000109u, /* cpuss.dw0_tr_in[25] */ 1480 TRIG_OUT_MUX_1_PDMA0_TR_IN26 = 0x4000010Au, /* cpuss.dw0_tr_in[26] */ 1481 TRIG_OUT_MUX_1_PDMA0_TR_IN27 = 0x4000010Bu, /* cpuss.dw0_tr_in[27] */ 1482 TRIG_OUT_MUX_1_PDMA0_TR_IN28 = 0x4000010Cu, /* cpuss.dw0_tr_in[28] */ 1483 TRIG_OUT_MUX_1_PDMA0_TR_IN29 = 0x4000010Du, /* cpuss.dw0_tr_in[29] */ 1484 TRIG_OUT_MUX_1_PDMA0_TR_IN30 = 0x4000010Eu, /* cpuss.dw0_tr_in[30] */ 1485 TRIG_OUT_MUX_1_PDMA0_TR_IN31 = 0x4000010Fu /* cpuss.dw0_tr_in[31] */ 1486 } en_trig_output_pdma0_16_31_t; 1487 1488 /* Trigger Output Group 2 - P-DMA1[0:15] Request Assignments */ 1489 typedef enum 1490 { 1491 TRIG_OUT_MUX_2_PDMA1_TR_IN0 = 0x40000200u, /* cpuss.dw1_tr_in[0] */ 1492 TRIG_OUT_MUX_2_PDMA1_TR_IN1 = 0x40000201u, /* cpuss.dw1_tr_in[1] */ 1493 TRIG_OUT_MUX_2_PDMA1_TR_IN2 = 0x40000202u, /* cpuss.dw1_tr_in[2] */ 1494 TRIG_OUT_MUX_2_PDMA1_TR_IN3 = 0x40000203u, /* cpuss.dw1_tr_in[3] */ 1495 TRIG_OUT_MUX_2_PDMA1_TR_IN4 = 0x40000204u, /* cpuss.dw1_tr_in[4] */ 1496 TRIG_OUT_MUX_2_PDMA1_TR_IN5 = 0x40000205u, /* cpuss.dw1_tr_in[5] */ 1497 TRIG_OUT_MUX_2_PDMA1_TR_IN6 = 0x40000206u, /* cpuss.dw1_tr_in[6] */ 1498 TRIG_OUT_MUX_2_PDMA1_TR_IN7 = 0x40000207u, /* cpuss.dw1_tr_in[7] */ 1499 TRIG_OUT_MUX_2_PDMA1_TR_IN8 = 0x40000208u, /* cpuss.dw1_tr_in[8] */ 1500 TRIG_OUT_MUX_2_PDMA1_TR_IN9 = 0x40000209u, /* cpuss.dw1_tr_in[9] */ 1501 TRIG_OUT_MUX_2_PDMA1_TR_IN10 = 0x4000020Au, /* cpuss.dw1_tr_in[10] */ 1502 TRIG_OUT_MUX_2_PDMA1_TR_IN11 = 0x4000020Bu, /* cpuss.dw1_tr_in[11] */ 1503 TRIG_OUT_MUX_2_PDMA1_TR_IN12 = 0x4000020Cu, /* cpuss.dw1_tr_in[12] */ 1504 TRIG_OUT_MUX_2_PDMA1_TR_IN13 = 0x4000020Du, /* cpuss.dw1_tr_in[13] */ 1505 TRIG_OUT_MUX_2_PDMA1_TR_IN14 = 0x4000020Eu, /* cpuss.dw1_tr_in[14] */ 1506 TRIG_OUT_MUX_2_PDMA1_TR_IN15 = 0x4000020Fu /* cpuss.dw1_tr_in[15] */ 1507 } en_trig_output_pdma1_0_15_t; 1508 1509 /* Trigger Output Group 3 - M-DMA Request Assignments */ 1510 typedef enum 1511 { 1512 TRIG_OUT_MUX_3_MDMA_TR_IN0 = 0x40000300u, /* cpuss.dmac_tr_in[0] */ 1513 TRIG_OUT_MUX_3_MDMA_TR_IN1 = 0x40000301u, /* cpuss.dmac_tr_in[1] */ 1514 TRIG_OUT_MUX_3_MDMA_TR_IN2 = 0x40000302u, /* cpuss.dmac_tr_in[2] */ 1515 TRIG_OUT_MUX_3_MDMA_TR_IN3 = 0x40000303u, /* cpuss.dmac_tr_in[3] */ 1516 TRIG_OUT_MUX_3_MDMA_TR_IN4 = 0x40000304u, /* cpuss.dmac_tr_in[4] */ 1517 TRIG_OUT_MUX_3_MDMA_TR_IN5 = 0x40000305u, /* cpuss.dmac_tr_in[5] */ 1518 TRIG_OUT_MUX_3_MDMA_TR_IN6 = 0x40000306u, /* cpuss.dmac_tr_in[6] */ 1519 TRIG_OUT_MUX_3_MDMA_TR_IN7 = 0x40000307u /* cpuss.dmac_tr_in[7] */ 1520 } en_trig_output_mdma_t; 1521 1522 /* Trigger Output Group 4 - */ 1523 typedef enum 1524 { 1525 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN0 = 0x40000400u, /* tcpwm[0].tr_all_cnt_in[0] */ 1526 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN1 = 0x40000401u, /* tcpwm[0].tr_all_cnt_in[1] */ 1527 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN2 = 0x40000402u, /* tcpwm[0].tr_all_cnt_in[2] */ 1528 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN3 = 0x40000403u, /* tcpwm[0].tr_all_cnt_in[3] */ 1529 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN4 = 0x40000404u, /* tcpwm[0].tr_all_cnt_in[4] */ 1530 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN5 = 0x40000405u, /* tcpwm[0].tr_all_cnt_in[5] */ 1531 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN6 = 0x40000406u, /* tcpwm[0].tr_all_cnt_in[6] */ 1532 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN7 = 0x40000407u, /* tcpwm[0].tr_all_cnt_in[7] */ 1533 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN8 = 0x40000408u, /* tcpwm[0].tr_all_cnt_in[8] */ 1534 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN9 = 0x40000409u, /* tcpwm[0].tr_all_cnt_in[9] */ 1535 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN10 = 0x4000040Au, /* tcpwm[0].tr_all_cnt_in[10] */ 1536 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN11 = 0x4000040Bu, /* tcpwm[0].tr_all_cnt_in[11] */ 1537 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN12 = 0x4000040Cu, /* tcpwm[0].tr_all_cnt_in[12] */ 1538 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN13 = 0x4000040Du, /* tcpwm[0].tr_all_cnt_in[13] */ 1539 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN14 = 0x4000040Eu, /* tcpwm[0].tr_all_cnt_in[14] */ 1540 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN15 = 0x4000040Fu, /* tcpwm[0].tr_all_cnt_in[15] */ 1541 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN16 = 0x40000410u, /* tcpwm[0].tr_all_cnt_in[16] */ 1542 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN17 = 0x40000411u, /* tcpwm[0].tr_all_cnt_in[17] */ 1543 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN18 = 0x40000412u, /* tcpwm[0].tr_all_cnt_in[18] */ 1544 TRIG_OUT_MUX_4_TCPWM0_ALL_CNT_TR_IN19 = 0x40000413u /* tcpwm[0].tr_all_cnt_in[19] */ 1545 } en_trig_output_tcpwm0_t; 1546 1547 /* Trigger Output Group 5 - */ 1548 typedef enum 1549 { 1550 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN20 = 0x40000500u, /* tcpwm[0].tr_all_cnt_in[20] */ 1551 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN21 = 0x40000501u, /* tcpwm[0].tr_all_cnt_in[21] */ 1552 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN22 = 0x40000502u, /* tcpwm[0].tr_all_cnt_in[22] */ 1553 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN23 = 0x40000503u, /* tcpwm[0].tr_all_cnt_in[23] */ 1554 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN24 = 0x40000504u, /* tcpwm[0].tr_all_cnt_in[24] */ 1555 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN25 = 0x40000505u, /* tcpwm[0].tr_all_cnt_in[25] */ 1556 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN26 = 0x40000506u, /* tcpwm[0].tr_all_cnt_in[26] */ 1557 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN27 = 0x40000507u, /* tcpwm[0].tr_all_cnt_in[27] */ 1558 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN28 = 0x40000508u, /* tcpwm[0].tr_all_cnt_in[28] */ 1559 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN29 = 0x40000509u, /* tcpwm[0].tr_all_cnt_in[29] */ 1560 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN30 = 0x4000050Au, /* tcpwm[0].tr_all_cnt_in[30] */ 1561 TRIG_OUT_MUX_5_TCPWM0_ALL_CNT_TR_IN31 = 0x4000050Bu /* tcpwm[0].tr_all_cnt_in[31] */ 1562 } en_trig_output_tcpwm0_20_31_t; 1563 1564 /* Trigger Output Group 6 - TCPWM trigger inputs */ 1565 typedef enum 1566 { 1567 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN32 = 0x40000600u, /* tcpwm[0].tr_all_cnt_in[32] */ 1568 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN33 = 0x40000601u, /* tcpwm[0].tr_all_cnt_in[33] */ 1569 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN34 = 0x40000602u, /* tcpwm[0].tr_all_cnt_in[34] */ 1570 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN35 = 0x40000603u, /* tcpwm[0].tr_all_cnt_in[35] */ 1571 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN36 = 0x40000604u, /* tcpwm[0].tr_all_cnt_in[36] */ 1572 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN37 = 0x40000605u, /* tcpwm[0].tr_all_cnt_in[37] */ 1573 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN38 = 0x40000606u, /* tcpwm[0].tr_all_cnt_in[38] */ 1574 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN39 = 0x40000607u, /* tcpwm[0].tr_all_cnt_in[39] */ 1575 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN40 = 0x40000608u, /* tcpwm[0].tr_all_cnt_in[40] */ 1576 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN41 = 0x40000609u, /* tcpwm[0].tr_all_cnt_in[41] */ 1577 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN42 = 0x4000060Au, /* tcpwm[0].tr_all_cnt_in[42] */ 1578 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN43 = 0x4000060Bu, /* tcpwm[0].tr_all_cnt_in[43] */ 1579 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN44 = 0x4000060Cu, /* tcpwm[0].tr_all_cnt_in[44] */ 1580 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN45 = 0x4000060Du, /* tcpwm[0].tr_all_cnt_in[45] */ 1581 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN46 = 0x4000060Eu, /* tcpwm[0].tr_all_cnt_in[46] */ 1582 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN47 = 0x4000060Fu, /* tcpwm[0].tr_all_cnt_in[47] */ 1583 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN48 = 0x40000610u, /* tcpwm[0].tr_all_cnt_in[48] */ 1584 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN49 = 0x40000611u, /* tcpwm[0].tr_all_cnt_in[49] */ 1585 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN50 = 0x40000612u, /* tcpwm[0].tr_all_cnt_in[50] */ 1586 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN51 = 0x40000613u, /* tcpwm[0].tr_all_cnt_in[51] */ 1587 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN52 = 0x40000614u, /* tcpwm[0].tr_all_cnt_in[52] */ 1588 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN53 = 0x40000615u, /* tcpwm[0].tr_all_cnt_in[53] */ 1589 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN54 = 0x40000616u, /* tcpwm[0].tr_all_cnt_in[54] */ 1590 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN55 = 0x40000617u, /* tcpwm[0].tr_all_cnt_in[55] */ 1591 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN56 = 0x40000618u, /* tcpwm[0].tr_all_cnt_in[56] */ 1592 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN57 = 0x40000619u, /* tcpwm[0].tr_all_cnt_in[57] */ 1593 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN58 = 0x4000061Au, /* tcpwm[0].tr_all_cnt_in[58] */ 1594 TRIG_OUT_MUX_6_TCPWM0_ALL_CNT_TR_IN59 = 0x4000061Bu /* tcpwm[0].tr_all_cnt_in[59] */ 1595 } en_trig_output_tcpwm0_32_59_t; 1596 1597 /* Trigger Output Group 7 - PASS trigger multiplexer */ 1598 typedef enum 1599 { 1600 TRIG_OUT_MUX_7_PASS_GEN_TR_IN0 = 0x40000700u, /* pass[0].tr_sar_gen_in[0] */ 1601 TRIG_OUT_MUX_7_PASS_GEN_TR_IN1 = 0x40000701u, /* pass[0].tr_sar_gen_in[1] */ 1602 TRIG_OUT_MUX_7_PASS_GEN_TR_IN2 = 0x40000702u, /* pass[0].tr_sar_gen_in[2] */ 1603 TRIG_OUT_MUX_7_PASS_GEN_TR_IN3 = 0x40000703u /* pass[0].tr_sar_gen_in[3] */ 1604 } en_trig_output_pass_t; 1605 1606 /* Trigger Output Group 8 - CAN TT Synchronization triggers */ 1607 typedef enum 1608 { 1609 TRIG_OUT_MUX_8_CAN0_TT_TR_IN0 = 0x40000800u, /* canfd[0].tr_evt_swt_in[0] */ 1610 TRIG_OUT_MUX_8_CAN0_TT_TR_IN1 = 0x40000801u, /* canfd[0].tr_evt_swt_in[1] */ 1611 TRIG_OUT_MUX_8_CAN1_TT_TR_IN0 = 0x40000802u, /* canfd[1].tr_evt_swt_in[0] */ 1612 TRIG_OUT_MUX_8_CAN1_TT_TR_IN1 = 0x40000803u /* canfd[1].tr_evt_swt_in[1] */ 1613 } en_trig_output_can_t; 1614 1615 /* Trigger Output Group 9 - 2nd level MUX using input from MUX_11/12/13 */ 1616 typedef enum 1617 { 1618 TRIG_OUT_MUX_9_HSIOM_IO_OUTPUT0 = 0x40000900u, /* peri.tr_io_output[0] */ 1619 TRIG_OUT_MUX_9_HSIOM_IO_OUTPUT1 = 0x40000901u, /* peri.tr_io_output[1] */ 1620 TRIG_OUT_MUX_9_CTI_TR_IN0 = 0x40000902u, /* cpuss.cti_tr_in[0] */ 1621 TRIG_OUT_MUX_9_CTI_TR_IN1 = 0x40000903u, /* cpuss.cti_tr_in[1] */ 1622 TRIG_OUT_MUX_9_PERI_DEBUG_FREEZE_TR_IN = 0x40000904u, /* peri.tr_dbg_freeze */ 1623 TRIG_OUT_MUX_9_PASS_DEBUG_FREEZE_TR_IN = 0x40000905u, /* pass[0].tr_debug_freeze */ 1624 TRIG_OUT_MUX_9_SRSS_WDT_DEBUG_FREEZE_TR_IN = 0x40000906u, /* srss.tr_debug_freeze_wdt */ 1625 TRIG_OUT_MUX_9_SRSS_MCWDT_DEBUG_FREEZE_TR_IN2 = 0x40000907u, /* srss.tr_debug_freeze_mcwdt[2] */ 1626 TRIG_OUT_MUX_9_SRSS_MCWDT_DEBUG_FREEZE_TR_IN1 = 0x40000908u, /* srss.tr_debug_freeze_mcwdt[1] */ 1627 TRIG_OUT_MUX_9_SRSS_MCWDT_DEBUG_FREEZE_TR_IN0 = 0x40000909u, /* srss.tr_debug_freeze_mcwdt[0] */ 1628 TRIG_OUT_MUX_9_TCPWM0_DEBUG_FREEZE_TR_IN = 0x4000090Au, /* tcpwm[0].tr_debug_freeze */ 1629 TRIG_OUT_MUX_9_TDM0_DEBUG_FREEZE_TR_IN = 0x4000090Cu, /* tdm[0].tr_dbg_freeze */ 1630 TRIG_OUT_MUX_9_SG0_DEBUG_FREEZE_TR_IN = 0x4000090Du, /* sg[0].tr_dbg_freeze */ 1631 TRIG_OUT_MUX_9_PWM0_DEBUG_FREEZE_TR_IN = 0x4000090Eu, /* pwm[0].tr_dbg_freeze */ 1632 TRIG_OUT_MUX_9_MIXER0_DEBUG_FREEZE_TR_IN = 0x4000090Fu, /* mixer[0].tr_dbg_freeze */ 1633 TRIG_OUT_MUX_9_MIXER1_DEBUG_FREEZE_TR_IN = 0x40000910u, /* mixer[1].tr_dbg_freeze */ 1634 TRIG_OUT_MUX_9_AUDIODAC0_DEBUG_FREEZE_TR_IN = 0x40000911u /* dac[0].tr_dbg_freeze */ 1635 } en_trig_output_debugmain_t; 1636 1637 /* Trigger Output Group 10 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1638 typedef enum 1639 { 1640 TRIG_OUT_MUX_10_TR_GROUP9_INPUT1 = 0x40000A00u, /* tr_group[9].input[1] */ 1641 TRIG_OUT_MUX_10_TR_GROUP9_INPUT2 = 0x40000A01u, /* tr_group[9].input[2] */ 1642 TRIG_OUT_MUX_10_TR_GROUP9_INPUT3 = 0x40000A02u, /* tr_group[9].input[3] */ 1643 TRIG_OUT_MUX_10_TR_GROUP9_INPUT4 = 0x40000A03u, /* tr_group[9].input[4] */ 1644 TRIG_OUT_MUX_10_TR_GROUP9_INPUT5 = 0x40000A04u /* tr_group[9].input[5] */ 1645 } en_trig_output_debugreducation1_t; 1646 1647 /* Trigger Output Group 11 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1648 typedef enum 1649 { 1650 TRIG_OUT_MUX_11_TR_GROUP9_INPUT6 = 0x40000B00u, /* tr_group[9].input[6] */ 1651 TRIG_OUT_MUX_11_TR_GROUP9_INPUT7 = 0x40000B01u, /* tr_group[9].input[7] */ 1652 TRIG_OUT_MUX_11_TR_GROUP9_INPUT8 = 0x40000B02u, /* tr_group[9].input[8] */ 1653 TRIG_OUT_MUX_11_TR_GROUP9_INPUT9 = 0x40000B03u, /* tr_group[9].input[9] */ 1654 TRIG_OUT_MUX_11_TR_GROUP9_INPUT10 = 0x40000B04u /* tr_group[9].input[10] */ 1655 } en_trig_output_debugreduction2_t; 1656 1657 /* Trigger Output Group 12 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1658 typedef enum 1659 { 1660 TRIG_OUT_MUX_12_TR_GROUP9_INPUT11 = 0x40000C00u, /* tr_group[9].input[11] */ 1661 TRIG_OUT_MUX_12_TR_GROUP9_INPUT12 = 0x40000C01u, /* tr_group[9].input[12] */ 1662 TRIG_OUT_MUX_12_TR_GROUP9_INPUT13 = 0x40000C02u, /* tr_group[9].input[13] */ 1663 TRIG_OUT_MUX_12_TR_GROUP9_INPUT14 = 0x40000C03u, /* tr_group[9].input[14] */ 1664 TRIG_OUT_MUX_12_TR_GROUP9_INPUT15 = 0x40000C04u /* tr_group[9].input[15] */ 1665 } en_trig_output_debugreduction3_t; 1666 1667 /* Trigger Output Group 13 - AXI-DMA Request Assignments */ 1668 typedef enum 1669 { 1670 TRIG_OUT_MUX_13_AXIDMA_TR_IN0 = 0x40000D00u, /* axi_dmac[0].tr_in[0] */ 1671 TRIG_OUT_MUX_13_AXIDMA_TR_IN1 = 0x40000D01u, /* axi_dmac[0].tr_in[1] */ 1672 TRIG_OUT_MUX_13_AXIDMA_TR_IN2 = 0x40000D02u, /* axi_dmac[0].tr_in[2] */ 1673 TRIG_OUT_MUX_13_AXIDMA_TR_IN3 = 0x40000D03u /* axi_dmac[0].tr_in[3] */ 1674 } en_trig_output_axidma_t; 1675 1676 /* Trigger Output Group 0 - Dedicated triggers to PDMA0 (OneToOne) */ 1677 typedef enum 1678 { 1679 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_0 = 0x40001000u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw0_tr_in[32] */ 1680 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_0 = 0x40001001u, /* From canfd[0].tr_fifo0[0] to cpuss.dw0_tr_in[33] */ 1681 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_0 = 0x40001002u, /* From canfd[0].tr_fifo1[0] to cpuss.dw0_tr_in[34] */ 1682 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_1 = 0x40001003u, /* From canfd[0].tr_dbg_dma_req[1] to cpuss.dw0_tr_in[35] */ 1683 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_1 = 0x40001004u, /* From canfd[0].tr_fifo0[1] to cpuss.dw0_tr_in[36] */ 1684 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_1 = 0x40001005u, /* From canfd[0].tr_fifo1[1] to cpuss.dw0_tr_in[37] */ 1685 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA00 = 0x40001006u, /* From pass[0].tr_sar_ch_done[0] to cpuss.dw0_tr_in[38] */ 1686 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA01 = 0x40001007u, /* From pass[0].tr_sar_ch_done[1] to cpuss.dw0_tr_in[39] */ 1687 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA02 = 0x40001008u, /* From pass[0].tr_sar_ch_done[2] to cpuss.dw0_tr_in[40] */ 1688 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA03 = 0x40001009u, /* From pass[0].tr_sar_ch_done[3] to cpuss.dw0_tr_in[41] */ 1689 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA04 = 0x4000100Au, /* From pass[0].tr_sar_ch_done[4] to cpuss.dw0_tr_in[42] */ 1690 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA05 = 0x4000100Bu, /* From pass[0].tr_sar_ch_done[5] to cpuss.dw0_tr_in[43] */ 1691 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA06 = 0x4000100Cu, /* From pass[0].tr_sar_ch_done[6] to cpuss.dw0_tr_in[44] */ 1692 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA07 = 0x4000100Du, /* From pass[0].tr_sar_ch_done[7] to cpuss.dw0_tr_in[45] */ 1693 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA08 = 0x4000100Eu, /* From pass[0].tr_sar_ch_done[8] to cpuss.dw0_tr_in[46] */ 1694 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA09 = 0x4000100Fu, /* From pass[0].tr_sar_ch_done[9] to cpuss.dw0_tr_in[47] */ 1695 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA010 = 0x40001010u, /* From pass[0].tr_sar_ch_done[10] to cpuss.dw0_tr_in[48] */ 1696 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA011 = 0x40001011u, /* From pass[0].tr_sar_ch_done[11] to cpuss.dw0_tr_in[49] */ 1697 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA012 = 0x40001012u, /* From pass[0].tr_sar_ch_done[12] to cpuss.dw0_tr_in[50] */ 1698 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA013 = 0x40001013u, /* From pass[0].tr_sar_ch_done[13] to cpuss.dw0_tr_in[51] */ 1699 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA014 = 0x40001014u, /* From pass[0].tr_sar_ch_done[14] to cpuss.dw0_tr_in[52] */ 1700 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA015 = 0x40001015u, /* From pass[0].tr_sar_ch_done[15] to cpuss.dw0_tr_in[53] */ 1701 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA016 = 0x40001016u, /* From pass[0].tr_sar_ch_done[16] to cpuss.dw0_tr_in[54] */ 1702 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA017 = 0x40001017u, /* From pass[0].tr_sar_ch_done[17] to cpuss.dw0_tr_in[55] */ 1703 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA018 = 0x40001018u, /* From pass[0].tr_sar_ch_done[18] to cpuss.dw0_tr_in[56] */ 1704 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA019 = 0x40001019u, /* From pass[0].tr_sar_ch_done[19] to cpuss.dw0_tr_in[57] */ 1705 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA020 = 0x4000101Au, /* From pass[0].tr_sar_ch_done[20] to cpuss.dw0_tr_in[58] */ 1706 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA021 = 0x4000101Bu, /* From pass[0].tr_sar_ch_done[21] to cpuss.dw0_tr_in[59] */ 1707 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA022 = 0x4000101Cu, /* From pass[0].tr_sar_ch_done[22] to cpuss.dw0_tr_in[60] */ 1708 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA023 = 0x4000101Du, /* From pass[0].tr_sar_ch_done[23] to cpuss.dw0_tr_in[61] */ 1709 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA024 = 0x4000101Eu, /* From pass[0].tr_sar_ch_done[24] to cpuss.dw0_tr_in[62] */ 1710 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA025 = 0x4000101Fu, /* From pass[0].tr_sar_ch_done[25] to cpuss.dw0_tr_in[63] */ 1711 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA026 = 0x40001020u, /* From pass[0].tr_sar_ch_done[26] to cpuss.dw0_tr_in[64] */ 1712 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA027 = 0x40001021u, /* From pass[0].tr_sar_ch_done[27] to cpuss.dw0_tr_in[65] */ 1713 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA028 = 0x40001022u, /* From pass[0].tr_sar_ch_done[28] to cpuss.dw0_tr_in[66] */ 1714 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA029 = 0x40001023u, /* From pass[0].tr_sar_ch_done[29] to cpuss.dw0_tr_in[67] */ 1715 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA030 = 0x40001024u, /* From pass[0].tr_sar_ch_done[30] to cpuss.dw0_tr_in[68] */ 1716 TRIG_OUT_1TO1_0_PASS_CH_DONE_TO_PDMA031 = 0x40001025u, /* From pass[0].tr_sar_ch_done[31] to cpuss.dw0_tr_in[69] */ 1717 TRIG_OUT_1TO1_0_SMIF_TX_TO_PDMA0 = 0x40001026u, /* From smif[0].smif0_tr_tx_req to cpuss.dw0_tr_in[70] */ 1718 TRIG_OUT_1TO1_0_SMIF_RX_TO_PDMA0 = 0x40001027u, /* From smif[0].smif0_tr_rx_req to cpuss.dw0_tr_in[71] */ 1719 TRIG_OUT_1TO1_0_CXPI_TR_TX_REQ0 = 0x40001028u, /* From cxpi[0].tr_tx_req[0] to cpuss.dw0_tr_in[72] */ 1720 TRIG_OUT_1TO1_0_CXPI_TR_TX_REQ1 = 0x40001029u, /* From cxpi[0].tr_tx_req[1] to cpuss.dw0_tr_in[73] */ 1721 TRIG_OUT_1TO1_0_CXPI_TR_RX_REQ0 = 0x4000102Au, /* From cxpi[0].tr_rx_req[0] to cpuss.dw0_tr_in[74] */ 1722 TRIG_OUT_1TO1_0_CXPI_TR_RX_REQ1 = 0x4000102Bu /* From cxpi[0].tr_rx_req[1] to cpuss.dw0_tr_in[75] */ 1723 } en_trig_output_1to1_to_pdma0_t; 1724 1725 /* Trigger Output Group 1 - Dedicated triggers to PDMA1 (OneToOne) */ 1726 typedef enum 1727 { 1728 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA10 = 0x40001100u, /* From scb[0].tr_tx_req to cpuss.dw1_tr_in[16] */ 1729 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA10 = 0x40001101u, /* From scb[0].tr_rx_req to cpuss.dw1_tr_in[17] */ 1730 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA11 = 0x40001102u, /* From scb[1].tr_tx_req to cpuss.dw1_tr_in[18] */ 1731 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA11 = 0x40001103u, /* From scb[1].tr_rx_req to cpuss.dw1_tr_in[19] */ 1732 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA12 = 0x40001104u, /* From scb[2].tr_tx_req to cpuss.dw1_tr_in[20] */ 1733 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA12 = 0x40001105u, /* From scb[2].tr_rx_req to cpuss.dw1_tr_in[21] */ 1734 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA13 = 0x40001106u, /* From scb[3].tr_tx_req to cpuss.dw1_tr_in[22] */ 1735 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA13 = 0x40001107u, /* From scb[3].tr_rx_req to cpuss.dw1_tr_in[23] */ 1736 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA14 = 0x40001108u, /* From scb[4].tr_tx_req to cpuss.dw1_tr_in[24] */ 1737 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA14 = 0x40001109u, /* From scb[4].tr_rx_req to cpuss.dw1_tr_in[25] */ 1738 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA15 = 0x4000110Au, /* From scb[5].tr_tx_req to cpuss.dw1_tr_in[26] */ 1739 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA15 = 0x4000110Bu, /* From scb[5].tr_rx_req to cpuss.dw1_tr_in[27] */ 1740 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA16 = 0x4000110Cu, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[28] */ 1741 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA16 = 0x4000110Du, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[29] */ 1742 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA17 = 0x4000110Eu, /* From scb[7].tr_tx_req to cpuss.dw1_tr_in[30] */ 1743 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA17 = 0x4000110Fu, /* From scb[7].tr_rx_req to cpuss.dw1_tr_in[31] */ 1744 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA18 = 0x40001110u, /* From scb[8].tr_tx_req to cpuss.dw1_tr_in[32] */ 1745 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA18 = 0x40001111u, /* From scb[8].tr_rx_req to cpuss.dw1_tr_in[33] */ 1746 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA19 = 0x40001112u, /* From scb[9].tr_tx_req to cpuss.dw1_tr_in[34] */ 1747 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA19 = 0x40001113u, /* From scb[9].tr_rx_req to cpuss.dw1_tr_in[35] */ 1748 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA110 = 0x40001114u, /* From scb[10].tr_tx_req to cpuss.dw1_tr_in[36] */ 1749 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA110 = 0x40001115u, /* From scb[10].tr_rx_req to cpuss.dw1_tr_in[37] */ 1750 TRIG_OUT_1TO1_1_SCB_TX_TO_PDMA111 = 0x40001116u, /* From scb[11].tr_tx_req to cpuss.dw1_tr_in[38] */ 1751 TRIG_OUT_1TO1_1_SCB_RX_TO_PDMA111 = 0x40001117u, /* From scb[11].tr_rx_req to cpuss.dw1_tr_in[39] */ 1752 TRIG_OUT_1TO1_1_CAN1_DBG_TO_PDMA1_0 = 0x40001118u, /* From canfd[1].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[40] */ 1753 TRIG_OUT_1TO1_1_CAN1_FIFO0_TO_PDMA1_0 = 0x40001119u, /* From canfd[1].tr_fifo0[0] to cpuss.dw1_tr_in[41] */ 1754 TRIG_OUT_1TO1_1_CAN1_FIFO1_TO_PDMA1_0 = 0x4000111Au, /* From canfd[1].tr_fifo1[0] to cpuss.dw1_tr_in[42] */ 1755 TRIG_OUT_1TO1_1_CAN1_DBG_TO_PDMA1_1 = 0x4000111Bu, /* From canfd[1].tr_dbg_dma_req[1] to cpuss.dw1_tr_in[43] */ 1756 TRIG_OUT_1TO1_1_CAN1_FIFO0_TO_PDMA1_1 = 0x4000111Cu, /* From canfd[1].tr_fifo0[1] to cpuss.dw1_tr_in[44] */ 1757 TRIG_OUT_1TO1_1_CAN1_FIFO1_TO_PDMA1_1 = 0x4000111Du, /* From canfd[1].tr_fifo1[1] to cpuss.dw1_tr_in[45] */ 1758 TRIG_OUT_1TO1_1_SMIF_TX_TO_PDMA1 = 0x4000111Eu, /* From smif[0].smif1_tr_tx_req to cpuss.dw1_tr_in[46] */ 1759 TRIG_OUT_1TO1_1_SMIF_RX_TO_PDMA1 = 0x4000111Fu, /* From smif[0].smif1_tr_rx_req to cpuss.dw1_tr_in[47] */ 1760 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA10 = 0x40001120u, /* From mixer[0].tr_src_req[0] to cpuss.dw1_tr_in[48] */ 1761 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA11 = 0x40001121u, /* From mixer[0].tr_src_req[1] to cpuss.dw1_tr_in[49] */ 1762 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA12 = 0x40001122u, /* From mixer[0].tr_src_req[2] to cpuss.dw1_tr_in[50] */ 1763 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA13 = 0x40001123u, /* From mixer[0].tr_src_req[3] to cpuss.dw1_tr_in[51] */ 1764 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA14 = 0x40001124u, /* From mixer[0].tr_src_req[4] to cpuss.dw1_tr_in[52] */ 1765 TRIG_OUT_1TO1_1_MIXER_DST_TO_PDMA10 = 0x40001125u, /* From mixer[0].tr_dst_req to cpuss.dw1_tr_in[53] */ 1766 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA15 = 0x40001126u, /* From mixer[1].tr_src_req[0] to cpuss.dw1_tr_in[54] */ 1767 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA16 = 0x40001127u, /* From mixer[1].tr_src_req[1] to cpuss.dw1_tr_in[55] */ 1768 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA17 = 0x40001128u, /* From mixer[1].tr_src_req[2] to cpuss.dw1_tr_in[56] */ 1769 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA18 = 0x40001129u, /* From mixer[1].tr_src_req[3] to cpuss.dw1_tr_in[57] */ 1770 TRIG_OUT_1TO1_1_MIXER_SRC_TO_PDMA19 = 0x4000112Au, /* From mixer[1].tr_src_req[4] to cpuss.dw1_tr_in[58] */ 1771 TRIG_OUT_1TO1_1_MIXER_DST_TO_PDMA11 = 0x4000112Bu, /* From mixer[1].tr_dst_req to cpuss.dw1_tr_in[59] */ 1772 TRIG_OUT_1TO1_1_AXI_DMAC_TO_PDMA10 = 0x4000112Cu, /* From axi_dmac[0].tr_out[0] to cpuss.dw1_tr_in[60] */ 1773 TRIG_OUT_1TO1_1_AXI_DMAC_TO_PDMA11 = 0x4000112Du, /* From axi_dmac[0].tr_out[1] to cpuss.dw1_tr_in[61] */ 1774 TRIG_OUT_1TO1_1_AXI_DMAC_TO_PDMA12 = 0x4000112Eu, /* From axi_dmac[0].tr_out[2] to cpuss.dw1_tr_in[62] */ 1775 TRIG_OUT_1TO1_1_AXI_DMAC_TO_PDMA13 = 0x4000112Fu, /* From axi_dmac[0].tr_out[3] to cpuss.dw1_tr_in[63] */ 1776 TRIG_OUT_1TO1_1_NOCONNECT = 0x40001130u, /* From to cpuss.dw1_tr_in[64] */ 1777 TRIG_OUT_1TO1_1_TDM_TX_TO_PDMA10 = 0x40001134u, /* From tdm[0].tr_tx_req[0] to cpuss.dw1_tr_in[68] */ 1778 TRIG_OUT_1TO1_1_TDM_TX_TO_PDMA11 = 0x40001135u, /* From tdm[0].tr_tx_req[1] to cpuss.dw1_tr_in[69] */ 1779 TRIG_OUT_1TO1_1_TDM_TX_TO_PDMA12 = 0x40001136u, /* From tdm[0].tr_tx_req[2] to cpuss.dw1_tr_in[70] */ 1780 TRIG_OUT_1TO1_1_TDM_TX_TO_PDMA13 = 0x40001137u, /* From tdm[0].tr_tx_req[3] to cpuss.dw1_tr_in[71] */ 1781 TRIG_OUT_1TO1_1_TDM_RX_TO_PDMA10 = 0x40001138u, /* From tdm[0].tr_rx_req[0] to cpuss.dw1_tr_in[72] */ 1782 TRIG_OUT_1TO1_1_TDM_RX_TO_PDMA11 = 0x40001139u, /* From tdm[0].tr_rx_req[1] to cpuss.dw1_tr_in[73] */ 1783 TRIG_OUT_1TO1_1_TDM_RX_TO_PDMA12 = 0x4000113Au, /* From tdm[0].tr_rx_req[2] to cpuss.dw1_tr_in[74] */ 1784 TRIG_OUT_1TO1_1_TDM_RX_TO_PDMA13 = 0x4000113Bu, /* From tdm[0].tr_rx_req[3] to cpuss.dw1_tr_in[75] */ 1785 TRIG_OUT_1TO1_1_SG_COMPLETE_TO_PDMA10 = 0x4000113Cu, /* From sg[0].tr_complete[0] to cpuss.dw1_tr_in[76] */ 1786 TRIG_OUT_1TO1_1_SG_COMPLETE_TO_PDMA11 = 0x4000113Du, /* From sg[0].tr_complete[1] to cpuss.dw1_tr_in[77] */ 1787 TRIG_OUT_1TO1_1_SG_COMPLETE_TO_PDMA12 = 0x4000113Eu, /* From sg[0].tr_complete[2] to cpuss.dw1_tr_in[78] */ 1788 TRIG_OUT_1TO1_1_SG_COMPLETE_TO_PDMA13 = 0x4000113Fu, /* From sg[0].tr_complete[3] to cpuss.dw1_tr_in[79] */ 1789 TRIG_OUT_1TO1_1_SG_COMPLETE_TO_PDMA14 = 0x40001140u, /* From sg[0].tr_complete[4] to cpuss.dw1_tr_in[80] */ 1790 TRIG_OUT_1TO1_1_PWM_TX_TO_PDMA10 = 0x40001141u, /* From pwm[0].tr_tx_req[0] to cpuss.dw1_tr_in[81] */ 1791 TRIG_OUT_1TO1_1_PWM_TX_TO_PDMA11 = 0x40001142u, /* From pwm[0].tr_tx_req[1] to cpuss.dw1_tr_in[82] */ 1792 TRIG_OUT_1TO1_1_AUDIODAC_TX_TO_PDMA1 = 0x40001143u /* From dac[0].tr_tx_req to cpuss.dw1_tr_in[83] */ 1793 } en_trig_output_1to1_to_pdma1_t; 1794 1795 /* Trigger Output Group 2 - Dedicated triggers to TCPWM[0] (OneToOne) */ 1796 typedef enum 1797 { 1798 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL0 = 0x40001200u, /* From pass[0].tr_sar_ch_rangevio[0] to tcpwm[0].tr_one_cnt_in[0] */ 1799 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL1 = 0x40001201u, /* From pass[0].tr_sar_ch_rangevio[1] to tcpwm[0].tr_one_cnt_in[1] */ 1800 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL2 = 0x40001202u, /* From pass[0].tr_sar_ch_rangevio[2] to tcpwm[0].tr_one_cnt_in[2] */ 1801 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL3 = 0x40001203u, /* From pass[0].tr_sar_ch_rangevio[3] to tcpwm[0].tr_one_cnt_in[3] */ 1802 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL4 = 0x40001204u, /* From pass[0].tr_sar_ch_rangevio[4] to tcpwm[0].tr_one_cnt_in[4] */ 1803 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL5 = 0x40001205u, /* From pass[0].tr_sar_ch_rangevio[5] to tcpwm[0].tr_one_cnt_in[5] */ 1804 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL6 = 0x40001206u, /* From pass[0].tr_sar_ch_rangevio[6] to tcpwm[0].tr_one_cnt_in[6] */ 1805 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL7 = 0x40001207u, /* From pass[0].tr_sar_ch_rangevio[7] to tcpwm[0].tr_one_cnt_in[7] */ 1806 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL8 = 0x40001208u, /* From pass[0].tr_sar_ch_rangevio[8] to tcpwm[0].tr_one_cnt_in[8] */ 1807 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL9 = 0x40001209u, /* From pass[0].tr_sar_ch_rangevio[9] to tcpwm[0].tr_one_cnt_in[9] */ 1808 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL10 = 0x4000120Au, /* From pass[0].tr_sar_ch_rangevio[10] to tcpwm[0].tr_one_cnt_in[10] */ 1809 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL11 = 0x4000120Bu, /* From pass[0].tr_sar_ch_rangevio[11] to tcpwm[0].tr_one_cnt_in[11] */ 1810 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL12 = 0x4000120Cu, /* From pass[0].tr_sar_ch_rangevio[12] to tcpwm[0].tr_one_cnt_in[12] */ 1811 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL13 = 0x4000120Du, /* From pass[0].tr_sar_ch_rangevio[13] to tcpwm[0].tr_one_cnt_in[13] */ 1812 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL14 = 0x4000120Eu, /* From pass[0].tr_sar_ch_rangevio[14] to tcpwm[0].tr_one_cnt_in[14] */ 1813 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL15 = 0x4000120Fu, /* From pass[0].tr_sar_ch_rangevio[15] to tcpwm[0].tr_one_cnt_in[15] */ 1814 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL16 = 0x40001210u, /* From pass[0].tr_sar_ch_rangevio[16] to tcpwm[0].tr_one_cnt_in[16] */ 1815 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL17 = 0x40001211u, /* From pass[0].tr_sar_ch_rangevio[17] to tcpwm[0].tr_one_cnt_in[17] */ 1816 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL18 = 0x40001212u, /* From pass[0].tr_sar_ch_rangevio[18] to tcpwm[0].tr_one_cnt_in[18] */ 1817 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL19 = 0x40001213u, /* From pass[0].tr_sar_ch_rangevio[19] to tcpwm[0].tr_one_cnt_in[19] */ 1818 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL20 = 0x40001214u, /* From pass[0].tr_sar_ch_rangevio[20] to tcpwm[0].tr_one_cnt_in[256] */ 1819 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL21 = 0x40001215u, /* From pass[0].tr_sar_ch_rangevio[21] to tcpwm[0].tr_one_cnt_in[257] */ 1820 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL22 = 0x40001216u, /* From pass[0].tr_sar_ch_rangevio[22] to tcpwm[0].tr_one_cnt_in[258] */ 1821 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL23 = 0x40001217u, /* From pass[0].tr_sar_ch_rangevio[23] to tcpwm[0].tr_one_cnt_in[259] */ 1822 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL24 = 0x40001218u, /* From pass[0].tr_sar_ch_rangevio[24] to tcpwm[0].tr_one_cnt_in[260] */ 1823 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL25 = 0x40001219u, /* From pass[0].tr_sar_ch_rangevio[25] to tcpwm[0].tr_one_cnt_in[261] */ 1824 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL26 = 0x4000121Au, /* From pass[0].tr_sar_ch_rangevio[26] to tcpwm[0].tr_one_cnt_in[262] */ 1825 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL27 = 0x4000121Bu, /* From pass[0].tr_sar_ch_rangevio[27] to tcpwm[0].tr_one_cnt_in[263] */ 1826 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL28 = 0x4000121Cu, /* From pass[0].tr_sar_ch_rangevio[28] to tcpwm[0].tr_one_cnt_in[264] */ 1827 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL29 = 0x4000121Du, /* From pass[0].tr_sar_ch_rangevio[29] to tcpwm[0].tr_one_cnt_in[265] */ 1828 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL30 = 0x4000121Eu, /* From pass[0].tr_sar_ch_rangevio[30] to tcpwm[0].tr_one_cnt_in[266] */ 1829 TRIG_OUT_1TO1_2_PASS_CH_RANGEVIO_TO_PWM0_KILL31 = 0x4000121Fu /* From pass[0].tr_sar_ch_rangevio[31] to tcpwm[0].tr_one_cnt_in[267] */ 1830 } en_trig_output_1to1_to_tcpwm0_t; 1831 1832 /* Trigger Output Group 3 - Dedicated triggers to PASS[0] (OneToOne) */ 1833 typedef enum 1834 { 1835 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR0 = 0x40001300u, /* From tcpwm[0].tr_out1[0] to pass[0].tr_sar_ch_in[0] */ 1836 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR1 = 0x40001301u, /* From tcpwm[0].tr_out1[1] to pass[0].tr_sar_ch_in[1] */ 1837 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR2 = 0x40001302u, /* From tcpwm[0].tr_out1[2] to pass[0].tr_sar_ch_in[2] */ 1838 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR3 = 0x40001303u, /* From tcpwm[0].tr_out1[3] to pass[0].tr_sar_ch_in[3] */ 1839 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR4 = 0x40001304u, /* From tcpwm[0].tr_out1[4] to pass[0].tr_sar_ch_in[4] */ 1840 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR5 = 0x40001305u, /* From tcpwm[0].tr_out1[5] to pass[0].tr_sar_ch_in[5] */ 1841 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR6 = 0x40001306u, /* From tcpwm[0].tr_out1[6] to pass[0].tr_sar_ch_in[6] */ 1842 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR7 = 0x40001307u, /* From tcpwm[0].tr_out1[7] to pass[0].tr_sar_ch_in[7] */ 1843 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR8 = 0x40001308u, /* From tcpwm[0].tr_out1[8] to pass[0].tr_sar_ch_in[8] */ 1844 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR9 = 0x40001309u, /* From tcpwm[0].tr_out1[9] to pass[0].tr_sar_ch_in[9] */ 1845 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR10 = 0x4000130Au, /* From tcpwm[0].tr_out1[10] to pass[0].tr_sar_ch_in[10] */ 1846 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR11 = 0x4000130Bu, /* From tcpwm[0].tr_out1[11] to pass[0].tr_sar_ch_in[11] */ 1847 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR12 = 0x4000130Cu, /* From tcpwm[0].tr_out1[12] to pass[0].tr_sar_ch_in[12] */ 1848 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR13 = 0x4000130Du, /* From tcpwm[0].tr_out1[13] to pass[0].tr_sar_ch_in[13] */ 1849 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR14 = 0x4000130Eu, /* From tcpwm[0].tr_out1[14] to pass[0].tr_sar_ch_in[14] */ 1850 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR15 = 0x4000130Fu, /* From tcpwm[0].tr_out1[15] to pass[0].tr_sar_ch_in[15] */ 1851 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR16 = 0x40001310u, /* From tcpwm[0].tr_out1[16] to pass[0].tr_sar_ch_in[16] */ 1852 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR17 = 0x40001311u, /* From tcpwm[0].tr_out1[17] to pass[0].tr_sar_ch_in[17] */ 1853 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR18 = 0x40001312u, /* From tcpwm[0].tr_out1[18] to pass[0].tr_sar_ch_in[18] */ 1854 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR19 = 0x40001313u, /* From tcpwm[0].tr_out1[19] to pass[0].tr_sar_ch_in[19] */ 1855 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR20 = 0x40001314u, /* From tcpwm[0].tr_out1[256] to pass[0].tr_sar_ch_in[20] */ 1856 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR21 = 0x40001315u, /* From tcpwm[0].tr_out1[257] to pass[0].tr_sar_ch_in[21] */ 1857 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR22 = 0x40001316u, /* From tcpwm[0].tr_out1[258] to pass[0].tr_sar_ch_in[22] */ 1858 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR23 = 0x40001317u, /* From tcpwm[0].tr_out1[259] to pass[0].tr_sar_ch_in[23] */ 1859 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR24 = 0x40001318u, /* From tcpwm[0].tr_out1[260] to pass[0].tr_sar_ch_in[24] */ 1860 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR25 = 0x40001319u, /* From tcpwm[0].tr_out1[261] to pass[0].tr_sar_ch_in[25] */ 1861 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR26 = 0x4000131Au, /* From tcpwm[0].tr_out1[262] to pass[0].tr_sar_ch_in[26] */ 1862 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR27 = 0x4000131Bu, /* From tcpwm[0].tr_out1[263] to pass[0].tr_sar_ch_in[27] */ 1863 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR28 = 0x4000131Cu, /* From tcpwm[0].tr_out1[264] to pass[0].tr_sar_ch_in[28] */ 1864 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR29 = 0x4000131Du, /* From tcpwm[0].tr_out1[265] to pass[0].tr_sar_ch_in[29] */ 1865 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR30 = 0x4000131Eu, /* From tcpwm[0].tr_out1[266] to pass[0].tr_sar_ch_in[30] */ 1866 TRIG_OUT_1TO1_3_TCPWM0_TO_PASS_CH_TR31 = 0x4000131Fu /* From tcpwm[0].tr_out1[267] to pass[0].tr_sar_ch_in[31] */ 1867 } en_trig_output_1to1_to_pass0_t; 1868 1869 /* Trigger Output Group 4 - Dedicated triggers to CANFD[1] (OneToOne) */ 1870 typedef enum 1871 { 1872 TRIG_OUT_1TO1_4_PDMA1_ACK_TO_CAN1_0 = 0x40001400u, /* From cpuss.dw1_tr_out[40] to canfd[1].tr_dbg_dma_ack[0] */ 1873 TRIG_OUT_1TO1_4_PDMA1_ACK_TO_CAN1_1 = 0x40001401u /* From cpuss.dw1_tr_out[43] to canfd[1].tr_dbg_dma_ack[1] */ 1874 } en_trig_output_1to1_to_canfd1_t; 1875 1876 /* Trigger Output Group 5 - Dedicated triggers to CANFD[0] (OneToOne) */ 1877 typedef enum 1878 { 1879 TRIG_OUT_1TO1_5_PDMA0_ACK_TO_CAN0_0 = 0x40001500u, /* From cpuss.dw0_tr_out[32] to canfd[0].tr_dbg_dma_ack[0] */ 1880 TRIG_OUT_1TO1_5_PDMA0_ACK_TO_CAN0_1 = 0x40001501u /* From cpuss.dw0_tr_out[35] to canfd[0].tr_dbg_dma_ack[1] */ 1881 } en_trig_output_1to1_to_canfd0_t; 1882 1883 /* Trigger Output Group 6 - Dedicated triggers to LIN[0] (OneToOne) */ 1884 typedef enum 1885 { 1886 TRIG_OUT_1TO1_6_TCPWM0_TO_LIN_TR0 = 0x40001600u, /* From tcpwm[0].tr_out1[24] to lin[0].tr_cmd_tx_header[0] */ 1887 TRIG_OUT_1TO1_6_TCPWM0_TO_LIN_TR1 = 0x40001601u /* From tcpwm[0].tr_out1[25] to lin[0].tr_cmd_tx_header[1] */ 1888 } en_trig_output_1to1_to_lin0_t; 1889 1890 /* Trigger Output Group 7 - Dedicated triggers to CXPI[0] (OneToOne) */ 1891 typedef enum 1892 { 1893 TRIG_OUT_1TO1_7_TCPWM_TO_CXPI_TR0 = 0x40001700u, /* From tcpwm[0].tr_out1[26] to cxpi[0].tr_cmd_tx_header[0] */ 1894 TRIG_OUT_1TO1_7_TCPWM_TO_CXPI_TR1 = 0x40001701u /* From tcpwm[0].tr_out1[27] to cxpi[0].tr_cmd_tx_header[1] */ 1895 } en_trig_output_1to1_to_cxpi0_t; 1896 1897 /* Level or edge detection setting for a trigger mux */ 1898 typedef enum 1899 { 1900 /* The trigger is a simple level output */ 1901 TRIGGER_TYPE_LEVEL = 0u, 1902 /* The trigger is synchronized to the consumer blocks clock 1903 and a two cycle pulse is generated on this clock */ 1904 TRIGGER_TYPE_EDGE = 1u 1905 } en_trig_type_t; 1906 1907 /* Trigger Type Defines */ 1908 /* CANFD Trigger Types */ 1909 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 1910 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 1911 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 1912 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 1913 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 1914 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 1915 /* CPUSS Trigger Types */ 1916 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 1917 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 1918 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1919 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE 1920 #define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE 1921 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1922 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 1923 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 1924 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1925 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE 1926 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE 1927 #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE 1928 /* CXPI Trigger Types */ 1929 #define TRIGGER_TYPE_CXPI_TR_CMD_TX_HEADER TRIGGER_TYPE_EDGE 1930 #define TRIGGER_TYPE_CXPI_TR_RX_REQ TRIGGER_TYPE_LEVEL 1931 #define TRIGGER_TYPE_CXPI_TR_TX_REQ TRIGGER_TYPE_LEVEL 1932 /* DAC Trigger Types */ 1933 #define TRIGGER_TYPE_DAC_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1934 #define TRIGGER_TYPE_DAC_TR_TX_REQ TRIGGER_TYPE_LEVEL 1935 /* LIN Trigger Types */ 1936 #define TRIGGER_TYPE_LIN_TR_CMD_TX_HEADER TRIGGER_TYPE_EDGE 1937 /* MIXER Trigger Types */ 1938 #define TRIGGER_TYPE_MIXER_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1939 #define TRIGGER_TYPE_MIXER_TR_DST_REQ TRIGGER_TYPE_LEVEL 1940 #define TRIGGER_TYPE_MIXER_TR_SRC_REQ TRIGGER_TYPE_LEVEL 1941 /* PASS Trigger Types */ 1942 #define TRIGGER_TYPE_PASS_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 1943 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__LEVEL TRIGGER_TYPE_LEVEL 1944 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__EDGE TRIGGER_TYPE_EDGE 1945 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__LEVEL TRIGGER_TYPE_LEVEL 1946 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__EDGE TRIGGER_TYPE_EDGE 1947 #define TRIGGER_TYPE_PASS_TR_SAR_CH_RANGEVIO TRIGGER_TYPE_EDGE 1948 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__LEVEL TRIGGER_TYPE_LEVEL 1949 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__EDGE TRIGGER_TYPE_EDGE 1950 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__LEVEL TRIGGER_TYPE_LEVEL 1951 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__EDGE TRIGGER_TYPE_EDGE 1952 /* PERI Trigger Types */ 1953 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1954 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1955 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 1956 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1957 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1958 /* PWM Trigger Types */ 1959 #define TRIGGER_TYPE_PWM_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1960 #define TRIGGER_TYPE_PWM_TR_TX_REQ TRIGGER_TYPE_LEVEL 1961 /* SCB Trigger Types */ 1962 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 1963 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 1964 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 1965 /* SG Trigger Types */ 1966 #define TRIGGER_TYPE_SG_TR_COMPLETE TRIGGER_TYPE_LEVEL 1967 #define TRIGGER_TYPE_SG_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1968 /* SMIF Trigger Types */ 1969 #define TRIGGER_TYPE_SMIF_SMIF0_TR_RX_REQ TRIGGER_TYPE_LEVEL 1970 #define TRIGGER_TYPE_SMIF_SMIF0_TR_TX_REQ TRIGGER_TYPE_LEVEL 1971 #define TRIGGER_TYPE_SMIF_SMIF1_TR_RX_REQ TRIGGER_TYPE_LEVEL 1972 #define TRIGGER_TYPE_SMIF_SMIF1_TR_TX_REQ TRIGGER_TYPE_LEVEL 1973 /* SRSS Trigger Types */ 1974 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_MCWDT TRIGGER_TYPE_LEVEL 1975 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_WDT TRIGGER_TYPE_LEVEL 1976 /* TCPWM Trigger Types */ 1977 #define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 1978 /* TDM Trigger Types */ 1979 #define TRIGGER_TYPE_TDM_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1980 #define TRIGGER_TYPE_TDM_TR_RX_REQ TRIGGER_TYPE_LEVEL 1981 #define TRIGGER_TYPE_TDM_TR_TX_REQ TRIGGER_TYPE_LEVEL 1982 /* TR_GROUP Trigger Types */ 1983 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1984 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1985 #define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1986 #define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE 1987 1988 /* Fault connections */ 1989 typedef enum 1990 { 1991 CPUSS_MPU_VIO_0 = 0x0000u, 1992 CPUSS_MPU_VIO_1 = 0x0001u, 1993 CPUSS_MPU_VIO_2 = 0x0002u, 1994 CPUSS_MPU_VIO_3 = 0x0003u, 1995 CPUSS_MPU_VIO_4 = 0x0004u, 1996 CPUSS_MPU_VIO_9 = 0x0009u, 1997 CPUSS_MPU_VIO_10 = 0x000Au, 1998 CPUSS_MPU_VIO_11 = 0x000Bu, 1999 CPUSS_MPU_VIO_12 = 0x000Cu, 2000 CPUSS_MPU_VIO_13 = 0x000Du, 2001 CPUSS_MPU_VIO_14 = 0x000Eu, 2002 CPUSS_MPU_VIO_15 = 0x000Fu, 2003 CPUSS_CM7_0_CACHE_C_ECC = 0x0010u, 2004 CPUSS_CM7_0_CACHE_NC_ECC = 0x0011u, 2005 CPUSS_CM7_0_TCM_C_ECC = 0x0012u, 2006 CPUSS_CM7_0_TCM_NC_ECC = 0x0013u, 2007 CPUSS_CM7_1_CACHE_C_ECC = 0x0014u, 2008 CPUSS_CM7_1_CACHE_NC_ECC = 0x0015u, 2009 CPUSS_CM7_1_TCM_C_ECC = 0x0016u, 2010 CPUSS_CM7_1_TCM_NC_ECC = 0x0017u, 2011 PERI_PERI_C_ECC = 0x0018u, 2012 PERI_PERI_NC_ECC = 0x0019u, 2013 PERI_MS_VIO_0 = 0x001Au, 2014 PERI_MS_VIO_1 = 0x001Bu, 2015 PERI_MS_VIO_2 = 0x001Cu, 2016 PERI_MS_VIO_3 = 0x001Du, 2017 PERI_MS_VIO_4 = 0x001Eu, 2018 PERI_GROUP_VIO_0 = 0x0020u, 2019 PERI_GROUP_VIO_1 = 0x0021u, 2020 PERI_GROUP_VIO_2 = 0x0022u, 2021 PERI_GROUP_VIO_3 = 0x0023u, 2022 PERI_GROUP_VIO_4 = 0x0024u, 2023 PERI_GROUP_VIO_5 = 0x0025u, 2024 PERI_GROUP_VIO_6 = 0x0026u, 2025 PERI_GROUP_VIO_8 = 0x0028u, 2026 PERI_GROUP_VIO_9 = 0x0029u, 2027 PERI_GROUP_VIO_10 = 0x002Au, 2028 CPUSS_FLASHC_MAIN_BUS_ERR = 0x0030u, 2029 CPUSS_FLASHC_MAIN_C_ECC = 0x0031u, 2030 CPUSS_FLASHC_MAIN_NC_ECC = 0x0032u, 2031 CPUSS_FLASHC_WORK_BUS_ERR = 0x0033u, 2032 CPUSS_FLASHC_WORK_C_ECC = 0x0034u, 2033 CPUSS_FLASHC_WORK_NC_ECC = 0x0035u, 2034 CPUSS_FLASHC_CM0_CA_C_ECC = 0x0036u, 2035 CPUSS_FLASHC_CM0_CA_NC_ECC = 0x0037u, 2036 CPUSS_FM_SRAM_C_ECC = 0x0038u, 2037 CPUSS_FM_SRAM_NC_ECC = 0x0039u, 2038 CPUSS_RAMC0_C_ECC = 0x003Au, 2039 CPUSS_RAMC0_NC_ECC = 0x003Bu, 2040 CPUSS_RAMC1_C_ECC = 0x003Cu, 2041 CPUSS_RAMC1_NC_ECC = 0x003Du, 2042 CPUSS_RAMC2_C_ECC = 0x003Eu, 2043 CPUSS_RAMC2_NC_ECC = 0x003Fu, 2044 CPUSS_CRYPTO_C_ECC = 0x0040u, 2045 CPUSS_CRYPTO_NC_ECC = 0x0041u, 2046 CPUSS_DW0_C_ECC = 0x0042u, 2047 CPUSS_DW0_NC_ECC = 0x0043u, 2048 CPUSS_DW1_C_ECC = 0x0044u, 2049 CPUSS_DW1_NC_ECC = 0x0045u, 2050 CANFD_0_CAN_C_ECC = 0x0046u, 2051 CANFD_0_CAN_NC_ECC = 0x0047u, 2052 CANFD_1_CAN_C_ECC = 0x0048u, 2053 CANFD_1_CAN_NC_ECC = 0x0049u, 2054 VIDEOSS_0_VRPU_RD_0 = 0x0052u, 2055 VIDEOSS_0_VRPU_RD_1 = 0x0053u, 2056 VIDEOSS_0_VRPU_RD_2 = 0x0054u, 2057 VIDEOSS_0_VRPU_RD_3 = 0x0055u, 2058 VIDEOSS_0_VRPU_RD_4 = 0x0056u, 2059 VIDEOSS_0_VRPU_WR_0 = 0x0057u, 2060 VIDEOSS_0_VRPU_WR_1 = 0x0058u, 2061 SRSS_FAULT_CSV = 0x005Au, 2062 SRSS_FAULT_SSV = 0x005Bu, 2063 SRSS_FAULT_MCWDT0 = 0x005Cu, 2064 SRSS_FAULT_MCWDT1 = 0x005Du, 2065 SRSS_FAULT_MCWDT2 = 0x005Eu 2066 } en_sysfault_source_t; 2067 2068 /* Bus masters */ 2069 typedef enum 2070 { 2071 CPUSS_MS_ID_CM0 = 0, 2072 CPUSS_MS_ID_CRYPTO = 1, 2073 CPUSS_MS_ID_DW0 = 2, 2074 CPUSS_MS_ID_DW1 = 3, 2075 CPUSS_MS_ID_DMAC = 4, 2076 CPUSS_MS_ID_SLOW0 = 5, 2077 CPUSS_MS_ID_SLOW1 = 6, 2078 CPUSS_MS_ID_FAST0 = 9, 2079 CPUSS_MS_ID_FAST1 = 10, 2080 CPUSS_MS_ID_FAST2 = 11, 2081 CPUSS_MS_ID_FAST3 = 12, 2082 CPUSS_MS_ID_CM7_1 = 13, 2083 CPUSS_MS_ID_CM7_0 = 14, 2084 CPUSS_MS_ID_TC = 15 2085 } en_prot_master_t; 2086 2087 /* Include IP definitions */ 2088 #include "ip/cyip_sflash_tviic2d6m.h" 2089 #include "ip/cyip_peri_v3.h" 2090 #include "ip/cyip_peri_ms_v3.h" 2091 #include "ip/cyip_peri_pclk_v3.h" 2092 #include "ip/cyip_crypto_v2.h" 2093 #include "ip/cyip_cpuss.h" 2094 #include "ip/cyip_fault.h" 2095 #include "ip/cyip_ipc.h" 2096 #include "ip/cyip_prot.h" 2097 #include "ip/cyip_flashc_ect.h" 2098 #include "ip/cyip_srss_v3_3.h" 2099 #include "ip/cyip_backup_v3_3.h" 2100 #include "ip/cyip_dw.h" 2101 #include "ip/cyip_dmac.h" 2102 #include "ip/cyip_axi_dmac.h" 2103 #include "ip/cyip_efuse_v2.h" 2104 #include "ip/cyip_efuse_data_v2_tviic2d6m.h" 2105 #include "ip/cyip_hsiom_v5.h" 2106 #include "ip/cyip_gpio_v5.h" 2107 #include "ip/cyip_smartio_v5.h" 2108 #include "ip/cyip_tcpwm_v2.h" 2109 #include "ip/cyip_evtgen.h" 2110 #include "ip/cyip_smif_v4.h" 2111 #include "ip/cyip_eth_v2.h" 2112 #include "ip/cyip_lin.h" 2113 #include "ip/cyip_canfd.h" 2114 #include "ip/cyip_scb_v2.h" 2115 #include "ip/cyip_tdm.h" 2116 #include "ip/cyip_sg.h" 2117 #include "ip/cyip_pwm.h" 2118 #include "ip/cyip_dac.h" 2119 #include "ip/cyip_pass.h" 2120 #include "ip/cyip_pd.h" 2121 2122 /* IP type definitions */ 2123 typedef CRYPTO_V2_Type CRYPTO_Type; 2124 2125 /* Parameter Defines */ 2126 /* Number of DMA channels */ 2127 #define AXI_DMAC_CH_NR 4u 2128 /* Software trigger present or not */ 2129 #define AXI_DMAC_SW_TR_PRESENT 1u 2130 /* Bit width of AXI transaction identifier */ 2131 #define AXI_DMAC_ID_WIDTH 12u 2132 /* Number of TTCAN instances */ 2133 #define CANFD0_CAN_NR 2u 2134 /* ECC logic present or not */ 2135 #define CANFD0_ECC_PRESENT 1u 2136 /* address included in ECC logic or not */ 2137 #define CANFD0_ECC_ADDR_PRESENT 1u 2138 /* Time Stamp counter present or not */ 2139 #define CANFD0_TS_PRESENT 1u 2140 /* Message RAM size in KB */ 2141 #define CANFD0_MRAM_SIZE 16u 2142 /* Message RAM address width */ 2143 #define CANFD0_MRAM_ADDR_WIDTH 12u 2144 /* Number of TTCAN instances */ 2145 #define CANFD1_CAN_NR 2u 2146 /* ECC logic present or not */ 2147 #define CANFD1_ECC_PRESENT 1u 2148 /* address included in ECC logic or not */ 2149 #define CANFD1_ECC_ADDR_PRESENT 1u 2150 /* Time Stamp counter present or not (required for instance 0, otherwise not 2151 allowed) */ 2152 #define CANFD1_TS_PRESENT 0u 2153 /* Message RAM size in KB */ 2154 #define CANFD1_MRAM_SIZE 16u 2155 /* Message RAM address width */ 2156 #define CANFD1_MRAM_ADDR_WIDTH 12u 2157 /* UDB present or not ('0': no, '1': yes) */ 2158 #define CPUSS_UDB_PRESENT 0u 2159 /* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the 2160 chips which doesn't use mxdft. */ 2161 #define CPUSS_MBIST_MMIO_PRESENT 0u 2162 /* System RAM 0 size in KB */ 2163 #define CPUSS_SRAM0_SIZE 256u 2164 /* Number of macros used to implement system RAM 0. Example: 8 if 256 KB system 2165 SRAM 0 is implemented with 8 32KB macros. */ 2166 #define CPUSS_RAMC0_MACRO_NR 8u 2167 /* System RAM 1 present or not ('0': no, '1': yes) */ 2168 #define CPUSS_RAMC1_PRESENT 1u 2169 /* System RAM 1 size in KB */ 2170 #define CPUSS_SRAM1_SIZE 256u 2171 /* Number of macros used to implement system RAM 1. */ 2172 #define CPUSS_RAMC1_MACRO_NR 8u 2173 /* System RAM 2 present or not ('0': no, '1': yes) */ 2174 #define CPUSS_RAMC2_PRESENT 1u 2175 /* System RAM 2 size in KB */ 2176 #define CPUSS_SRAM2_SIZE 128u 2177 /* Number of macros used to implement System RAM 2. */ 2178 #define CPUSS_RAMC2_MACRO_NR 4u 2179 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 2180 #define CPUSS_RAMC_ECC_PRESENT 1u 2181 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 2182 #define CPUSS_RAMC_ECC_ADDR_PRESENT 1u 2183 /* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ 2184 #define CPUSS_ECC_PRESENT 1u 2185 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 2186 #define CPUSS_DW_ECC_PRESENT 1u 2187 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 2188 #define CPUSS_DW_ECC_ADDR_PRESENT 1u 2189 /* System ROM size in KB */ 2190 #define CPUSS_ROM_SIZE 64u 2191 /* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM 2192 is implemented with 4 128KB macros. */ 2193 #define CPUSS_ROMC_MACRO_NR 1u 2194 /* Flash memory present or not ('0': no, '1': yes) */ 2195 #define CPUSS_FLASHC_PRESENT 1u 2196 /* Flash memory type ('0' : SONOS, '1': ECT) */ 2197 #define CPUSS_FLASHC_ECT 1u 2198 /* Flash main region size in KB */ 2199 #define CPUSS_FLASH_SIZE 0x00001800u 2200 /* Flash work region size in KB (EEPROM emulation, data) */ 2201 #define CPUSS_WFLASH_SIZE 128u 2202 /* Flash supervisory region size in KB */ 2203 #define CPUSS_SFLASH_SIZE 32u 2204 /* Flash data output word size (in Bits) Example: 256 for 256-bit Flash data 2205 output */ 2206 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 256u 2207 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 2208 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 2209 Flash, and no Work Flash present. */ 2210 #define CPUSS_FLASHC_SONOS_RWW 0u 2211 /* SONOS Flash, number of main sectors. */ 2212 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 0u 2213 /* SONOS Flash, number of rows per main sector. */ 2214 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 0u 2215 /* SONOS Flash, number of words per row of main sector. */ 2216 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 0u 2217 /* SONOS Flash, number of special sectors. */ 2218 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 0u 2219 /* SONOS Flash, number of rows per special sector. */ 2220 #define CPUSS_FLASHC_SONOS_SPL_ROWS 0u 2221 /* Flash memory ECC present or not ('0': no, '1': yes) */ 2222 #define CPUSS_FLASHC_FLASH_ECC_PRESENT 1u 2223 /* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ 2224 #define CPUSS_FLASHC_RAM_ECC_PRESENT 1u 2225 /* Number of external AHB-Lite slaves directly connected to slow AHB-Lite 2226 infrastructure. Maximum number of slave supported is 6. Width of this 2227 parameter is 6-bits. 1-bit mask for each slave indicating present or not. 2228 Example: 6'b00_0011 - slave 0 and slave 1 are present. Note: The 2229 SLOW_SLx_ADDR and SLOW_SLx_MASK parameters (for the slaves present) should be 2230 derived from the Memory Map. */ 2231 #define CPUSS_SLOW_SL_PRESENT 3u 2232 /* Number of external AXI slaves directly connected to fast AXI infrastructure. 2233 Maximum number of slave supported is 8. Width of this parameter is 8-bits. 2234 1-bit mask for each slave indicating present or not. Example: 8'b0000_0011 - 2235 slave 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK 2236 parameters (for the slaves present) should be derived from the Memory Map. */ 2237 #define CPUSS_FAST_SL_PRESENT 7u 2238 /* Number of external AHB-Lite masters driving the slow AHB-Lite infrastructure. 2239 Maximum number of masters supported is 2. Width of this parameter is 2-bits. 2240 1-bit mask for each master indicating present or not. Example: 2'b01 - master 2241 0 is present. */ 2242 #define CPUSS_SLOW_MS_PRESENT 0u 2243 /* Number of external AXI masters driving the fast AXI infrastructure. Maximum 2244 number of masters supported is 4. Width of this parameter is 4-bits. 1-bit 2245 mask for each master indicating present or not. Example: 4'b0001 - master 0 2246 is present. */ 2247 #define CPUSS_FAST_MS_PRESENT 15u 2248 /* Retain 'protection context' (PC), 'privileged' (P), 'Non Secure' (NS) 2249 attributes coming from external AXI master or use it from CPUSS protection 2250 MMIO (PROT_MPU.MS_CTL.PC, PROT_SMPU.MSx_CTL.P, PROT_SMPU.MSx_CTL.NS). Width 2251 of this parameter is 4-bits. 1-bit mask for each master indicating retain PC 2252 or not. */ 2253 #define CPUSS_AXIM_RETAIN_PROT 12u 2254 /* IRQ expander present ('0': no, '1': yes) */ 2255 #define CPUSS_SYSTEM_IRQ_PRESENT 1u 2256 /* Number of system interrupt inputs to CPUSS */ 2257 #define CPUSS_SYSTEM_INT_NR 798u 2258 /* Number of DeepSleep system interrupt inputs to CPUSS */ 2259 #define CPUSS_SYSTEM_DPSLP_INT_NR 50u 2260 /* Width of the CM7 interrupt priority bits. Legal range [3,8] Example: 3 = 8 2261 levels of priority 8 = 256 levels of priority */ 2262 #define CPUSS_CM7_LVL_WIDTH 3u 2263 /* Number of CM7 CPU Interrupts. Legal values 8 or 16. */ 2264 #define CPUSS_CM7_INT_NR 8u 2265 /* CM7 Cache SRAMs ECC present or not ('0': no, '1': yes) */ 2266 #define CPUSS_CM7_CACHE_ECC_PRESENT 1u 2267 /* CM7 TCM SRAMs ECC present or not ('0': no, '1': yes) */ 2268 #define CPUSS_CM7_TCM_ECC_PRESENT 1u 2269 /* CM7 TCM SRAMs address ECC present or not ('0': no, '1': yes) */ 2270 #define CPUSS_CM7_TCM_ECC_ADDR_PRESENT 0u 2271 /* CM7_0 Floating point unit configuration. Legal range [0,2] 0 - No FPU 1 - 2272 Single precision FPU 2 - Single and Double precision FPU */ 2273 #define CPUSS_CM7_0_FPU_LVL 2u 2274 /* Number of MPU regions in CM7_0. Legal values [0, 8, 16] */ 2275 #define CPUSS_CM7_0_MPU_NR 16u 2276 /* CM7_0 Instruction cache (ICACHE) size in KB */ 2277 #define CPUSS_CM7_0_ICACHE_SIZE 16u 2278 /* CM7_0 Data cache size (DCACHE) in KB */ 2279 #define CPUSS_CM7_0_DCACHE_SIZE 16u 2280 /* CM7_0 Instruction TCM (ITCM) size in KB */ 2281 #define CPUSS_CM7_0_ITCM_SIZE 64u 2282 /* CM7_0 Data TCM (DTCM) size in KB */ 2283 #define CPUSS_CM7_0_DTCM_SIZE 64u 2284 /* CM7_1 CPU present or not ('0': no, '1': yes) */ 2285 #define CPUSS_CM7_1_PRESENT 1u 2286 /* System interrupt functionality present or not ('0': no; '1': yes) for CM7_1. 2287 Not used for CM0+ CPU, which always uses system interrupt functionality. */ 2288 #define CPUSS_CM7_1_SYSTEM_IRQ_PRESENT 1u 2289 /* CM7_1 Floating point unit configuration. Legal range [0,2] 0 - No FPU 1 - 2290 Single precision FPU 2 - Single and Double precision FPU */ 2291 #define CPUSS_CM7_1_FPU_LVL 2u 2292 /* Number of MPU regions in CM7_1. Legal values [0, 8, 16] */ 2293 #define CPUSS_CM7_1_MPU_NR 16u 2294 /* CM7_1 Instruction cache (ICACHE) size in KB */ 2295 #define CPUSS_CM7_1_ICACHE_SIZE 16u 2296 /* CM7_1 Data cache size (DCACHE) in KB */ 2297 #define CPUSS_CM7_1_DCACHE_SIZE 16u 2298 /* CM7_1 Instruction TCM (ITCM) size in KB */ 2299 #define CPUSS_CM7_1_ITCM_SIZE 64u 2300 /* CM7_1 Data TCM (DTCM) size in KB */ 2301 #define CPUSS_CM7_1_DTCM_SIZE 64u 2302 /* Debug level. Legal range [0,3] */ 2303 #define CPUSS_DEBUG_LVL 3u 2304 /* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 2305 for trace level is not supported in CPUSS. // CPUSS_TRACE_LVL: // 0 = no 2306 tracing // 1 = only ITM source and TPIU sink (no ETM, Funnel, Replicator or 2307 ETB) // 2 = ITM and ETM sources, Funnel and TPIU (no Replicator or ETB) // 3 2308 = ITM and ETM sources, Funnel, Replicator, TPIU and ET */ 2309 #define CPUSS_TRACE_LVL 2u 2310 /* Embedded Trace Buffer present or not ('0': no, '1': yes) */ 2311 #define CPUSS_ETB_PRESENT 1u 2312 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2313 #define CPUSS_MTB_SRAM_SIZE 4u 2314 /* CM7 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2315 #define CPUSS_ETB_SRAM_SIZE 8u 2316 /* PTM interface present (0=No, 1=Yes) */ 2317 #define CPUSS_PTM_PRESENT 0u 2318 /* Width of the PTM interface in bits ([2,32]) */ 2319 #define CPUSS_PTM_WIDTH 1u 2320 /* Width of the TPIU interface in bits ([1,4]) */ 2321 #define CPUSS_TPIU_WIDTH 8u 2322 /* CoreSight Part Identification Number */ 2323 #define CPUSS_JEPID 52u 2324 /* CoreSight Part Identification Number */ 2325 #define CPUSS_JEPCONTINUATION 0u 2326 /* CoreSight Part Identification Number */ 2327 #define CPUSS_FAMILYID 262u 2328 /* ROM trim register width (for ARM 3, for Synopsys 5) */ 2329 #define CPUSS_ROM_TRIM_WIDTH 3u 2330 /* ROM trim register default (for both ARM and Synopsys 0x0000_0002) */ 2331 #define CPUSS_ROM_TRIM_DEFAULT 2u 2332 /* RAM trim register width (for ARM 8, for Synopsys 15) */ 2333 #define CPUSS_RAM_TRIM_WIDTH 8u 2334 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ 2335 #define CPUSS_RAM_TRIM_DEFAULT 98u 2336 /* Cryptography IP present or not ('0': no, '1': yes) */ 2337 #define CPUSS_CRYPTO_PRESENT 1u 2338 /* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2339 #define CPUSS_SW_TR_PRESENT 1u 2340 /* DataWire 0 present or not ('0': no, '1': yes) */ 2341 #define CPUSS_DW0_PRESENT 1u 2342 /* Number of DataWire 0 channels ([1, 1024]) */ 2343 #define CPUSS_DW0_CH_NR 76u 2344 /* DataWire 1 present or not ('0': no, '1': yes) */ 2345 #define CPUSS_DW1_PRESENT 1u 2346 /* Number of DataWire 1 channels ([1, 1024]) */ 2347 #define CPUSS_DW1_CH_NR 84u 2348 /* DMA controller present or not ('0': no, '1': yes) */ 2349 #define CPUSS_DMAC_PRESENT 1u 2350 /* Number of DMA controller channels ([1, 8]) */ 2351 #define CPUSS_DMAC_CH_NR 8u 2352 /* Width of external AXI master ID signals. Legal range [3,8] */ 2353 #define CPUSS_AXIM_ID_WIDTH 4u 2354 /* Width of external AXI slave ID signals. Legal range [12,17] */ 2355 #define CPUSS_AXIS_ID_WIDTH 13u 2356 /* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2357 #define CPUSS_CH_SW_TR_PRESENT 1u 2358 /* See MMIO2 instantiation or not */ 2359 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 2360 /* ETAS Calibration support pin out present (automotive only) */ 2361 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 1u 2362 /* TRACE_LVL>0 */ 2363 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 2364 /* PTM_PRESENT ? PTM_WIDTH : 0 */ 2365 #define CPUSS_CHIP_TOP_PTM_PRESENT_WIDTH 0u 2366 /* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ 2367 #define CPUSS_CH_STRUCT_SW_TR_PRESENT 1u 2368 /* Number of DataWire controllers present (max 2) (same as DW.NR above) */ 2369 #define CPUSS_CPUSS_DW_DW_NR 2u 2370 /* Number of channels in each DataWire controller */ 2371 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 76u 2372 /* Width of a channel number in bits */ 2373 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 7u 2374 /* Number of channels in each DataWire controller */ 2375 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 84u 2376 /* Width of a channel number in bits */ 2377 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 7u 2378 /* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ 2379 #define CPUSS_CRYPTO_ECC_PRESENT 1u 2380 /* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ 2381 #define CPUSS_CRYPTO_ECC_ADDR_PRESENT 1u 2382 /* AES cipher support ('0': no, '1': yes) */ 2383 #define CPUSS_CRYPTO_AES 1u 2384 /* (Tripple) DES cipher support ('0': no, '1': yes) */ 2385 #define CPUSS_CRYPTO_DES 1u 2386 /* Chacha support ('0': no, '1': yes) */ 2387 #define CPUSS_CRYPTO_CHACHA 1u 2388 /* Pseudo random number generation support ('0': no, '1': yes) */ 2389 #define CPUSS_CRYPTO_PR 1u 2390 /* SHA1 hash support ('0': no, '1': yes) */ 2391 #define CPUSS_CRYPTO_SHA1 1u 2392 /* SHA2 hash support ('0': no, '1': yes) */ 2393 #define CPUSS_CRYPTO_SHA2 1u 2394 /* SHA3 hash support ('0': no, '1': yes) */ 2395 #define CPUSS_CRYPTO_SHA3 1u 2396 /* Cyclic Redundancy Check support ('0': no, '1': yes) */ 2397 #define CPUSS_CRYPTO_CRC 1u 2398 /* True random number generation support ('0': no, '1': yes) */ 2399 #define CPUSS_CRYPTO_TR 1u 2400 /* Vector unit support ('0': no, '1': yes) */ 2401 #define CPUSS_CRYPTO_VU 1u 2402 /* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ 2403 #define CPUSS_CRYPTO_GCM 1u 2404 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, 2405 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 2406 kB and 16 kB memory buffer) */ 2407 #define CPUSS_CRYPTO_BUFF_SIZE 2048u 2408 /* Number of DMA controller channels ([1, 8]) */ 2409 #define CPUSS_DMAC_CH_NR 8u 2410 /* Number of DataWire controllers present (max 2) */ 2411 #define CPUSS_DW_NR 2u 2412 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 2413 #define CPUSS_DW_ECC_PRESENT 1u 2414 /* Number of fault structures. Legal range [1, 4] */ 2415 #define CPUSS_FAULT_FAULT_NR 4u 2416 /* Number of Flash BIST_DATA registers */ 2417 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 8u 2418 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 2419 #define CPUSS_FLASHC_PA_SIZE 128u 2420 /* SONOS Flash is used or not ('0': no, '1': yes) */ 2421 #define CPUSS_FLASHC_FLASHC_IS_SONOS 0u 2422 /* eCT Flash is used or not ('0': no, '1': yes) */ 2423 #define CPUSS_FLASHC_FLASHC_IS_ECT 1u 2424 /* Flash Controller Workflash sequencer present */ 2425 #define CPUSS_FLASHC_FLASHC_WORK_SEQ_PRESENT 1u 2426 /* CM7_1 CPU present or not ('0': no, '1': yes) */ 2427 #define CPUSS_FLASHC_CM7_1_PRESENT 1u 2428 /* External AHB-Lite master0 Present */ 2429 #define CPUSS_FLASHC_SLOW0_MS_PRESENT 0u 2430 /* External AHB-Lite master1 Present */ 2431 #define CPUSS_FLASHC_SLOW1_MS_PRESENT 0u 2432 /* Number of IPC structures. Legal range [1, 16] */ 2433 #define CPUSS_IPC_IPC_NR 8u 2434 /* Number of IPC interrupt structures. Legal range [1, 16] */ 2435 #define CPUSS_IPC_IPC_IRQ_NR 8u 2436 /* Master 0 protect contexts minus one */ 2437 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u 2438 /* Master 1 protect contexts minus one */ 2439 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u 2440 /* Master 2 protect contexts minus one */ 2441 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u 2442 /* Master 3 protect contexts minus one */ 2443 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u 2444 /* Master 4 protect contexts minus one */ 2445 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u 2446 /* Master 5 protect contexts minus one */ 2447 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u 2448 /* Master 6 protect contexts minus one */ 2449 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u 2450 /* Master 7 protect contexts minus one */ 2451 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u 2452 /* Master 8 protect contexts minus one */ 2453 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u 2454 /* Master 9 protect contexts minus one */ 2455 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 7u 2456 /* Master 10 protect contexts minus one */ 2457 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 7u 2458 /* Master 11 protect contexts minus one */ 2459 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 7u 2460 /* Master 12 protect contexts minus one */ 2461 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 7u 2462 /* Master 13 protect contexts minus one */ 2463 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 7u 2464 /* Master 14 protect contexts minus one */ 2465 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u 2466 /* Master 15 protect contexts minus one */ 2467 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u 2468 /* Number of SMPU protection structures */ 2469 #define CPUSS_PROT_SMPU_STRUCT_NR 16u 2470 /* Number of protection contexts supported minus 1. Legal range [1,16] */ 2471 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u 2472 /* Number of CXPI channels ([2, 32]). For test functionality (two channels are 2473 connected), the minimal number of CXPI channels is 2. */ 2474 #define CXPI_CH_NR 2u 2475 /* Spare Enable 0=no spare, 1=max, 2=min */ 2476 #define CXPI_SPARE_EN 1u 2477 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2478 #define CXPI_MASTER_WIDTH 8u 2479 /* Set to 1 if IP will instantiate spares (0=None, 1=Max, 2=Min) */ 2480 #define DAC_SPARE_EN 1u 2481 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2482 #define DAC_MASTER_WIDTH 8u 2483 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 2484 #define DAC_PLATFORM_VARIANT 2u 2485 /* RAM vendor (0=CYP, 1=SNPS, 2=ARM) */ 2486 #define DAC_RAM_VEND 2u 2487 /* DAC functionality */ 2488 #define DAC_CHIP_TOP_DAC_PRESENT 1u 2489 /* Number of HFCLK roots present. Must be > 0. Must be same as set for SRSS */ 2490 #define DFT_NUM_HFROOT 14u 2491 /* Width of clk_occ_fast output bus (number of external OCCs) */ 2492 #define DFT_EXT_OCC 2u 2493 /* Number of PLLs usable as struct mode clock source (number of clk_occ_fast 2494 clocks). Not expected to be more than 4 */ 2495 #define DFT_NUM_FASTCLK 1u 2496 /* Number of select signals to control each FASTCLK multiplexer. Not expected to 2497 be more than 2 */ 2498 #define DFT_NUM_FASTCLK_SEL 1u 2499 /* Number of MBIST controllers with corresponding mbist(pg)_done and mbist(pg)_go 2500 signals. Value defined by CIC during Pass 1 */ 2501 #define DFT_MBIST_C_NUM 46u 2502 /* Number of LBIST controllers with corresponding lbist_en, lbist_done and 2503 lbist_misr_fail signals. Value depends on number of HLB modules */ 2504 #define DFT_LBIST_C_NUM 3u 2505 /* Number of memory BISR chains (which can be loaded individually) */ 2506 #define DFT_MBISR_CH_NUM 1u 2507 /* Controls generation of (BI-) Monitor logic */ 2508 #define DFT_MONITOR_PRESENT 1u 2509 /* Controls generation of control/status registers for Mentor BISR */ 2510 #define DFT_MENTOR_BISR_PRESENT 1u 2511 /* Controls generation of control/status registers for "Direct MBIST Access" 2512 function */ 2513 #define DFT_DIRECT_MBIST_ACCESS_PRESENT 0u 2514 /* Controls generation of DIRECT_MBIST*_SEL and DIRECT_MBIST*_RESULT registers for 2515 "Direct MBIST Access" function */ 2516 #define DFT_DIRECT_MBIST_CTRL_ACCESS_PRESENT 0u 2517 /* Controls generation of BIST_STEP_SEL_EN and BIST_STEP_SEL register fields 2518 within DIRECT_MBIST_CTL reg */ 2519 #define DFT_DIRECT_MBIST_STEP_ACCESS_PRESENT 0u 2520 /* Controls generation of BIST_MEM_SEL_EN and BIST_MEM_SEL register fields within 2521 DIRECT_MBIST_CTL reg */ 2522 #define DFT_DIRECT_MBIST_MEM_ACCESS_PRESENT 0u 2523 /* Number of HLBs with Direct MBIST Access function (only used for 2524 DIRECT_MBIST_ACCESS_PRESENT=1) */ 2525 #define DFT_DIRECT_MBIST_BAP_NUM 1u 2526 /* Maximum value of MBIST controllers connected to single BAP (only used for 2527 DIRECT_MBIST_ACCESS_PRESENT=1) */ 2528 #define DFT_DIRECT_MBIST_CTRL_NUM 1u 2529 /* Must be set to 1 when using this mxdft version in MXS40Sv2 devices */ 2530 #define DFT_PLATFORM_MXS40SV2 0u 2531 /* local parameter in mxdft_mmio.v (here only used for header file generation) */ 2532 #define DFT_MBIST0_C_NUM 32u 2533 /* local parameter in mxdft_mmio.v (here only used for header file generation) */ 2534 #define DFT_MBIST1_C_NUM 14u 2535 /* local parameter in mxdft_mmio.v (here only used for header file generation) */ 2536 #define DFT_MBIST2_C_NUM 1u 2537 /* local parameter in mxdft_mmio.v (here only used for header file generation) */ 2538 #define DFT_MBIST3_C_NUM 1u 2539 /* local parameter in mxdft_mmio.v (here only used for header file generation) */ 2540 #define DFT_DIRECT_MBIST0_CTRL_NUM 1u 2541 /* local parameter in mxdft_mmio.v (here only used for header file generation) */ 2542 #define DFT_DIRECT_MBIST1_CTRL_NUM 1u 2543 /* local parameter in mxdft_mmio.v (here only used for header file generation) */ 2544 #define DFT_DIRECT_MBIST2_CTRL_NUM 1u 2545 /* local parameter in mxdft_mmio.v (here only used for header file generation) */ 2546 #define DFT_DIRECT_MBIST3_CTRL_NUM 1u 2547 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ 2548 #define EFUSE_EFUSE_NR 4u 2549 /* AXI Master present ([0,1]): 0 - AHB master interface is present 1 - AXI master 2550 interface is present. */ 2551 #define ETH_AXI_MASTER_PRESENT 1u 2552 /* TX Packet Buffer Size (jumbo frame size is 1.5KB): 00: 16KB to support four 2553 queues with capacity for two jumbo frames; 01: 8KB to support two queues with 2554 capacity for two jumbo frames or four queues with capacity for one jumbo 2555 frame; 10: 4KB to support one queue with capacity for two jumbo frames or two 2556 queues with capacity for one jumbo frame; 11: 2KB to support one queue with 2557 capacity for one jumbo frame; */ 2558 #define ETH_TX_PACKET_BUFFER_SIZE 1u 2559 /* RX Packet Buffer Size (jumbo frame size is 1.5KB): 00: 4KB to support capacity 2560 for two jumbo frames; 01: 2KB to support capacity for one jumbo frames; */ 2561 #define ETH_RX_PACKET_BUFFER_SIZE 0u 2562 /* Selects the clock source to use for the tsu_clk. A value of 0=Internal PCLK, , 2563 1=clk_hf */ 2564 #define ETH_TSU_CLK_SOURCE 1u 2565 /* This parameter is used to specify if mxeth should contain a clock divider. The 2566 clock divider is useful for chips where multiple mxeth are instantiated as it 2567 allows a single source PLL to be used 0=No Divider, ref_clk_int_in is used as 2568 is 1=Divider instantiated, ref_clk_int_in should be 125MHz */ 2569 #define ETH_SRC_CLOCK_DIVIDER 1u 2570 /* Number of Priority Queues. */ 2571 #define ETH_ETH_NPQ 3u 2572 /* Set to 1 if IP will instantiate spares (0=None, 1=Max, 2=Min) */ 2573 #define ETH_SPARE_EN 2u 2574 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2575 #define ETH_MASTER_WIDTH 8u 2576 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 2577 #define ETH_PLATFORM_VARIANT 2u 2578 /* RAM vendor (0=CYP, 1=SNPS, 2=ARM) */ 2579 #define ETH_RAM_VEND 2u 2580 /* Width of external AXI master ID signals. Legal range [3,8] */ 2581 #define ETH_AXIM_ID_WIDTH 4u 2582 /* RMII internal clock mode support */ 2583 #define ETH_CHIP_TOP_MXETH_RMII_INT_MODE_EN 1u 2584 /* RGMII internal clock mode support */ 2585 #define ETH_CHIP_TOP_MXETH_RGMII_INT_MODE_EN 0u 2586 /* Number of comparator structures ([1, 32]) */ 2587 #define EVTGEN_COMP_STRUCT_NR 16u 2588 /* Number of GPIO ports in range 0..31 */ 2589 #define IOSS_GPIO_GPIO_PORT_NR_0_31 31u 2590 /* Number of GPIO ports in range 32..63 */ 2591 #define IOSS_GPIO_GPIO_PORT_NR_32_63 0u 2592 /* Number of GPIO ports in range 64..95 */ 2593 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 2594 /* Number of GPIO ports in range 96..127 */ 2595 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 2596 /* Number of GPIO ports in device */ 2597 #define IOSS_GPIO_GPIO_PORT_NR 31u 2598 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2599 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 2600 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2601 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 2602 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2603 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 1u 2604 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2605 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DS_CTRL 0u 2606 /* Indicates port supports slew extension bits */ 2607 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLEW_EXT 0u 2608 /* Indicates port supports drive select extension bits */ 2609 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DRIVE_EXT 0u 2610 /* Indicates slew bit width */ 2611 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLEW_WIDTH 0u 2612 /* Indicates drive sel bit width */ 2613 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DRIVE_WIDTH 0u 2614 /* Indicates that pin #0 exists for this port with slew control feature */ 2615 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u 2616 /* Indicates that pin #1 exists for this port with slew control feature */ 2617 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u 2618 /* Indicates that pin #2 exists for this port with slew control feature */ 2619 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u 2620 /* Indicates that pin #3 exists for this port with slew control feature */ 2621 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u 2622 /* Indicates that pin #4 exists for this port with slew control feature */ 2623 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 1u 2624 /* Indicates that pin #5 exists for this port with slew control feature */ 2625 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 1u 2626 /* Indicates that pin #6 exists for this port with slew control feature */ 2627 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 2628 /* Indicates that pin #7 exists for this port with slew control feature */ 2629 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 2630 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2631 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 2632 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2633 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 2634 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2635 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 1u 2636 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2637 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DS_CTRL 0u 2638 /* Indicates port supports slew extension bits */ 2639 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLEW_EXT 0u 2640 /* Indicates port supports drive select extension bits */ 2641 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DRIVE_EXT 0u 2642 /* Indicates slew bit width */ 2643 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLEW_WIDTH 0u 2644 /* Indicates drive sel bit width */ 2645 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DRIVE_WIDTH 0u 2646 /* Indicates that pin #0 exists for this port with slew control feature */ 2647 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 0u 2648 /* Indicates that pin #1 exists for this port with slew control feature */ 2649 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 0u 2650 /* Indicates that pin #2 exists for this port with slew control feature */ 2651 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u 2652 /* Indicates that pin #3 exists for this port with slew control feature */ 2653 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 2654 /* Indicates that pin #4 exists for this port with slew control feature */ 2655 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 2656 /* Indicates that pin #5 exists for this port with slew control feature */ 2657 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 2658 /* Indicates that pin #6 exists for this port with slew control feature */ 2659 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 2660 /* Indicates that pin #7 exists for this port with slew control feature */ 2661 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 2662 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2663 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 2664 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2665 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 2666 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2667 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 1u 2668 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2669 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DS_CTRL 0u 2670 /* Indicates port supports slew extension bits */ 2671 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLEW_EXT 0u 2672 /* Indicates port supports drive select extension bits */ 2673 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DRIVE_EXT 0u 2674 /* Indicates slew bit width */ 2675 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLEW_WIDTH 0u 2676 /* Indicates drive sel bit width */ 2677 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DRIVE_WIDTH 0u 2678 /* Indicates that pin #0 exists for this port with slew control feature */ 2679 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 0u 2680 /* Indicates that pin #1 exists for this port with slew control feature */ 2681 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 0u 2682 /* Indicates that pin #2 exists for this port with slew control feature */ 2683 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 0u 2684 /* Indicates that pin #3 exists for this port with slew control feature */ 2685 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 0u 2686 /* Indicates that pin #4 exists for this port with slew control feature */ 2687 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 0u 2688 /* Indicates that pin #5 exists for this port with slew control feature */ 2689 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 0u 2690 /* Indicates that pin #6 exists for this port with slew control feature */ 2691 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 0u 2692 /* Indicates that pin #7 exists for this port with slew control feature */ 2693 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 0u 2694 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2695 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 2696 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2697 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 2698 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2699 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 1u 2700 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2701 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DS_CTRL 0u 2702 /* Indicates port supports slew extension bits */ 2703 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLEW_EXT 0u 2704 /* Indicates port supports drive select extension bits */ 2705 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DRIVE_EXT 0u 2706 /* Indicates slew bit width */ 2707 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLEW_WIDTH 0u 2708 /* Indicates drive sel bit width */ 2709 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DRIVE_WIDTH 0u 2710 /* Indicates that pin #0 exists for this port with slew control feature */ 2711 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 0u 2712 /* Indicates that pin #1 exists for this port with slew control feature */ 2713 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 0u 2714 /* Indicates that pin #2 exists for this port with slew control feature */ 2715 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 2716 /* Indicates that pin #3 exists for this port with slew control feature */ 2717 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 2718 /* Indicates that pin #4 exists for this port with slew control feature */ 2719 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 2720 /* Indicates that pin #5 exists for this port with slew control feature */ 2721 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 2722 /* Indicates that pin #6 exists for this port with slew control feature */ 2723 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 2724 /* Indicates that pin #7 exists for this port with slew control feature */ 2725 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 2726 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2727 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 1u 2728 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2729 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 2730 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2731 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 1u 2732 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2733 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DS_CTRL 0u 2734 /* Indicates port supports slew extension bits */ 2735 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLEW_EXT 0u 2736 /* Indicates port supports drive select extension bits */ 2737 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DRIVE_EXT 0u 2738 /* Indicates slew bit width */ 2739 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLEW_WIDTH 0u 2740 /* Indicates drive sel bit width */ 2741 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DRIVE_WIDTH 0u 2742 /* Indicates that pin #0 exists for this port with slew control feature */ 2743 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u 2744 /* Indicates that pin #1 exists for this port with slew control feature */ 2745 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u 2746 /* Indicates that pin #2 exists for this port with slew control feature */ 2747 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 2748 /* Indicates that pin #3 exists for this port with slew control feature */ 2749 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 2750 /* Indicates that pin #4 exists for this port with slew control feature */ 2751 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 2752 /* Indicates that pin #5 exists for this port with slew control feature */ 2753 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 2754 /* Indicates that pin #6 exists for this port with slew control feature */ 2755 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 2756 /* Indicates that pin #7 exists for this port with slew control feature */ 2757 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 2758 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2759 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 2760 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2761 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 2762 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2763 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 1u 2764 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2765 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DS_CTRL 0u 2766 /* Indicates port supports slew extension bits */ 2767 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLEW_EXT 0u 2768 /* Indicates port supports drive select extension bits */ 2769 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DRIVE_EXT 0u 2770 /* Indicates slew bit width */ 2771 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLEW_WIDTH 0u 2772 /* Indicates drive sel bit width */ 2773 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DRIVE_WIDTH 0u 2774 /* Indicates that pin #0 exists for this port with slew control feature */ 2775 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 0u 2776 /* Indicates that pin #1 exists for this port with slew control feature */ 2777 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 0u 2778 /* Indicates that pin #2 exists for this port with slew control feature */ 2779 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u 2780 /* Indicates that pin #3 exists for this port with slew control feature */ 2781 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 2782 /* Indicates that pin #4 exists for this port with slew control feature */ 2783 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 2784 /* Indicates that pin #5 exists for this port with slew control feature */ 2785 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 2786 /* Indicates that pin #6 exists for this port with slew control feature */ 2787 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 0u 2788 /* Indicates that pin #7 exists for this port with slew control feature */ 2789 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 0u 2790 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2791 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u 2792 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2793 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u 2794 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2795 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 1u 2796 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2797 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_DS_CTRL 0u 2798 /* Indicates port supports slew extension bits */ 2799 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLEW_EXT 0u 2800 /* Indicates port supports drive select extension bits */ 2801 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_DRIVE_EXT 0u 2802 /* Indicates slew bit width */ 2803 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLEW_WIDTH 0u 2804 /* Indicates drive sel bit width */ 2805 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_DRIVE_WIDTH 0u 2806 /* Indicates that pin #0 exists for this port with slew control feature */ 2807 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 0u 2808 /* Indicates that pin #1 exists for this port with slew control feature */ 2809 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 0u 2810 /* Indicates that pin #2 exists for this port with slew control feature */ 2811 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 0u 2812 /* Indicates that pin #3 exists for this port with slew control feature */ 2813 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 0u 2814 /* Indicates that pin #4 exists for this port with slew control feature */ 2815 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 0u 2816 /* Indicates that pin #5 exists for this port with slew control feature */ 2817 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 0u 2818 /* Indicates that pin #6 exists for this port with slew control feature */ 2819 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 0u 2820 /* Indicates that pin #7 exists for this port with slew control feature */ 2821 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 0u 2822 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2823 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u 2824 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2825 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u 2826 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2827 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 1u 2828 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2829 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_DS_CTRL 0u 2830 /* Indicates port supports slew extension bits */ 2831 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLEW_EXT 0u 2832 /* Indicates port supports drive select extension bits */ 2833 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_DRIVE_EXT 0u 2834 /* Indicates slew bit width */ 2835 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLEW_WIDTH 0u 2836 /* Indicates drive sel bit width */ 2837 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_DRIVE_WIDTH 0u 2838 /* Indicates that pin #0 exists for this port with slew control feature */ 2839 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 0u 2840 /* Indicates that pin #1 exists for this port with slew control feature */ 2841 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 0u 2842 /* Indicates that pin #2 exists for this port with slew control feature */ 2843 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 0u 2844 /* Indicates that pin #3 exists for this port with slew control feature */ 2845 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 0u 2846 /* Indicates that pin #4 exists for this port with slew control feature */ 2847 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 0u 2848 /* Indicates that pin #5 exists for this port with slew control feature */ 2849 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 0u 2850 /* Indicates that pin #6 exists for this port with slew control feature */ 2851 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 0u 2852 /* Indicates that pin #7 exists for this port with slew control feature */ 2853 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 0u 2854 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2855 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u 2856 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2857 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u 2858 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2859 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 1u 2860 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2861 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_DS_CTRL 0u 2862 /* Indicates port supports slew extension bits */ 2863 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLEW_EXT 0u 2864 /* Indicates port supports drive select extension bits */ 2865 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_DRIVE_EXT 0u 2866 /* Indicates slew bit width */ 2867 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLEW_WIDTH 0u 2868 /* Indicates drive sel bit width */ 2869 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_DRIVE_WIDTH 0u 2870 /* Indicates that pin #0 exists for this port with slew control feature */ 2871 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 0u 2872 /* Indicates that pin #1 exists for this port with slew control feature */ 2873 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 0u 2874 /* Indicates that pin #2 exists for this port with slew control feature */ 2875 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u 2876 /* Indicates that pin #3 exists for this port with slew control feature */ 2877 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u 2878 /* Indicates that pin #4 exists for this port with slew control feature */ 2879 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u 2880 /* Indicates that pin #5 exists for this port with slew control feature */ 2881 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u 2882 /* Indicates that pin #6 exists for this port with slew control feature */ 2883 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u 2884 /* Indicates that pin #7 exists for this port with slew control feature */ 2885 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u 2886 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2887 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u 2888 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2889 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u 2890 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2891 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 1u 2892 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2893 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_DS_CTRL 0u 2894 /* Indicates port supports slew extension bits */ 2895 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLEW_EXT 0u 2896 /* Indicates port supports drive select extension bits */ 2897 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_DRIVE_EXT 0u 2898 /* Indicates slew bit width */ 2899 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLEW_WIDTH 0u 2900 /* Indicates drive sel bit width */ 2901 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_DRIVE_WIDTH 0u 2902 /* Indicates that pin #0 exists for this port with slew control feature */ 2903 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 1u 2904 /* Indicates that pin #1 exists for this port with slew control feature */ 2905 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 1u 2906 /* Indicates that pin #2 exists for this port with slew control feature */ 2907 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 1u 2908 /* Indicates that pin #3 exists for this port with slew control feature */ 2909 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 1u 2910 /* Indicates that pin #4 exists for this port with slew control feature */ 2911 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 1u 2912 /* Indicates that pin #5 exists for this port with slew control feature */ 2913 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 1u 2914 /* Indicates that pin #6 exists for this port with slew control feature */ 2915 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 1u 2916 /* Indicates that pin #7 exists for this port with slew control feature */ 2917 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 1u 2918 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2919 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u 2920 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2921 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u 2922 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2923 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 1u 2924 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2925 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_DS_CTRL 0u 2926 /* Indicates port supports slew extension bits */ 2927 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLEW_EXT 0u 2928 /* Indicates port supports drive select extension bits */ 2929 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_DRIVE_EXT 0u 2930 /* Indicates slew bit width */ 2931 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLEW_WIDTH 0u 2932 /* Indicates drive sel bit width */ 2933 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_DRIVE_WIDTH 0u 2934 /* Indicates that pin #0 exists for this port with slew control feature */ 2935 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 1u 2936 /* Indicates that pin #1 exists for this port with slew control feature */ 2937 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 1u 2938 /* Indicates that pin #2 exists for this port with slew control feature */ 2939 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 0u 2940 /* Indicates that pin #3 exists for this port with slew control feature */ 2941 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 0u 2942 /* Indicates that pin #4 exists for this port with slew control feature */ 2943 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 0u 2944 /* Indicates that pin #5 exists for this port with slew control feature */ 2945 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 0u 2946 /* Indicates that pin #6 exists for this port with slew control feature */ 2947 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 0u 2948 /* Indicates that pin #7 exists for this port with slew control feature */ 2949 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 0u 2950 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2951 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u 2952 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2953 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u 2954 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2955 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 1u 2956 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2957 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_DS_CTRL 0u 2958 /* Indicates port supports slew extension bits */ 2959 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLEW_EXT 0u 2960 /* Indicates port supports drive select extension bits */ 2961 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_DRIVE_EXT 0u 2962 /* Indicates slew bit width */ 2963 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLEW_WIDTH 0u 2964 /* Indicates drive sel bit width */ 2965 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_DRIVE_WIDTH 0u 2966 /* Indicates that pin #0 exists for this port with slew control feature */ 2967 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 1u 2968 /* Indicates that pin #1 exists for this port with slew control feature */ 2969 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 1u 2970 /* Indicates that pin #2 exists for this port with slew control feature */ 2971 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 1u 2972 /* Indicates that pin #3 exists for this port with slew control feature */ 2973 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 1u 2974 /* Indicates that pin #4 exists for this port with slew control feature */ 2975 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 1u 2976 /* Indicates that pin #5 exists for this port with slew control feature */ 2977 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 1u 2978 /* Indicates that pin #6 exists for this port with slew control feature */ 2979 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 1u 2980 /* Indicates that pin #7 exists for this port with slew control feature */ 2981 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 1u 2982 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2983 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u 2984 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2985 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u 2986 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2987 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 1u 2988 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 2989 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_DS_CTRL 0u 2990 /* Indicates port supports slew extension bits */ 2991 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLEW_EXT 0u 2992 /* Indicates port supports drive select extension bits */ 2993 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_DRIVE_EXT 0u 2994 /* Indicates slew bit width */ 2995 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLEW_WIDTH 0u 2996 /* Indicates drive sel bit width */ 2997 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_DRIVE_WIDTH 0u 2998 /* Indicates that pin #0 exists for this port with slew control feature */ 2999 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 1u 3000 /* Indicates that pin #1 exists for this port with slew control feature */ 3001 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 1u 3002 /* Indicates that pin #2 exists for this port with slew control feature */ 3003 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 1u 3004 /* Indicates that pin #3 exists for this port with slew control feature */ 3005 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 1u 3006 /* Indicates that pin #4 exists for this port with slew control feature */ 3007 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 1u 3008 /* Indicates that pin #5 exists for this port with slew control feature */ 3009 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 1u 3010 /* Indicates that pin #6 exists for this port with slew control feature */ 3011 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 1u 3012 /* Indicates that pin #7 exists for this port with slew control feature */ 3013 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 1u 3014 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3015 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 1u 3016 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3017 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u 3018 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3019 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 1u 3020 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3021 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_DS_CTRL 0u 3022 /* Indicates port supports slew extension bits */ 3023 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLEW_EXT 0u 3024 /* Indicates port supports drive select extension bits */ 3025 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_DRIVE_EXT 0u 3026 /* Indicates slew bit width */ 3027 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLEW_WIDTH 0u 3028 /* Indicates drive sel bit width */ 3029 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_DRIVE_WIDTH 0u 3030 /* Indicates that pin #0 exists for this port with slew control feature */ 3031 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u 3032 /* Indicates that pin #1 exists for this port with slew control feature */ 3033 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u 3034 /* Indicates that pin #2 exists for this port with slew control feature */ 3035 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u 3036 /* Indicates that pin #3 exists for this port with slew control feature */ 3037 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u 3038 /* Indicates that pin #4 exists for this port with slew control feature */ 3039 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u 3040 /* Indicates that pin #5 exists for this port with slew control feature */ 3041 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u 3042 /* Indicates that pin #6 exists for this port with slew control feature */ 3043 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u 3044 /* Indicates that pin #7 exists for this port with slew control feature */ 3045 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u 3046 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3047 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 1u 3048 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3049 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u 3050 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3051 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 1u 3052 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3053 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_DS_CTRL 0u 3054 /* Indicates port supports slew extension bits */ 3055 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLEW_EXT 0u 3056 /* Indicates port supports drive select extension bits */ 3057 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_DRIVE_EXT 0u 3058 /* Indicates slew bit width */ 3059 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLEW_WIDTH 0u 3060 /* Indicates drive sel bit width */ 3061 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_DRIVE_WIDTH 0u 3062 /* Indicates that pin #0 exists for this port with slew control feature */ 3063 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 0u 3064 /* Indicates that pin #1 exists for this port with slew control feature */ 3065 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 0u 3066 /* Indicates that pin #2 exists for this port with slew control feature */ 3067 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u 3068 /* Indicates that pin #3 exists for this port with slew control feature */ 3069 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u 3070 /* Indicates that pin #4 exists for this port with slew control feature */ 3071 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u 3072 /* Indicates that pin #5 exists for this port with slew control feature */ 3073 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u 3074 /* Indicates that pin #6 exists for this port with slew control feature */ 3075 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u 3076 /* Indicates that pin #7 exists for this port with slew control feature */ 3077 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u 3078 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3079 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_GPIO 1u 3080 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3081 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SIO 0u 3082 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3083 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_AUTOLVL 1u 3084 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3085 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_DS_CTRL 0u 3086 /* Indicates port supports slew extension bits */ 3087 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLEW_EXT 1u 3088 /* Indicates port supports drive select extension bits */ 3089 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_DRIVE_EXT 1u 3090 /* Indicates slew bit width */ 3091 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLEW_WIDTH 1u 3092 /* Indicates drive sel bit width */ 3093 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_DRIVE_WIDTH 3u 3094 /* Indicates that pin #0 exists for this port with slew control feature */ 3095 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO0 0u 3096 /* Indicates that pin #1 exists for this port with slew control feature */ 3097 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO1 0u 3098 /* Indicates that pin #2 exists for this port with slew control feature */ 3099 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO2 0u 3100 /* Indicates that pin #3 exists for this port with slew control feature */ 3101 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO3 0u 3102 /* Indicates that pin #4 exists for this port with slew control feature */ 3103 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO4 0u 3104 /* Indicates that pin #5 exists for this port with slew control feature */ 3105 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO5 0u 3106 /* Indicates that pin #6 exists for this port with slew control feature */ 3107 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO6 0u 3108 /* Indicates that pin #7 exists for this port with slew control feature */ 3109 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO7 0u 3110 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3111 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_GPIO 1u 3112 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3113 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SIO 0u 3114 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3115 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_AUTOLVL 1u 3116 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3117 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_DS_CTRL 0u 3118 /* Indicates port supports slew extension bits */ 3119 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLEW_EXT 1u 3120 /* Indicates port supports drive select extension bits */ 3121 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_DRIVE_EXT 1u 3122 /* Indicates slew bit width */ 3123 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLEW_WIDTH 1u 3124 /* Indicates drive sel bit width */ 3125 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_DRIVE_WIDTH 3u 3126 /* Indicates that pin #0 exists for this port with slew control feature */ 3127 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO0 0u 3128 /* Indicates that pin #1 exists for this port with slew control feature */ 3129 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO1 0u 3130 /* Indicates that pin #2 exists for this port with slew control feature */ 3131 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO2 0u 3132 /* Indicates that pin #3 exists for this port with slew control feature */ 3133 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO3 0u 3134 /* Indicates that pin #4 exists for this port with slew control feature */ 3135 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO4 0u 3136 /* Indicates that pin #5 exists for this port with slew control feature */ 3137 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO5 0u 3138 /* Indicates that pin #6 exists for this port with slew control feature */ 3139 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO6 0u 3140 /* Indicates that pin #7 exists for this port with slew control feature */ 3141 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO7 0u 3142 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3143 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_GPIO 1u 3144 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3145 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SIO 0u 3146 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3147 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_AUTOLVL 1u 3148 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3149 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_DS_CTRL 0u 3150 /* Indicates port supports slew extension bits */ 3151 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLEW_EXT 1u 3152 /* Indicates port supports drive select extension bits */ 3153 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_DRIVE_EXT 1u 3154 /* Indicates slew bit width */ 3155 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLEW_WIDTH 1u 3156 /* Indicates drive sel bit width */ 3157 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_DRIVE_WIDTH 3u 3158 /* Indicates that pin #0 exists for this port with slew control feature */ 3159 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO0 0u 3160 /* Indicates that pin #1 exists for this port with slew control feature */ 3161 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO1 0u 3162 /* Indicates that pin #2 exists for this port with slew control feature */ 3163 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO2 0u 3164 /* Indicates that pin #3 exists for this port with slew control feature */ 3165 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO3 0u 3166 /* Indicates that pin #4 exists for this port with slew control feature */ 3167 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO4 0u 3168 /* Indicates that pin #5 exists for this port with slew control feature */ 3169 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO5 0u 3170 /* Indicates that pin #6 exists for this port with slew control feature */ 3171 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO6 0u 3172 /* Indicates that pin #7 exists for this port with slew control feature */ 3173 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO7 0u 3174 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3175 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_GPIO 1u 3176 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3177 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SIO 0u 3178 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3179 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_AUTOLVL 1u 3180 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3181 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_DS_CTRL 0u 3182 /* Indicates port supports slew extension bits */ 3183 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLEW_EXT 1u 3184 /* Indicates port supports drive select extension bits */ 3185 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_DRIVE_EXT 1u 3186 /* Indicates slew bit width */ 3187 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLEW_WIDTH 1u 3188 /* Indicates drive sel bit width */ 3189 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_DRIVE_WIDTH 3u 3190 /* Indicates that pin #0 exists for this port with slew control feature */ 3191 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO0 0u 3192 /* Indicates that pin #1 exists for this port with slew control feature */ 3193 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO1 0u 3194 /* Indicates that pin #2 exists for this port with slew control feature */ 3195 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO2 0u 3196 /* Indicates that pin #3 exists for this port with slew control feature */ 3197 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO3 0u 3198 /* Indicates that pin #4 exists for this port with slew control feature */ 3199 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO4 0u 3200 /* Indicates that pin #5 exists for this port with slew control feature */ 3201 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO5 0u 3202 /* Indicates that pin #6 exists for this port with slew control feature */ 3203 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO6 0u 3204 /* Indicates that pin #7 exists for this port with slew control feature */ 3205 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO7 0u 3206 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3207 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_GPIO 1u 3208 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3209 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SIO 0u 3210 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3211 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_AUTOLVL 1u 3212 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3213 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_DS_CTRL 0u 3214 /* Indicates port supports slew extension bits */ 3215 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLEW_EXT 1u 3216 /* Indicates port supports drive select extension bits */ 3217 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_DRIVE_EXT 1u 3218 /* Indicates slew bit width */ 3219 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLEW_WIDTH 1u 3220 /* Indicates drive sel bit width */ 3221 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_DRIVE_WIDTH 3u 3222 /* Indicates that pin #0 exists for this port with slew control feature */ 3223 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO0 0u 3224 /* Indicates that pin #1 exists for this port with slew control feature */ 3225 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO1 0u 3226 /* Indicates that pin #2 exists for this port with slew control feature */ 3227 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO2 0u 3228 /* Indicates that pin #3 exists for this port with slew control feature */ 3229 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO3 0u 3230 /* Indicates that pin #4 exists for this port with slew control feature */ 3231 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO4 0u 3232 /* Indicates that pin #5 exists for this port with slew control feature */ 3233 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO5 0u 3234 /* Indicates that pin #6 exists for this port with slew control feature */ 3235 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO6 0u 3236 /* Indicates that pin #7 exists for this port with slew control feature */ 3237 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO7 0u 3238 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3239 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_GPIO 1u 3240 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3241 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SIO 0u 3242 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3243 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_AUTOLVL 1u 3244 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3245 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_DS_CTRL 0u 3246 /* Indicates port supports slew extension bits */ 3247 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLEW_EXT 1u 3248 /* Indicates port supports drive select extension bits */ 3249 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_DRIVE_EXT 1u 3250 /* Indicates slew bit width */ 3251 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLEW_WIDTH 1u 3252 /* Indicates drive sel bit width */ 3253 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_DRIVE_WIDTH 3u 3254 /* Indicates that pin #0 exists for this port with slew control feature */ 3255 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO0 0u 3256 /* Indicates that pin #1 exists for this port with slew control feature */ 3257 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO1 0u 3258 /* Indicates that pin #2 exists for this port with slew control feature */ 3259 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO2 0u 3260 /* Indicates that pin #3 exists for this port with slew control feature */ 3261 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO3 0u 3262 /* Indicates that pin #4 exists for this port with slew control feature */ 3263 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO4 0u 3264 /* Indicates that pin #5 exists for this port with slew control feature */ 3265 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO5 0u 3266 /* Indicates that pin #6 exists for this port with slew control feature */ 3267 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO6 0u 3268 /* Indicates that pin #7 exists for this port with slew control feature */ 3269 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO7 0u 3270 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3271 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_GPIO 1u 3272 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3273 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SIO 0u 3274 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3275 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_AUTOLVL 1u 3276 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3277 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_DS_CTRL 0u 3278 /* Indicates port supports slew extension bits */ 3279 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLEW_EXT 1u 3280 /* Indicates port supports drive select extension bits */ 3281 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_DRIVE_EXT 1u 3282 /* Indicates slew bit width */ 3283 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLEW_WIDTH 1u 3284 /* Indicates drive sel bit width */ 3285 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_DRIVE_WIDTH 3u 3286 /* Indicates that pin #0 exists for this port with slew control feature */ 3287 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO0 0u 3288 /* Indicates that pin #1 exists for this port with slew control feature */ 3289 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO1 0u 3290 /* Indicates that pin #2 exists for this port with slew control feature */ 3291 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO2 0u 3292 /* Indicates that pin #3 exists for this port with slew control feature */ 3293 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO3 0u 3294 /* Indicates that pin #4 exists for this port with slew control feature */ 3295 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO4 0u 3296 /* Indicates that pin #5 exists for this port with slew control feature */ 3297 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO5 0u 3298 /* Indicates that pin #6 exists for this port with slew control feature */ 3299 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO6 0u 3300 /* Indicates that pin #7 exists for this port with slew control feature */ 3301 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO7 0u 3302 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3303 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_GPIO 1u 3304 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3305 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SIO 0u 3306 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3307 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_AUTOLVL 1u 3308 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3309 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_DS_CTRL 0u 3310 /* Indicates port supports slew extension bits */ 3311 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLEW_EXT 1u 3312 /* Indicates port supports drive select extension bits */ 3313 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_DRIVE_EXT 1u 3314 /* Indicates slew bit width */ 3315 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLEW_WIDTH 1u 3316 /* Indicates drive sel bit width */ 3317 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_DRIVE_WIDTH 3u 3318 /* Indicates that pin #0 exists for this port with slew control feature */ 3319 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO0 0u 3320 /* Indicates that pin #1 exists for this port with slew control feature */ 3321 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO1 0u 3322 /* Indicates that pin #2 exists for this port with slew control feature */ 3323 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO2 0u 3324 /* Indicates that pin #3 exists for this port with slew control feature */ 3325 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO3 0u 3326 /* Indicates that pin #4 exists for this port with slew control feature */ 3327 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO4 0u 3328 /* Indicates that pin #5 exists for this port with slew control feature */ 3329 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO5 0u 3330 /* Indicates that pin #6 exists for this port with slew control feature */ 3331 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO6 0u 3332 /* Indicates that pin #7 exists for this port with slew control feature */ 3333 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO7 0u 3334 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3335 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_GPIO 1u 3336 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3337 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SIO 0u 3338 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3339 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_AUTOLVL 1u 3340 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3341 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_DS_CTRL 1u 3342 /* Indicates port supports slew extension bits */ 3343 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLEW_EXT 1u 3344 /* Indicates port supports drive select extension bits */ 3345 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_DRIVE_EXT 0u 3346 /* Indicates slew bit width */ 3347 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLEW_WIDTH 1u 3348 /* Indicates drive sel bit width */ 3349 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_DRIVE_WIDTH 0u 3350 /* Indicates that pin #0 exists for this port with slew control feature */ 3351 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO0 0u 3352 /* Indicates that pin #1 exists for this port with slew control feature */ 3353 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO1 0u 3354 /* Indicates that pin #2 exists for this port with slew control feature */ 3355 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO2 0u 3356 /* Indicates that pin #3 exists for this port with slew control feature */ 3357 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO3 0u 3358 /* Indicates that pin #4 exists for this port with slew control feature */ 3359 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO4 0u 3360 /* Indicates that pin #5 exists for this port with slew control feature */ 3361 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO5 0u 3362 /* Indicates that pin #6 exists for this port with slew control feature */ 3363 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO6 0u 3364 /* Indicates that pin #7 exists for this port with slew control feature */ 3365 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO7 0u 3366 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3367 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_GPIO 1u 3368 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3369 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SIO 0u 3370 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3371 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_AUTOLVL 1u 3372 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3373 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_DS_CTRL 1u 3374 /* Indicates port supports slew extension bits */ 3375 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLEW_EXT 1u 3376 /* Indicates port supports drive select extension bits */ 3377 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_DRIVE_EXT 0u 3378 /* Indicates slew bit width */ 3379 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLEW_WIDTH 1u 3380 /* Indicates drive sel bit width */ 3381 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_DRIVE_WIDTH 0u 3382 /* Indicates that pin #0 exists for this port with slew control feature */ 3383 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO0 0u 3384 /* Indicates that pin #1 exists for this port with slew control feature */ 3385 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO1 0u 3386 /* Indicates that pin #2 exists for this port with slew control feature */ 3387 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO2 0u 3388 /* Indicates that pin #3 exists for this port with slew control feature */ 3389 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO3 0u 3390 /* Indicates that pin #4 exists for this port with slew control feature */ 3391 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO4 0u 3392 /* Indicates that pin #5 exists for this port with slew control feature */ 3393 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO5 0u 3394 /* Indicates that pin #6 exists for this port with slew control feature */ 3395 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO6 0u 3396 /* Indicates that pin #7 exists for this port with slew control feature */ 3397 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO7 0u 3398 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3399 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_GPIO 1u 3400 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3401 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SIO 0u 3402 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3403 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_AUTOLVL 1u 3404 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3405 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_DS_CTRL 1u 3406 /* Indicates port supports slew extension bits */ 3407 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLEW_EXT 1u 3408 /* Indicates port supports drive select extension bits */ 3409 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_DRIVE_EXT 0u 3410 /* Indicates slew bit width */ 3411 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLEW_WIDTH 1u 3412 /* Indicates drive sel bit width */ 3413 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_DRIVE_WIDTH 0u 3414 /* Indicates that pin #0 exists for this port with slew control feature */ 3415 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO0 0u 3416 /* Indicates that pin #1 exists for this port with slew control feature */ 3417 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO1 0u 3418 /* Indicates that pin #2 exists for this port with slew control feature */ 3419 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO2 0u 3420 /* Indicates that pin #3 exists for this port with slew control feature */ 3421 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO3 0u 3422 /* Indicates that pin #4 exists for this port with slew control feature */ 3423 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO4 0u 3424 /* Indicates that pin #5 exists for this port with slew control feature */ 3425 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO5 0u 3426 /* Indicates that pin #6 exists for this port with slew control feature */ 3427 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO6 0u 3428 /* Indicates that pin #7 exists for this port with slew control feature */ 3429 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO7 0u 3430 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3431 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_GPIO 1u 3432 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3433 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SIO 0u 3434 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3435 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_AUTOLVL 1u 3436 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3437 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_DS_CTRL 1u 3438 /* Indicates port supports slew extension bits */ 3439 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLEW_EXT 1u 3440 /* Indicates port supports drive select extension bits */ 3441 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_DRIVE_EXT 0u 3442 /* Indicates slew bit width */ 3443 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLEW_WIDTH 1u 3444 /* Indicates drive sel bit width */ 3445 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_DRIVE_WIDTH 0u 3446 /* Indicates that pin #0 exists for this port with slew control feature */ 3447 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO0 0u 3448 /* Indicates that pin #1 exists for this port with slew control feature */ 3449 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO1 0u 3450 /* Indicates that pin #2 exists for this port with slew control feature */ 3451 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO2 0u 3452 /* Indicates that pin #3 exists for this port with slew control feature */ 3453 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO3 0u 3454 /* Indicates that pin #4 exists for this port with slew control feature */ 3455 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO4 0u 3456 /* Indicates that pin #5 exists for this port with slew control feature */ 3457 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO5 0u 3458 /* Indicates that pin #6 exists for this port with slew control feature */ 3459 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO6 0u 3460 /* Indicates that pin #7 exists for this port with slew control feature */ 3461 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO7 0u 3462 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3463 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_GPIO 1u 3464 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3465 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SIO 0u 3466 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3467 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_AUTOLVL 1u 3468 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3469 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_DS_CTRL 1u 3470 /* Indicates port supports slew extension bits */ 3471 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLEW_EXT 1u 3472 /* Indicates port supports drive select extension bits */ 3473 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_DRIVE_EXT 0u 3474 /* Indicates slew bit width */ 3475 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLEW_WIDTH 1u 3476 /* Indicates drive sel bit width */ 3477 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_DRIVE_WIDTH 0u 3478 /* Indicates that pin #0 exists for this port with slew control feature */ 3479 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO0 0u 3480 /* Indicates that pin #1 exists for this port with slew control feature */ 3481 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO1 0u 3482 /* Indicates that pin #2 exists for this port with slew control feature */ 3483 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO2 0u 3484 /* Indicates that pin #3 exists for this port with slew control feature */ 3485 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO3 0u 3486 /* Indicates that pin #4 exists for this port with slew control feature */ 3487 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO4 0u 3488 /* Indicates that pin #5 exists for this port with slew control feature */ 3489 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO5 0u 3490 /* Indicates that pin #6 exists for this port with slew control feature */ 3491 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO6 0u 3492 /* Indicates that pin #7 exists for this port with slew control feature */ 3493 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO7 0u 3494 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3495 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_GPIO 1u 3496 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3497 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SIO 0u 3498 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3499 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_AUTOLVL 1u 3500 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3501 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_DS_CTRL 1u 3502 /* Indicates port supports slew extension bits */ 3503 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLEW_EXT 1u 3504 /* Indicates port supports drive select extension bits */ 3505 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_DRIVE_EXT 0u 3506 /* Indicates slew bit width */ 3507 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLEW_WIDTH 1u 3508 /* Indicates drive sel bit width */ 3509 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_DRIVE_WIDTH 0u 3510 /* Indicates that pin #0 exists for this port with slew control feature */ 3511 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO0 0u 3512 /* Indicates that pin #1 exists for this port with slew control feature */ 3513 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO1 0u 3514 /* Indicates that pin #2 exists for this port with slew control feature */ 3515 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO2 0u 3516 /* Indicates that pin #3 exists for this port with slew control feature */ 3517 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO3 0u 3518 /* Indicates that pin #4 exists for this port with slew control feature */ 3519 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO4 0u 3520 /* Indicates that pin #5 exists for this port with slew control feature */ 3521 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO5 0u 3522 /* Indicates that pin #6 exists for this port with slew control feature */ 3523 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO6 0u 3524 /* Indicates that pin #7 exists for this port with slew control feature */ 3525 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO7 0u 3526 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3527 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_GPIO 1u 3528 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3529 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SIO 0u 3530 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3531 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_AUTOLVL 1u 3532 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3533 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_DS_CTRL 0u 3534 /* Indicates port supports slew extension bits */ 3535 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLEW_EXT 0u 3536 /* Indicates port supports drive select extension bits */ 3537 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_DRIVE_EXT 0u 3538 /* Indicates slew bit width */ 3539 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLEW_WIDTH 0u 3540 /* Indicates drive sel bit width */ 3541 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_DRIVE_WIDTH 0u 3542 /* Indicates that pin #0 exists for this port with slew control feature */ 3543 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO0 1u 3544 /* Indicates that pin #1 exists for this port with slew control feature */ 3545 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO1 1u 3546 /* Indicates that pin #2 exists for this port with slew control feature */ 3547 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO2 0u 3548 /* Indicates that pin #3 exists for this port with slew control feature */ 3549 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO3 0u 3550 /* Indicates that pin #4 exists for this port with slew control feature */ 3551 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO4 0u 3552 /* Indicates that pin #5 exists for this port with slew control feature */ 3553 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO5 0u 3554 /* Indicates that pin #6 exists for this port with slew control feature */ 3555 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO6 0u 3556 /* Indicates that pin #7 exists for this port with slew control feature */ 3557 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO7 0u 3558 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3559 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_GPIO 1u 3560 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3561 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SIO 0u 3562 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3563 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_AUTOLVL 1u 3564 /* Indicates port supports drive select trims (new in GPIO_rev4) */ 3565 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_DS_CTRL 0u 3566 /* Indicates port supports slew extension bits */ 3567 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLEW_EXT 0u 3568 /* Indicates port supports drive select extension bits */ 3569 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_DRIVE_EXT 0u 3570 /* Indicates slew bit width */ 3571 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLEW_WIDTH 0u 3572 /* Indicates drive sel bit width */ 3573 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_DRIVE_WIDTH 0u 3574 /* Indicates that pin #0 exists for this port with slew control feature */ 3575 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO0 0u 3576 /* Indicates that pin #1 exists for this port with slew control feature */ 3577 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO1 0u 3578 /* Indicates that pin #2 exists for this port with slew control feature */ 3579 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO2 0u 3580 /* Indicates that pin #3 exists for this port with slew control feature */ 3581 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO3 0u 3582 /* Indicates that pin #4 exists for this port with slew control feature */ 3583 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO4 0u 3584 /* Indicates that pin #5 exists for this port with slew control feature */ 3585 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO5 0u 3586 /* Indicates that pin #6 exists for this port with slew control feature */ 3587 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO6 0u 3588 /* Indicates that pin #7 exists for this port with slew control feature */ 3589 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO7 0u 3590 /* Level Detector present */ 3591 #define IOSS_GPIO_LVL_DET_PRESENT 0u 3592 /* Number of AMUX splitter cells */ 3593 #define IOSS_HSIOM_AMUX_SPLIT_NR 6u 3594 /* Number of HSIOM ports in device */ 3595 #define IOSS_HSIOM_HSIOM_PORT_NR 31u 3596 /* Number of PWR/GND MONITOR CELLs in the device */ 3597 #define IOSS_HSIOM_MONITOR_NR 23u 3598 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 3599 #define IOSS_HSIOM_MONITOR_NR_0_31 23u 3600 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 3601 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 3602 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 3603 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 3604 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 3605 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 3606 /* Indicates the presence of alternate JTAG interface */ 3607 #define IOSS_HSIOM_ALTJTAG_PRESENT 0u 3608 /* Mask of SMARTIO instances presence */ 3609 #define IOSS_SMARTIO_SMARTIO_MASK 128u 3610 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3611 #define JPEGDEC_MASTER_WIDTH 8u 3612 /* Number of LIN channels ([2, 32]). For test functionality (two channels are 3613 connected), the minimal number of LIN channels is 2. */ 3614 #define LIN_CH_NR 2u 3615 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3616 #define LIN_MASTER_WIDTH 8u 3617 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 3618 #define LIN_CHIP_TOP_PLATFORM_VARIANT 2u 3619 /* Number of mixer source ({1, 2, 3, 4, 5, 6, 7, 8}]). */ 3620 #define MIXER0_NR 5u 3621 /* I2S transmitter functionality. */ 3622 #define MIXER0_TX_PRESENT 0u 3623 /* Spare Enable 0=no spare, 1=max, 2=min */ 3624 #define MIXER0_SPARE_EN 1u 3625 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3626 #define MIXER0_MASTER_WIDTH 8u 3627 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 3628 #define MIXER0_PLATFORM_VARIANT 2u 3629 /* RAM vendor (0=CYP, 1=SNPS, 2=ARM) */ 3630 #define MIXER0_RAM_VEND 2u 3631 /* Number of mixer source ({1, 2, 3, 4, 5, 6, 7, 8}]). */ 3632 #define MIXER1_NR 5u 3633 /* I2S transmitter functionality. */ 3634 #define MIXER1_TX_PRESENT 0u 3635 /* Spare Enable 0=no spare, 1=max, 2=min */ 3636 #define MIXER1_SPARE_EN 1u 3637 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3638 #define MIXER1_MASTER_WIDTH 8u 3639 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 3640 #define MIXER1_PLATFORM_VARIANT 2u 3641 /* RAM vendor (0=CYP, 1=SNPS, 2=ARM) */ 3642 #define MIXER1_RAM_VEND 2u 3643 /* Number of SAR and associate sequencers. */ 3644 #define PASS_SAR_ADC_NR 1u 3645 /* Number of ADC slices. Each slice will contain one SARMUX block and optionally a 3646 SAR and associated sequencer logic. */ 3647 #define PASS_SAR_SLICE_NR 2u 3648 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 for each valid ADC 3649 slice. For ADC slices without a SAR, the mux connects to slice zero through 3650 the mux borrowing mechanism, performance is degraded. All connections from IO 3651 for a single mux must be on the same VDDIO domain */ 3652 #define PASS_SAR_SLICE_NR0_SAR_SAR_MUX_IN 24u 3653 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 3654 that lower numbered slices contain the ADCs that are present. */ 3655 #define PASS_SAR_SLICE_NR0_SAR_SAR_ADC_PRESENT 1u 3656 /* Number of SAR sequencer channels (per SAR). Must be set to 0 if SAR_ADC_PRESENT 3657 is 0. */ 3658 #define PASS_SAR_SLICE_NR0_SAR_SAR_CHAN_NR 32u 3659 /* Averaging logic present in SAR. Must be sest to 0 if SAR_ADC_PRESENT is 0. Must 3660 be consistent (all 1 or all 0) for ADC slices where SAR_ADC_PRESENT is 1. */ 3661 #define PASS_SAR_SLICE_NR0_SAR_SAR_AVERAGE 1u 3662 /* Range detect logic present in SAR. Must be set to 1 if PUSEDET=1 Must be sest 3663 to 0 if SAR_ADC_PRESENT is 0. Must be consistent (all 1 or all 0) for ADC 3664 slices where SAR_ADC_PRESENT is 1. */ 3665 #define PASS_SAR_SLICE_NR0_SAR_SAR_RANGEDET 1u 3666 /* Pulse detect logic present in SAR. Must be sest to 0 if SAR_ADC_PRESENT is 0. 3667 Must be consistent (all 1 or all 0) for ADC slices where SAR_ADC_PRESENT is 3668 1. */ 3669 #define PASS_SAR_SLICE_NR0_SAR_SAR_PULSEDET 1u 3670 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 for each valid ADC 3671 slice. For ADC slices without a SAR, the mux connects to slice zero through 3672 the mux borrowing mechanism, performance is degraded. All connections from IO 3673 for a single mux must be on the same VDDIO domain */ 3674 #define PASS_SAR_SLICE_NR1_SAR_SAR_MUX_IN 24u 3675 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 3676 that lower numbered slices contain the ADCs that are present. */ 3677 #define PASS_SAR_SLICE_NR1_SAR_SAR_ADC_PRESENT 0u 3678 /* Number of SAR sequencer channels (per SAR). Must be set to 0 if SAR_ADC_PRESENT 3679 is 0. */ 3680 #define PASS_SAR_SLICE_NR1_SAR_SAR_CHAN_NR 0u 3681 /* Averaging logic present in SAR. Must be sest to 0 if SAR_ADC_PRESENT is 0. Must 3682 be consistent (all 1 or all 0) for ADC slices where SAR_ADC_PRESENT is 1. */ 3683 #define PASS_SAR_SLICE_NR1_SAR_SAR_AVERAGE 0u 3684 /* Range detect logic present in SAR. Must be set to 1 if PUSEDET=1 Must be sest 3685 to 0 if SAR_ADC_PRESENT is 0. Must be consistent (all 1 or all 0) for ADC 3686 slices where SAR_ADC_PRESENT is 1. */ 3687 #define PASS_SAR_SLICE_NR1_SAR_SAR_RANGEDET 0u 3688 /* Pulse detect logic present in SAR. Must be sest to 0 if SAR_ADC_PRESENT is 0. 3689 Must be consistent (all 1 or all 0) for ADC slices where SAR_ADC_PRESENT is 3690 1. */ 3691 #define PASS_SAR_SLICE_NR1_SAR_SAR_PULSEDET 0u 3692 /* Parameter that is 1 for ADC0 only if ADC1 or, if SAR_SLICE_NR > SAR_ADC_NR */ 3693 #define PASS_SAR_SAR_ADC0 1u 3694 /* The number of protection contexts ([2, 16]). */ 3695 #define PERI_PC_NR 8u 3696 /* Master interface presence mask (5 bits) */ 3697 #define PERI_MS_PRESENT 31u 3698 /* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ 3699 #define PERI_ECC_PRESENT 1u 3700 /* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ 3701 #define PERI_ECC_ADDR_PRESENT 1u 3702 /* Peripheral group PCLK root select */ 3703 #define PERI_GROUP_PRESENT0_PERI_GROUP_PCLK_ROOT_SEL 0u 3704 /* Clock control functionality present ('0': no, '1': yes) */ 3705 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3706 /* Slave present ('0': no, '1': yes) */ 3707 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3708 /* Slave present ('0': no, '1': yes) */ 3709 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3710 /* Slave present ('0': no, '1': yes) */ 3711 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3712 /* Slave present ('0': no, '1': yes) */ 3713 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3714 /* Slave present ('0': no, '1': yes) */ 3715 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3716 /* Slave present ('0': no, '1': yes) */ 3717 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3718 /* Slave present ('0': no, '1': yes) */ 3719 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3720 /* Slave present ('0': no, '1': yes) */ 3721 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3722 /* Slave present ('0': no, '1': yes) */ 3723 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3724 /* Slave present ('0': no, '1': yes) */ 3725 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3726 /* Slave present ('0': no, '1': yes) */ 3727 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3728 /* Slave present ('0': no, '1': yes) */ 3729 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3730 /* Slave present ('0': no, '1': yes) */ 3731 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3732 /* Slave present ('0': no, '1': yes) */ 3733 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3734 /* Slave present ('0': no, '1': yes) */ 3735 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3736 /* Slave present ('0': no, '1': yes) */ 3737 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3738 /* Peripheral group PCLK root select */ 3739 #define PERI_GROUP_PRESENT1_PERI_GROUP_PCLK_ROOT_SEL 0u 3740 /* Clock control functionality present ('0': no, '1': yes) */ 3741 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3742 /* Slave present ('0': no, '1': yes) */ 3743 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3744 /* Slave present ('0': no, '1': yes) */ 3745 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3746 /* Slave present ('0': no, '1': yes) */ 3747 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3748 /* Slave present ('0': no, '1': yes) */ 3749 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3750 /* Slave present ('0': no, '1': yes) */ 3751 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3752 /* Slave present ('0': no, '1': yes) */ 3753 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3754 /* Slave present ('0': no, '1': yes) */ 3755 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3756 /* Slave present ('0': no, '1': yes) */ 3757 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3758 /* Slave present ('0': no, '1': yes) */ 3759 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3760 /* Slave present ('0': no, '1': yes) */ 3761 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3762 /* Slave present ('0': no, '1': yes) */ 3763 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3764 /* Slave present ('0': no, '1': yes) */ 3765 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3766 /* Slave present ('0': no, '1': yes) */ 3767 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3768 /* Slave present ('0': no, '1': yes) */ 3769 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3770 /* Slave present ('0': no, '1': yes) */ 3771 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3772 /* Slave present ('0': no, '1': yes) */ 3773 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3774 /* Peripheral group PCLK root select */ 3775 #define PERI_GROUP_PRESENT2_PERI_GROUP_PCLK_ROOT_SEL 0u 3776 /* Clock control functionality present ('0': no, '1': yes) */ 3777 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3778 /* Slave present ('0': no, '1': yes) */ 3779 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3780 /* Slave present ('0': no, '1': yes) */ 3781 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3782 /* Slave present ('0': no, '1': yes) */ 3783 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3784 /* Slave present ('0': no, '1': yes) */ 3785 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3786 /* Slave present ('0': no, '1': yes) */ 3787 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u 3788 /* Slave present ('0': no, '1': yes) */ 3789 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u 3790 /* Slave present ('0': no, '1': yes) */ 3791 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u 3792 /* Slave present ('0': no, '1': yes) */ 3793 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u 3794 /* Slave present ('0': no, '1': yes) */ 3795 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u 3796 /* Slave present ('0': no, '1': yes) */ 3797 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u 3798 /* Slave present ('0': no, '1': yes) */ 3799 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u 3800 /* Slave present ('0': no, '1': yes) */ 3801 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 1u 3802 /* Slave present ('0': no, '1': yes) */ 3803 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u 3804 /* Slave present ('0': no, '1': yes) */ 3805 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3806 /* Slave present ('0': no, '1': yes) */ 3807 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3808 /* Slave present ('0': no, '1': yes) */ 3809 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3810 /* Peripheral group PCLK root select */ 3811 #define PERI_GROUP_PRESENT3_PERI_GROUP_PCLK_ROOT_SEL 0u 3812 /* Clock control functionality present ('0': no, '1': yes) */ 3813 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3814 /* Slave present ('0': no, '1': yes) */ 3815 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3816 /* Slave present ('0': no, '1': yes) */ 3817 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3818 /* Slave present ('0': no, '1': yes) */ 3819 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3820 /* Slave present ('0': no, '1': yes) */ 3821 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3822 /* Slave present ('0': no, '1': yes) */ 3823 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 1u 3824 /* Slave present ('0': no, '1': yes) */ 3825 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3826 /* Slave present ('0': no, '1': yes) */ 3827 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3828 /* Slave present ('0': no, '1': yes) */ 3829 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3830 /* Slave present ('0': no, '1': yes) */ 3831 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3832 /* Slave present ('0': no, '1': yes) */ 3833 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3834 /* Slave present ('0': no, '1': yes) */ 3835 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3836 /* Slave present ('0': no, '1': yes) */ 3837 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3838 /* Slave present ('0': no, '1': yes) */ 3839 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3840 /* Slave present ('0': no, '1': yes) */ 3841 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3842 /* Slave present ('0': no, '1': yes) */ 3843 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3844 /* Slave present ('0': no, '1': yes) */ 3845 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3846 /* Peripheral group PCLK root select */ 3847 #define PERI_GROUP_PRESENT4_PERI_GROUP_PCLK_ROOT_SEL 0u 3848 /* Clock control functionality present ('0': no, '1': yes) */ 3849 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3850 /* Slave present ('0': no, '1': yes) */ 3851 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3852 /* Slave present ('0': no, '1': yes) */ 3853 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3854 /* Slave present ('0': no, '1': yes) */ 3855 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3856 /* Slave present ('0': no, '1': yes) */ 3857 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3858 /* Slave present ('0': no, '1': yes) */ 3859 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3860 /* Slave present ('0': no, '1': yes) */ 3861 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3862 /* Slave present ('0': no, '1': yes) */ 3863 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3864 /* Slave present ('0': no, '1': yes) */ 3865 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3866 /* Slave present ('0': no, '1': yes) */ 3867 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3868 /* Slave present ('0': no, '1': yes) */ 3869 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3870 /* Slave present ('0': no, '1': yes) */ 3871 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3872 /* Slave present ('0': no, '1': yes) */ 3873 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3874 /* Slave present ('0': no, '1': yes) */ 3875 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3876 /* Slave present ('0': no, '1': yes) */ 3877 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3878 /* Slave present ('0': no, '1': yes) */ 3879 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3880 /* Slave present ('0': no, '1': yes) */ 3881 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3882 /* Peripheral group PCLK root select */ 3883 #define PERI_GROUP_PRESENT5_PERI_GROUP_PCLK_ROOT_SEL 1u 3884 /* Clock control functionality present ('0': no, '1': yes) */ 3885 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3886 /* Slave present ('0': no, '1': yes) */ 3887 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3888 /* Slave present ('0': no, '1': yes) */ 3889 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3890 /* Slave present ('0': no, '1': yes) */ 3891 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3892 /* Slave present ('0': no, '1': yes) */ 3893 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3894 /* Slave present ('0': no, '1': yes) */ 3895 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3896 /* Slave present ('0': no, '1': yes) */ 3897 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3898 /* Slave present ('0': no, '1': yes) */ 3899 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3900 /* Slave present ('0': no, '1': yes) */ 3901 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3902 /* Slave present ('0': no, '1': yes) */ 3903 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3904 /* Slave present ('0': no, '1': yes) */ 3905 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3906 /* Slave present ('0': no, '1': yes) */ 3907 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3908 /* Slave present ('0': no, '1': yes) */ 3909 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3910 /* Slave present ('0': no, '1': yes) */ 3911 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3912 /* Slave present ('0': no, '1': yes) */ 3913 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3914 /* Slave present ('0': no, '1': yes) */ 3915 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3916 /* Slave present ('0': no, '1': yes) */ 3917 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3918 /* Peripheral group PCLK root select */ 3919 #define PERI_GROUP_PRESENT6_PERI_GROUP_PCLK_ROOT_SEL 1u 3920 /* Clock control functionality present ('0': no, '1': yes) */ 3921 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3922 /* Slave present ('0': no, '1': yes) */ 3923 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3924 /* Slave present ('0': no, '1': yes) */ 3925 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3926 /* Slave present ('0': no, '1': yes) */ 3927 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3928 /* Slave present ('0': no, '1': yes) */ 3929 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3930 /* Slave present ('0': no, '1': yes) */ 3931 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u 3932 /* Slave present ('0': no, '1': yes) */ 3933 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u 3934 /* Slave present ('0': no, '1': yes) */ 3935 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u 3936 /* Slave present ('0': no, '1': yes) */ 3937 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u 3938 /* Slave present ('0': no, '1': yes) */ 3939 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u 3940 /* Slave present ('0': no, '1': yes) */ 3941 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 1u 3942 /* Slave present ('0': no, '1': yes) */ 3943 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 1u 3944 /* Slave present ('0': no, '1': yes) */ 3945 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 1u 3946 /* Slave present ('0': no, '1': yes) */ 3947 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3948 /* Slave present ('0': no, '1': yes) */ 3949 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3950 /* Slave present ('0': no, '1': yes) */ 3951 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3952 /* Slave present ('0': no, '1': yes) */ 3953 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3954 /* Peripheral group PCLK root select */ 3955 #define PERI_GROUP_PRESENT7_PERI_GROUP_PCLK_ROOT_SEL 0u 3956 /* Clock control functionality present ('0': no, '1': yes) */ 3957 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3958 /* Slave present ('0': no, '1': yes) */ 3959 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3960 /* Slave present ('0': no, '1': yes) */ 3961 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3962 /* Slave present ('0': no, '1': yes) */ 3963 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3964 /* Slave present ('0': no, '1': yes) */ 3965 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3966 /* Slave present ('0': no, '1': yes) */ 3967 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3968 /* Slave present ('0': no, '1': yes) */ 3969 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3970 /* Slave present ('0': no, '1': yes) */ 3971 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3972 /* Slave present ('0': no, '1': yes) */ 3973 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3974 /* Slave present ('0': no, '1': yes) */ 3975 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3976 /* Slave present ('0': no, '1': yes) */ 3977 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3978 /* Slave present ('0': no, '1': yes) */ 3979 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3980 /* Slave present ('0': no, '1': yes) */ 3981 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3982 /* Slave present ('0': no, '1': yes) */ 3983 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3984 /* Slave present ('0': no, '1': yes) */ 3985 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3986 /* Slave present ('0': no, '1': yes) */ 3987 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3988 /* Slave present ('0': no, '1': yes) */ 3989 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3990 /* Peripheral group PCLK root select */ 3991 #define PERI_GROUP_PRESENT8_PERI_GROUP_PCLK_ROOT_SEL 0u 3992 /* Clock control functionality present ('0': no, '1': yes) */ 3993 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3994 /* Slave present ('0': no, '1': yes) */ 3995 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3996 /* Slave present ('0': no, '1': yes) */ 3997 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3998 /* Slave present ('0': no, '1': yes) */ 3999 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 1u 4000 /* Slave present ('0': no, '1': yes) */ 4001 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 1u 4002 /* Slave present ('0': no, '1': yes) */ 4003 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 1u 4004 /* Slave present ('0': no, '1': yes) */ 4005 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 1u 4006 /* Slave present ('0': no, '1': yes) */ 4007 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4008 /* Slave present ('0': no, '1': yes) */ 4009 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4010 /* Slave present ('0': no, '1': yes) */ 4011 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4012 /* Slave present ('0': no, '1': yes) */ 4013 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4014 /* Slave present ('0': no, '1': yes) */ 4015 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4016 /* Slave present ('0': no, '1': yes) */ 4017 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4018 /* Slave present ('0': no, '1': yes) */ 4019 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4020 /* Slave present ('0': no, '1': yes) */ 4021 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4022 /* Slave present ('0': no, '1': yes) */ 4023 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4024 /* Slave present ('0': no, '1': yes) */ 4025 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4026 /* Peripheral group PCLK root select */ 4027 #define PERI_GROUP_PRESENT9_PERI_GROUP_PCLK_ROOT_SEL 1u 4028 /* Clock control functionality present ('0': no, '1': yes) */ 4029 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 4030 /* Slave present ('0': no, '1': yes) */ 4031 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u 4032 /* Slave present ('0': no, '1': yes) */ 4033 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4034 /* Slave present ('0': no, '1': yes) */ 4035 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4036 /* Slave present ('0': no, '1': yes) */ 4037 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4038 /* Slave present ('0': no, '1': yes) */ 4039 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4040 /* Slave present ('0': no, '1': yes) */ 4041 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4042 /* Slave present ('0': no, '1': yes) */ 4043 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4044 /* Slave present ('0': no, '1': yes) */ 4045 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4046 /* Slave present ('0': no, '1': yes) */ 4047 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4048 /* Slave present ('0': no, '1': yes) */ 4049 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4050 /* Slave present ('0': no, '1': yes) */ 4051 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4052 /* Slave present ('0': no, '1': yes) */ 4053 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4054 /* Slave present ('0': no, '1': yes) */ 4055 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4056 /* Slave present ('0': no, '1': yes) */ 4057 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4058 /* Slave present ('0': no, '1': yes) */ 4059 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4060 /* Slave present ('0': no, '1': yes) */ 4061 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4062 /* Peripheral group PCLK root select */ 4063 #define PERI_GROUP_PRESENT10_PERI_GROUP_PCLK_ROOT_SEL 0u 4064 /* Clock control functionality present ('0': no, '1': yes) */ 4065 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 4066 /* Slave present ('0': no, '1': yes) */ 4067 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 1u 4068 /* Slave present ('0': no, '1': yes) */ 4069 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 1u 4070 /* Slave present ('0': no, '1': yes) */ 4071 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 1u 4072 /* Slave present ('0': no, '1': yes) */ 4073 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4074 /* Slave present ('0': no, '1': yes) */ 4075 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4076 /* Slave present ('0': no, '1': yes) */ 4077 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4078 /* Slave present ('0': no, '1': yes) */ 4079 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4080 /* Slave present ('0': no, '1': yes) */ 4081 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4082 /* Slave present ('0': no, '1': yes) */ 4083 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4084 /* Slave present ('0': no, '1': yes) */ 4085 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4086 /* Slave present ('0': no, '1': yes) */ 4087 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4088 /* Slave present ('0': no, '1': yes) */ 4089 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4090 /* Slave present ('0': no, '1': yes) */ 4091 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4092 /* Slave present ('0': no, '1': yes) */ 4093 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4094 /* Slave present ('0': no, '1': yes) */ 4095 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4096 /* Slave present ('0': no, '1': yes) */ 4097 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4098 /* Peripheral group PCLK root select */ 4099 #define PERI_GROUP_PRESENT11_PERI_GROUP_PCLK_ROOT_SEL 0u 4100 /* Clock control functionality present ('0': no, '1': yes) */ 4101 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4102 /* Slave present ('0': no, '1': yes) */ 4103 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4104 /* Slave present ('0': no, '1': yes) */ 4105 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4106 /* Slave present ('0': no, '1': yes) */ 4107 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4108 /* Slave present ('0': no, '1': yes) */ 4109 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4110 /* Slave present ('0': no, '1': yes) */ 4111 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4112 /* Slave present ('0': no, '1': yes) */ 4113 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4114 /* Slave present ('0': no, '1': yes) */ 4115 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4116 /* Slave present ('0': no, '1': yes) */ 4117 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4118 /* Slave present ('0': no, '1': yes) */ 4119 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4120 /* Slave present ('0': no, '1': yes) */ 4121 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4122 /* Slave present ('0': no, '1': yes) */ 4123 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4124 /* Slave present ('0': no, '1': yes) */ 4125 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4126 /* Slave present ('0': no, '1': yes) */ 4127 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4128 /* Slave present ('0': no, '1': yes) */ 4129 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4130 /* Slave present ('0': no, '1': yes) */ 4131 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4132 /* Slave present ('0': no, '1': yes) */ 4133 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4134 /* Peripheral group PCLK root select */ 4135 #define PERI_GROUP_PRESENT12_PERI_GROUP_PCLK_ROOT_SEL 0u 4136 /* Clock control functionality present ('0': no, '1': yes) */ 4137 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4138 /* Slave present ('0': no, '1': yes) */ 4139 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4140 /* Slave present ('0': no, '1': yes) */ 4141 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4142 /* Slave present ('0': no, '1': yes) */ 4143 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4144 /* Slave present ('0': no, '1': yes) */ 4145 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4146 /* Slave present ('0': no, '1': yes) */ 4147 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4148 /* Slave present ('0': no, '1': yes) */ 4149 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4150 /* Slave present ('0': no, '1': yes) */ 4151 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4152 /* Slave present ('0': no, '1': yes) */ 4153 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4154 /* Slave present ('0': no, '1': yes) */ 4155 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4156 /* Slave present ('0': no, '1': yes) */ 4157 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4158 /* Slave present ('0': no, '1': yes) */ 4159 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4160 /* Slave present ('0': no, '1': yes) */ 4161 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4162 /* Slave present ('0': no, '1': yes) */ 4163 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4164 /* Slave present ('0': no, '1': yes) */ 4165 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4166 /* Slave present ('0': no, '1': yes) */ 4167 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4168 /* Slave present ('0': no, '1': yes) */ 4169 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4170 /* Peripheral group PCLK root select */ 4171 #define PERI_GROUP_PRESENT13_PERI_GROUP_PCLK_ROOT_SEL 0u 4172 /* Clock control functionality present ('0': no, '1': yes) */ 4173 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4174 /* Slave present ('0': no, '1': yes) */ 4175 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4176 /* Slave present ('0': no, '1': yes) */ 4177 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4178 /* Slave present ('0': no, '1': yes) */ 4179 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4180 /* Slave present ('0': no, '1': yes) */ 4181 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4182 /* Slave present ('0': no, '1': yes) */ 4183 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4184 /* Slave present ('0': no, '1': yes) */ 4185 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4186 /* Slave present ('0': no, '1': yes) */ 4187 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4188 /* Slave present ('0': no, '1': yes) */ 4189 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4190 /* Slave present ('0': no, '1': yes) */ 4191 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4192 /* Slave present ('0': no, '1': yes) */ 4193 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4194 /* Slave present ('0': no, '1': yes) */ 4195 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4196 /* Slave present ('0': no, '1': yes) */ 4197 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4198 /* Slave present ('0': no, '1': yes) */ 4199 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4200 /* Slave present ('0': no, '1': yes) */ 4201 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4202 /* Slave present ('0': no, '1': yes) */ 4203 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4204 /* Slave present ('0': no, '1': yes) */ 4205 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4206 /* Peripheral group PCLK root select */ 4207 #define PERI_GROUP_PRESENT14_PERI_GROUP_PCLK_ROOT_SEL 0u 4208 /* Clock control functionality present ('0': no, '1': yes) */ 4209 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4210 /* Slave present ('0': no, '1': yes) */ 4211 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4212 /* Slave present ('0': no, '1': yes) */ 4213 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4214 /* Slave present ('0': no, '1': yes) */ 4215 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4216 /* Slave present ('0': no, '1': yes) */ 4217 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4218 /* Slave present ('0': no, '1': yes) */ 4219 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4220 /* Slave present ('0': no, '1': yes) */ 4221 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4222 /* Slave present ('0': no, '1': yes) */ 4223 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4224 /* Slave present ('0': no, '1': yes) */ 4225 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4226 /* Slave present ('0': no, '1': yes) */ 4227 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4228 /* Slave present ('0': no, '1': yes) */ 4229 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4230 /* Slave present ('0': no, '1': yes) */ 4231 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4232 /* Slave present ('0': no, '1': yes) */ 4233 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4234 /* Slave present ('0': no, '1': yes) */ 4235 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4236 /* Slave present ('0': no, '1': yes) */ 4237 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4238 /* Slave present ('0': no, '1': yes) */ 4239 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4240 /* Slave present ('0': no, '1': yes) */ 4241 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4242 /* Peripheral group PCLK root select */ 4243 #define PERI_GROUP_PRESENT15_PERI_GROUP_PCLK_ROOT_SEL 0u 4244 /* Clock control functionality present ('0': no, '1': yes) */ 4245 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 4246 /* Slave present ('0': no, '1': yes) */ 4247 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u 4248 /* Slave present ('0': no, '1': yes) */ 4249 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u 4250 /* Slave present ('0': no, '1': yes) */ 4251 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u 4252 /* Slave present ('0': no, '1': yes) */ 4253 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u 4254 /* Slave present ('0': no, '1': yes) */ 4255 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u 4256 /* Slave present ('0': no, '1': yes) */ 4257 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u 4258 /* Slave present ('0': no, '1': yes) */ 4259 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u 4260 /* Slave present ('0': no, '1': yes) */ 4261 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u 4262 /* Slave present ('0': no, '1': yes) */ 4263 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u 4264 /* Slave present ('0': no, '1': yes) */ 4265 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u 4266 /* Slave present ('0': no, '1': yes) */ 4267 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u 4268 /* Slave present ('0': no, '1': yes) */ 4269 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u 4270 /* Slave present ('0': no, '1': yes) */ 4271 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u 4272 /* Slave present ('0': no, '1': yes) */ 4273 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u 4274 /* Slave present ('0': no, '1': yes) */ 4275 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u 4276 /* Slave present ('0': no, '1': yes) */ 4277 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u 4278 /* Number of asynchronous PCLK groups */ 4279 #define PERI_PCLK_GROUP_NR 2u 4280 /* Timeout functionality present ('0': no, '1': yes) */ 4281 #define PERI_TIMEOUT_PRESENT 1u 4282 /* Trigger module present ('0': no, '1': yes) */ 4283 #define PERI_TR 1u 4284 /* Number of trigger groups */ 4285 #define PERI_TR_GROUP_NR 14u 4286 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4287 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4288 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4289 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4290 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4291 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4292 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4293 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4294 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4295 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4296 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4297 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4298 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4299 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4300 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4301 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4302 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4303 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4304 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4305 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4306 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4307 #define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 0u 4308 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4309 #define PERI_TR_GROUP_NR11_TR_GROUP_TR_MANIPULATION_PRESENT 0u 4310 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4311 #define PERI_TR_GROUP_NR12_TR_GROUP_TR_MANIPULATION_PRESENT 0u 4312 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 4313 #define PERI_TR_GROUP_NR13_TR_GROUP_TR_MANIPULATION_PRESENT 1u 4314 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4315 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4316 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4317 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4318 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4319 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4320 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4321 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4322 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4323 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4324 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4325 #define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4326 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4327 #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4328 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 4329 #define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 4330 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 4331 #define PERI_GR_DIV_ADDR_WIDTH 4u 4332 /* Number of asynchronous PCLK groups */ 4333 #define PERI_PERI_PCLK_PCLK_GROUP_NR 2u 4334 /* Number of 8.0 dividers */ 4335 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 9u 4336 /* Number of 16.0 dividers */ 4337 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 16u 4338 /* Number of 16.5 (fractional) dividers */ 4339 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT 7u 4340 /* Number of 24.5 (fractional) dividers */ 4341 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 3u 4342 /* Number of programmable clocks [1, 256] */ 4343 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT 84u 4344 /* Number of 8.0 dividers */ 4345 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 3u 4346 /* Number of 16.0 dividers */ 4347 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 4u 4348 /* Number of 16.5 (fractional) dividers */ 4349 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT 0u 4350 /* Number of 24.5 (fractional) dividers */ 4351 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 7u 4352 /* Number of programmable clocks [1, 256] */ 4353 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT 21u 4354 /* Number of PWM structures ({1, 2, 3, 4, 5, 6, 7, 8}]). */ 4355 #define PWM_NR 2u 4356 /* Spare Enable 0=no spare, 1=max, 2=min */ 4357 #define PWM_SPARE_EN 1u 4358 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4359 #define PWM_MASTER_WIDTH 8u 4360 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 4361 #define PWM_PLATFORM_VARIANT 2u 4362 /* RAM vendor (0=CYP, 1=SNPS, 2=ARM) */ 4363 #define PWM_RAM_VEND 2u 4364 /* Number of connected clocks at the IP's top level ([1, 4]). */ 4365 #define PWM_CHIP_TOP_CLK_NR 3u 4366 /* DeepSleep support ('0':no, '1': yes) */ 4367 #define SCB0_DEEPSLEEP 1u 4368 /* Externally clocked support? ('0': no, '1': yes) */ 4369 #define SCB0_EC 1u 4370 /* I2C master support? ('0': no, '1': yes) */ 4371 #define SCB0_I2C_M 1u 4372 /* I2C slave support? ('0': no, '1': yes) */ 4373 #define SCB0_I2C_S 1u 4374 /* I2C glitch filters present? ('0': no, '1': yes) */ 4375 #define SCB0_I2C_GLITCH 1u 4376 /* I2C support? (I2C_M | I2C_S) */ 4377 #define SCB0_I2C 1u 4378 /* I2C externally clocked support? ('0': no, '1': yes) */ 4379 #define SCB0_I2C_EC 1u 4380 /* I2C master and slave support? (I2C_M & I2C_S) */ 4381 #define SCB0_I2C_M_S 1u 4382 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4383 #define SCB0_I2C_S_EC 1u 4384 /* SPI master support? ('0': no, '1': yes) */ 4385 #define SCB0_SPI_M 1u 4386 /* SPI slave support? ('0': no, '1': yes) */ 4387 #define SCB0_SPI_S 1u 4388 /* SPI support? (SPI_M | SPI_S) */ 4389 #define SCB0_SPI 1u 4390 /* SPI externally clocked support? ('0': no, '1': yes) */ 4391 #define SCB0_SPI_EC 1u 4392 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4393 #define SCB0_SPI_S_EC 1u 4394 /* UART support? ('0': no, '1': yes) */ 4395 #define SCB0_UART 1u 4396 /* SPI or UART (SPI | UART) */ 4397 #define SCB0_SPI_UART 1u 4398 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4399 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4400 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4401 #define SCB0_EZ_DATA_NR 256u 4402 /* Command/response mode support? ('0': no, '1': yes) */ 4403 #define SCB0_CMD_RESP 1u 4404 /* EZ mode support? ('0': no, '1': yes) */ 4405 #define SCB0_EZ 1u 4406 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4407 #define SCB0_EZ_CMD_RESP 1u 4408 /* I2C slave with EZ mode (I2C_S & EZ) */ 4409 #define SCB0_I2C_S_EZ 1u 4410 /* SPI slave with EZ mode (SPI_S & EZ) */ 4411 #define SCB0_SPI_S_EZ 1u 4412 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4413 #define SCB0_MASTER_WIDTH 8u 4414 /* Number of used spi_select signals (max 4) */ 4415 #define SCB0_CHIP_TOP_SPI_SEL_NR 4u 4416 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4417 #define SCB0_CHIP_TOP_I2C_FAST_PLUS 1u 4418 /* DeepSleep support ('0':no, '1': yes) */ 4419 #define SCB1_DEEPSLEEP 0u 4420 /* Externally clocked support? ('0': no, '1': yes) */ 4421 #define SCB1_EC 1u 4422 /* I2C master support? ('0': no, '1': yes) */ 4423 #define SCB1_I2C_M 1u 4424 /* I2C slave support? ('0': no, '1': yes) */ 4425 #define SCB1_I2C_S 1u 4426 /* I2C glitch filters present? ('0': no, '1': yes) */ 4427 #define SCB1_I2C_GLITCH 1u 4428 /* I2C support? (I2C_M | I2C_S) */ 4429 #define SCB1_I2C 1u 4430 /* I2C externally clocked support? ('0': no, '1': yes) */ 4431 #define SCB1_I2C_EC 0u 4432 /* I2C master and slave support? (I2C_M & I2C_S) */ 4433 #define SCB1_I2C_M_S 1u 4434 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4435 #define SCB1_I2C_S_EC 0u 4436 /* SPI master support? ('0': no, '1': yes) */ 4437 #define SCB1_SPI_M 1u 4438 /* SPI slave support? ('0': no, '1': yes) */ 4439 #define SCB1_SPI_S 1u 4440 /* SPI support? (SPI_M | SPI_S) */ 4441 #define SCB1_SPI 1u 4442 /* SPI externally clocked support? ('0': no, '1': yes) */ 4443 #define SCB1_SPI_EC 1u 4444 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4445 #define SCB1_SPI_S_EC 1u 4446 /* UART support? ('0': no, '1': yes) */ 4447 #define SCB1_UART 1u 4448 /* SPI or UART (SPI | UART) */ 4449 #define SCB1_SPI_UART 1u 4450 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4451 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4452 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4453 #define SCB1_EZ_DATA_NR 256u 4454 /* Command/response mode support? ('0': no, '1': yes) */ 4455 #define SCB1_CMD_RESP 0u 4456 /* EZ mode support? ('0': no, '1': yes) */ 4457 #define SCB1_EZ 1u 4458 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4459 #define SCB1_EZ_CMD_RESP 1u 4460 /* I2C slave with EZ mode (I2C_S & EZ) */ 4461 #define SCB1_I2C_S_EZ 1u 4462 /* SPI slave with EZ mode (SPI_S & EZ) */ 4463 #define SCB1_SPI_S_EZ 1u 4464 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4465 #define SCB1_MASTER_WIDTH 8u 4466 /* Number of used spi_select signals (max 4) */ 4467 #define SCB1_CHIP_TOP_SPI_SEL_NR 2u 4468 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4469 #define SCB1_CHIP_TOP_I2C_FAST_PLUS 1u 4470 /* DeepSleep support ('0':no, '1': yes) */ 4471 #define SCB2_DEEPSLEEP 0u 4472 /* Externally clocked support? ('0': no, '1': yes) */ 4473 #define SCB2_EC 1u 4474 /* I2C master support? ('0': no, '1': yes) */ 4475 #define SCB2_I2C_M 1u 4476 /* I2C slave support? ('0': no, '1': yes) */ 4477 #define SCB2_I2C_S 1u 4478 /* I2C glitch filters present? ('0': no, '1': yes) */ 4479 #define SCB2_I2C_GLITCH 1u 4480 /* I2C support? (I2C_M | I2C_S) */ 4481 #define SCB2_I2C 1u 4482 /* I2C externally clocked support? ('0': no, '1': yes) */ 4483 #define SCB2_I2C_EC 0u 4484 /* I2C master and slave support? (I2C_M & I2C_S) */ 4485 #define SCB2_I2C_M_S 1u 4486 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4487 #define SCB2_I2C_S_EC 0u 4488 /* SPI master support? ('0': no, '1': yes) */ 4489 #define SCB2_SPI_M 1u 4490 /* SPI slave support? ('0': no, '1': yes) */ 4491 #define SCB2_SPI_S 1u 4492 /* SPI support? (SPI_M | SPI_S) */ 4493 #define SCB2_SPI 1u 4494 /* SPI externally clocked support? ('0': no, '1': yes) */ 4495 #define SCB2_SPI_EC 1u 4496 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4497 #define SCB2_SPI_S_EC 1u 4498 /* UART support? ('0': no, '1': yes) */ 4499 #define SCB2_UART 1u 4500 /* SPI or UART (SPI | UART) */ 4501 #define SCB2_SPI_UART 1u 4502 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4503 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4504 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4505 #define SCB2_EZ_DATA_NR 256u 4506 /* Command/response mode support? ('0': no, '1': yes) */ 4507 #define SCB2_CMD_RESP 0u 4508 /* EZ mode support? ('0': no, '1': yes) */ 4509 #define SCB2_EZ 1u 4510 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4511 #define SCB2_EZ_CMD_RESP 1u 4512 /* I2C slave with EZ mode (I2C_S & EZ) */ 4513 #define SCB2_I2C_S_EZ 1u 4514 /* SPI slave with EZ mode (SPI_S & EZ) */ 4515 #define SCB2_SPI_S_EZ 1u 4516 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4517 #define SCB2_MASTER_WIDTH 8u 4518 /* Number of used spi_select signals (max 4) */ 4519 #define SCB2_CHIP_TOP_SPI_SEL_NR 2u 4520 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4521 #define SCB2_CHIP_TOP_I2C_FAST_PLUS 1u 4522 /* DeepSleep support ('0':no, '1': yes) */ 4523 #define SCB3_DEEPSLEEP 0u 4524 /* Externally clocked support? ('0': no, '1': yes) */ 4525 #define SCB3_EC 1u 4526 /* I2C master support? ('0': no, '1': yes) */ 4527 #define SCB3_I2C_M 1u 4528 /* I2C slave support? ('0': no, '1': yes) */ 4529 #define SCB3_I2C_S 1u 4530 /* I2C glitch filters present? ('0': no, '1': yes) */ 4531 #define SCB3_I2C_GLITCH 1u 4532 /* I2C support? (I2C_M | I2C_S) */ 4533 #define SCB3_I2C 1u 4534 /* I2C externally clocked support? ('0': no, '1': yes) */ 4535 #define SCB3_I2C_EC 0u 4536 /* I2C master and slave support? (I2C_M & I2C_S) */ 4537 #define SCB3_I2C_M_S 1u 4538 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4539 #define SCB3_I2C_S_EC 0u 4540 /* SPI master support? ('0': no, '1': yes) */ 4541 #define SCB3_SPI_M 1u 4542 /* SPI slave support? ('0': no, '1': yes) */ 4543 #define SCB3_SPI_S 1u 4544 /* SPI support? (SPI_M | SPI_S) */ 4545 #define SCB3_SPI 1u 4546 /* SPI externally clocked support? ('0': no, '1': yes) */ 4547 #define SCB3_SPI_EC 1u 4548 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4549 #define SCB3_SPI_S_EC 1u 4550 /* UART support? ('0': no, '1': yes) */ 4551 #define SCB3_UART 1u 4552 /* SPI or UART (SPI | UART) */ 4553 #define SCB3_SPI_UART 1u 4554 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4555 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4556 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4557 #define SCB3_EZ_DATA_NR 256u 4558 /* Command/response mode support? ('0': no, '1': yes) */ 4559 #define SCB3_CMD_RESP 0u 4560 /* EZ mode support? ('0': no, '1': yes) */ 4561 #define SCB3_EZ 1u 4562 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4563 #define SCB3_EZ_CMD_RESP 1u 4564 /* I2C slave with EZ mode (I2C_S & EZ) */ 4565 #define SCB3_I2C_S_EZ 1u 4566 /* SPI slave with EZ mode (SPI_S & EZ) */ 4567 #define SCB3_SPI_S_EZ 1u 4568 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4569 #define SCB3_MASTER_WIDTH 8u 4570 /* Number of used spi_select signals (max 4) */ 4571 #define SCB3_CHIP_TOP_SPI_SEL_NR 2u 4572 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4573 #define SCB3_CHIP_TOP_I2C_FAST_PLUS 1u 4574 /* DeepSleep support ('0':no, '1': yes) */ 4575 #define SCB4_DEEPSLEEP 0u 4576 /* Externally clocked support? ('0': no, '1': yes) */ 4577 #define SCB4_EC 1u 4578 /* I2C master support? ('0': no, '1': yes) */ 4579 #define SCB4_I2C_M 1u 4580 /* I2C slave support? ('0': no, '1': yes) */ 4581 #define SCB4_I2C_S 1u 4582 /* I2C glitch filters present? ('0': no, '1': yes) */ 4583 #define SCB4_I2C_GLITCH 1u 4584 /* I2C support? (I2C_M | I2C_S) */ 4585 #define SCB4_I2C 1u 4586 /* I2C externally clocked support? ('0': no, '1': yes) */ 4587 #define SCB4_I2C_EC 0u 4588 /* I2C master and slave support? (I2C_M & I2C_S) */ 4589 #define SCB4_I2C_M_S 1u 4590 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4591 #define SCB4_I2C_S_EC 0u 4592 /* SPI master support? ('0': no, '1': yes) */ 4593 #define SCB4_SPI_M 1u 4594 /* SPI slave support? ('0': no, '1': yes) */ 4595 #define SCB4_SPI_S 1u 4596 /* SPI support? (SPI_M | SPI_S) */ 4597 #define SCB4_SPI 1u 4598 /* SPI externally clocked support? ('0': no, '1': yes) */ 4599 #define SCB4_SPI_EC 1u 4600 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4601 #define SCB4_SPI_S_EC 1u 4602 /* UART support? ('0': no, '1': yes) */ 4603 #define SCB4_UART 1u 4604 /* SPI or UART (SPI | UART) */ 4605 #define SCB4_SPI_UART 1u 4606 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4607 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4608 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4609 #define SCB4_EZ_DATA_NR 256u 4610 /* Command/response mode support? ('0': no, '1': yes) */ 4611 #define SCB4_CMD_RESP 0u 4612 /* EZ mode support? ('0': no, '1': yes) */ 4613 #define SCB4_EZ 1u 4614 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4615 #define SCB4_EZ_CMD_RESP 1u 4616 /* I2C slave with EZ mode (I2C_S & EZ) */ 4617 #define SCB4_I2C_S_EZ 1u 4618 /* SPI slave with EZ mode (SPI_S & EZ) */ 4619 #define SCB4_SPI_S_EZ 1u 4620 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4621 #define SCB4_MASTER_WIDTH 8u 4622 /* Number of used spi_select signals (max 4) */ 4623 #define SCB4_CHIP_TOP_SPI_SEL_NR 2u 4624 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4625 #define SCB4_CHIP_TOP_I2C_FAST_PLUS 1u 4626 /* DeepSleep support ('0':no, '1': yes) */ 4627 #define SCB5_DEEPSLEEP 0u 4628 /* Externally clocked support? ('0': no, '1': yes) */ 4629 #define SCB5_EC 1u 4630 /* I2C master support? ('0': no, '1': yes) */ 4631 #define SCB5_I2C_M 1u 4632 /* I2C slave support? ('0': no, '1': yes) */ 4633 #define SCB5_I2C_S 1u 4634 /* I2C glitch filters present? ('0': no, '1': yes) */ 4635 #define SCB5_I2C_GLITCH 1u 4636 /* I2C support? (I2C_M | I2C_S) */ 4637 #define SCB5_I2C 1u 4638 /* I2C externally clocked support? ('0': no, '1': yes) */ 4639 #define SCB5_I2C_EC 0u 4640 /* I2C master and slave support? (I2C_M & I2C_S) */ 4641 #define SCB5_I2C_M_S 1u 4642 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4643 #define SCB5_I2C_S_EC 0u 4644 /* SPI master support? ('0': no, '1': yes) */ 4645 #define SCB5_SPI_M 1u 4646 /* SPI slave support? ('0': no, '1': yes) */ 4647 #define SCB5_SPI_S 1u 4648 /* SPI support? (SPI_M | SPI_S) */ 4649 #define SCB5_SPI 1u 4650 /* SPI externally clocked support? ('0': no, '1': yes) */ 4651 #define SCB5_SPI_EC 1u 4652 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4653 #define SCB5_SPI_S_EC 1u 4654 /* UART support? ('0': no, '1': yes) */ 4655 #define SCB5_UART 1u 4656 /* SPI or UART (SPI | UART) */ 4657 #define SCB5_SPI_UART 1u 4658 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4659 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4660 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4661 #define SCB5_EZ_DATA_NR 256u 4662 /* Command/response mode support? ('0': no, '1': yes) */ 4663 #define SCB5_CMD_RESP 0u 4664 /* EZ mode support? ('0': no, '1': yes) */ 4665 #define SCB5_EZ 1u 4666 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4667 #define SCB5_EZ_CMD_RESP 1u 4668 /* I2C slave with EZ mode (I2C_S & EZ) */ 4669 #define SCB5_I2C_S_EZ 1u 4670 /* SPI slave with EZ mode (SPI_S & EZ) */ 4671 #define SCB5_SPI_S_EZ 1u 4672 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4673 #define SCB5_MASTER_WIDTH 8u 4674 /* Number of used spi_select signals (max 4) */ 4675 #define SCB5_CHIP_TOP_SPI_SEL_NR 2u 4676 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4677 #define SCB5_CHIP_TOP_I2C_FAST_PLUS 1u 4678 /* DeepSleep support ('0':no, '1': yes) */ 4679 #define SCB6_DEEPSLEEP 0u 4680 /* Externally clocked support? ('0': no, '1': yes) */ 4681 #define SCB6_EC 1u 4682 /* I2C master support? ('0': no, '1': yes) */ 4683 #define SCB6_I2C_M 1u 4684 /* I2C slave support? ('0': no, '1': yes) */ 4685 #define SCB6_I2C_S 1u 4686 /* I2C glitch filters present? ('0': no, '1': yes) */ 4687 #define SCB6_I2C_GLITCH 1u 4688 /* I2C support? (I2C_M | I2C_S) */ 4689 #define SCB6_I2C 1u 4690 /* I2C externally clocked support? ('0': no, '1': yes) */ 4691 #define SCB6_I2C_EC 0u 4692 /* I2C master and slave support? (I2C_M & I2C_S) */ 4693 #define SCB6_I2C_M_S 1u 4694 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4695 #define SCB6_I2C_S_EC 0u 4696 /* SPI master support? ('0': no, '1': yes) */ 4697 #define SCB6_SPI_M 1u 4698 /* SPI slave support? ('0': no, '1': yes) */ 4699 #define SCB6_SPI_S 1u 4700 /* SPI support? (SPI_M | SPI_S) */ 4701 #define SCB6_SPI 1u 4702 /* SPI externally clocked support? ('0': no, '1': yes) */ 4703 #define SCB6_SPI_EC 1u 4704 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4705 #define SCB6_SPI_S_EC 1u 4706 /* UART support? ('0': no, '1': yes) */ 4707 #define SCB6_UART 1u 4708 /* SPI or UART (SPI | UART) */ 4709 #define SCB6_SPI_UART 1u 4710 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4711 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4712 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4713 #define SCB6_EZ_DATA_NR 256u 4714 /* Command/response mode support? ('0': no, '1': yes) */ 4715 #define SCB6_CMD_RESP 0u 4716 /* EZ mode support? ('0': no, '1': yes) */ 4717 #define SCB6_EZ 1u 4718 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4719 #define SCB6_EZ_CMD_RESP 1u 4720 /* I2C slave with EZ mode (I2C_S & EZ) */ 4721 #define SCB6_I2C_S_EZ 1u 4722 /* SPI slave with EZ mode (SPI_S & EZ) */ 4723 #define SCB6_SPI_S_EZ 1u 4724 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4725 #define SCB6_MASTER_WIDTH 8u 4726 /* Number of used spi_select signals (max 4) */ 4727 #define SCB6_CHIP_TOP_SPI_SEL_NR 2u 4728 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4729 #define SCB6_CHIP_TOP_I2C_FAST_PLUS 1u 4730 /* DeepSleep support ('0':no, '1': yes) */ 4731 #define SCB7_DEEPSLEEP 0u 4732 /* Externally clocked support? ('0': no, '1': yes) */ 4733 #define SCB7_EC 1u 4734 /* I2C master support? ('0': no, '1': yes) */ 4735 #define SCB7_I2C_M 1u 4736 /* I2C slave support? ('0': no, '1': yes) */ 4737 #define SCB7_I2C_S 1u 4738 /* I2C glitch filters present? ('0': no, '1': yes) */ 4739 #define SCB7_I2C_GLITCH 1u 4740 /* I2C support? (I2C_M | I2C_S) */ 4741 #define SCB7_I2C 1u 4742 /* I2C externally clocked support? ('0': no, '1': yes) */ 4743 #define SCB7_I2C_EC 0u 4744 /* I2C master and slave support? (I2C_M & I2C_S) */ 4745 #define SCB7_I2C_M_S 1u 4746 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4747 #define SCB7_I2C_S_EC 0u 4748 /* SPI master support? ('0': no, '1': yes) */ 4749 #define SCB7_SPI_M 1u 4750 /* SPI slave support? ('0': no, '1': yes) */ 4751 #define SCB7_SPI_S 1u 4752 /* SPI support? (SPI_M | SPI_S) */ 4753 #define SCB7_SPI 1u 4754 /* SPI externally clocked support? ('0': no, '1': yes) */ 4755 #define SCB7_SPI_EC 1u 4756 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4757 #define SCB7_SPI_S_EC 1u 4758 /* UART support? ('0': no, '1': yes) */ 4759 #define SCB7_UART 1u 4760 /* SPI or UART (SPI | UART) */ 4761 #define SCB7_SPI_UART 1u 4762 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4763 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4764 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4765 #define SCB7_EZ_DATA_NR 256u 4766 /* Command/response mode support? ('0': no, '1': yes) */ 4767 #define SCB7_CMD_RESP 0u 4768 /* EZ mode support? ('0': no, '1': yes) */ 4769 #define SCB7_EZ 1u 4770 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4771 #define SCB7_EZ_CMD_RESP 1u 4772 /* I2C slave with EZ mode (I2C_S & EZ) */ 4773 #define SCB7_I2C_S_EZ 1u 4774 /* SPI slave with EZ mode (SPI_S & EZ) */ 4775 #define SCB7_SPI_S_EZ 1u 4776 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4777 #define SCB7_MASTER_WIDTH 8u 4778 /* Number of used spi_select signals (max 4) */ 4779 #define SCB7_CHIP_TOP_SPI_SEL_NR 2u 4780 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4781 #define SCB7_CHIP_TOP_I2C_FAST_PLUS 1u 4782 /* DeepSleep support ('0':no, '1': yes) */ 4783 #define SCB8_DEEPSLEEP 0u 4784 /* Externally clocked support? ('0': no, '1': yes) */ 4785 #define SCB8_EC 1u 4786 /* I2C master support? ('0': no, '1': yes) */ 4787 #define SCB8_I2C_M 1u 4788 /* I2C slave support? ('0': no, '1': yes) */ 4789 #define SCB8_I2C_S 1u 4790 /* I2C glitch filters present? ('0': no, '1': yes) */ 4791 #define SCB8_I2C_GLITCH 1u 4792 /* I2C support? (I2C_M | I2C_S) */ 4793 #define SCB8_I2C 1u 4794 /* I2C externally clocked support? ('0': no, '1': yes) */ 4795 #define SCB8_I2C_EC 0u 4796 /* I2C master and slave support? (I2C_M & I2C_S) */ 4797 #define SCB8_I2C_M_S 1u 4798 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4799 #define SCB8_I2C_S_EC 0u 4800 /* SPI master support? ('0': no, '1': yes) */ 4801 #define SCB8_SPI_M 1u 4802 /* SPI slave support? ('0': no, '1': yes) */ 4803 #define SCB8_SPI_S 1u 4804 /* SPI support? (SPI_M | SPI_S) */ 4805 #define SCB8_SPI 1u 4806 /* SPI externally clocked support? ('0': no, '1': yes) */ 4807 #define SCB8_SPI_EC 1u 4808 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4809 #define SCB8_SPI_S_EC 1u 4810 /* UART support? ('0': no, '1': yes) */ 4811 #define SCB8_UART 1u 4812 /* SPI or UART (SPI | UART) */ 4813 #define SCB8_SPI_UART 1u 4814 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4815 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4816 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4817 #define SCB8_EZ_DATA_NR 256u 4818 /* Command/response mode support? ('0': no, '1': yes) */ 4819 #define SCB8_CMD_RESP 0u 4820 /* EZ mode support? ('0': no, '1': yes) */ 4821 #define SCB8_EZ 1u 4822 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4823 #define SCB8_EZ_CMD_RESP 1u 4824 /* I2C slave with EZ mode (I2C_S & EZ) */ 4825 #define SCB8_I2C_S_EZ 1u 4826 /* SPI slave with EZ mode (SPI_S & EZ) */ 4827 #define SCB8_SPI_S_EZ 1u 4828 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4829 #define SCB8_MASTER_WIDTH 8u 4830 /* Number of used spi_select signals (max 4) */ 4831 #define SCB8_CHIP_TOP_SPI_SEL_NR 2u 4832 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4833 #define SCB8_CHIP_TOP_I2C_FAST_PLUS 1u 4834 /* DeepSleep support ('0':no, '1': yes) */ 4835 #define SCB9_DEEPSLEEP 0u 4836 /* Externally clocked support? ('0': no, '1': yes) */ 4837 #define SCB9_EC 1u 4838 /* I2C master support? ('0': no, '1': yes) */ 4839 #define SCB9_I2C_M 1u 4840 /* I2C slave support? ('0': no, '1': yes) */ 4841 #define SCB9_I2C_S 1u 4842 /* I2C glitch filters present? ('0': no, '1': yes) */ 4843 #define SCB9_I2C_GLITCH 1u 4844 /* I2C support? (I2C_M | I2C_S) */ 4845 #define SCB9_I2C 1u 4846 /* I2C externally clocked support? ('0': no, '1': yes) */ 4847 #define SCB9_I2C_EC 0u 4848 /* I2C master and slave support? (I2C_M & I2C_S) */ 4849 #define SCB9_I2C_M_S 1u 4850 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4851 #define SCB9_I2C_S_EC 0u 4852 /* SPI master support? ('0': no, '1': yes) */ 4853 #define SCB9_SPI_M 1u 4854 /* SPI slave support? ('0': no, '1': yes) */ 4855 #define SCB9_SPI_S 1u 4856 /* SPI support? (SPI_M | SPI_S) */ 4857 #define SCB9_SPI 1u 4858 /* SPI externally clocked support? ('0': no, '1': yes) */ 4859 #define SCB9_SPI_EC 1u 4860 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4861 #define SCB9_SPI_S_EC 1u 4862 /* UART support? ('0': no, '1': yes) */ 4863 #define SCB9_UART 1u 4864 /* SPI or UART (SPI | UART) */ 4865 #define SCB9_SPI_UART 1u 4866 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4867 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4868 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4869 #define SCB9_EZ_DATA_NR 256u 4870 /* Command/response mode support? ('0': no, '1': yes) */ 4871 #define SCB9_CMD_RESP 0u 4872 /* EZ mode support? ('0': no, '1': yes) */ 4873 #define SCB9_EZ 1u 4874 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4875 #define SCB9_EZ_CMD_RESP 1u 4876 /* I2C slave with EZ mode (I2C_S & EZ) */ 4877 #define SCB9_I2C_S_EZ 1u 4878 /* SPI slave with EZ mode (SPI_S & EZ) */ 4879 #define SCB9_SPI_S_EZ 1u 4880 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4881 #define SCB9_MASTER_WIDTH 8u 4882 /* Number of used spi_select signals (max 4) */ 4883 #define SCB9_CHIP_TOP_SPI_SEL_NR 2u 4884 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4885 #define SCB9_CHIP_TOP_I2C_FAST_PLUS 1u 4886 /* DeepSleep support ('0':no, '1': yes) */ 4887 #define SCB10_DEEPSLEEP 0u 4888 /* Externally clocked support? ('0': no, '1': yes) */ 4889 #define SCB10_EC 1u 4890 /* I2C master support? ('0': no, '1': yes) */ 4891 #define SCB10_I2C_M 1u 4892 /* I2C slave support? ('0': no, '1': yes) */ 4893 #define SCB10_I2C_S 1u 4894 /* I2C glitch filters present? ('0': no, '1': yes) */ 4895 #define SCB10_I2C_GLITCH 1u 4896 /* I2C support? (I2C_M | I2C_S) */ 4897 #define SCB10_I2C 1u 4898 /* I2C externally clocked support? ('0': no, '1': yes) */ 4899 #define SCB10_I2C_EC 0u 4900 /* I2C master and slave support? (I2C_M & I2C_S) */ 4901 #define SCB10_I2C_M_S 1u 4902 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4903 #define SCB10_I2C_S_EC 0u 4904 /* SPI master support? ('0': no, '1': yes) */ 4905 #define SCB10_SPI_M 1u 4906 /* SPI slave support? ('0': no, '1': yes) */ 4907 #define SCB10_SPI_S 1u 4908 /* SPI support? (SPI_M | SPI_S) */ 4909 #define SCB10_SPI 1u 4910 /* SPI externally clocked support? ('0': no, '1': yes) */ 4911 #define SCB10_SPI_EC 1u 4912 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4913 #define SCB10_SPI_S_EC 1u 4914 /* UART support? ('0': no, '1': yes) */ 4915 #define SCB10_UART 1u 4916 /* SPI or UART (SPI | UART) */ 4917 #define SCB10_SPI_UART 1u 4918 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4919 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4920 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4921 #define SCB10_EZ_DATA_NR 256u 4922 /* Command/response mode support? ('0': no, '1': yes) */ 4923 #define SCB10_CMD_RESP 0u 4924 /* EZ mode support? ('0': no, '1': yes) */ 4925 #define SCB10_EZ 1u 4926 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4927 #define SCB10_EZ_CMD_RESP 1u 4928 /* I2C slave with EZ mode (I2C_S & EZ) */ 4929 #define SCB10_I2C_S_EZ 1u 4930 /* SPI slave with EZ mode (SPI_S & EZ) */ 4931 #define SCB10_SPI_S_EZ 1u 4932 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4933 #define SCB10_MASTER_WIDTH 8u 4934 /* Number of used spi_select signals (max 4) */ 4935 #define SCB10_CHIP_TOP_SPI_SEL_NR 2u 4936 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4937 #define SCB10_CHIP_TOP_I2C_FAST_PLUS 1u 4938 /* DeepSleep support ('0':no, '1': yes) */ 4939 #define SCB11_DEEPSLEEP 0u 4940 /* Externally clocked support? ('0': no, '1': yes) */ 4941 #define SCB11_EC 1u 4942 /* I2C master support? ('0': no, '1': yes) */ 4943 #define SCB11_I2C_M 1u 4944 /* I2C slave support? ('0': no, '1': yes) */ 4945 #define SCB11_I2C_S 1u 4946 /* I2C glitch filters present? ('0': no, '1': yes) */ 4947 #define SCB11_I2C_GLITCH 1u 4948 /* I2C support? (I2C_M | I2C_S) */ 4949 #define SCB11_I2C 1u 4950 /* I2C externally clocked support? ('0': no, '1': yes) */ 4951 #define SCB11_I2C_EC 0u 4952 /* I2C master and slave support? (I2C_M & I2C_S) */ 4953 #define SCB11_I2C_M_S 1u 4954 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4955 #define SCB11_I2C_S_EC 0u 4956 /* SPI master support? ('0': no, '1': yes) */ 4957 #define SCB11_SPI_M 1u 4958 /* SPI slave support? ('0': no, '1': yes) */ 4959 #define SCB11_SPI_S 1u 4960 /* SPI support? (SPI_M | SPI_S) */ 4961 #define SCB11_SPI 1u 4962 /* SPI externally clocked support? ('0': no, '1': yes) */ 4963 #define SCB11_SPI_EC 1u 4964 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4965 #define SCB11_SPI_S_EC 1u 4966 /* UART support? ('0': no, '1': yes) */ 4967 #define SCB11_UART 1u 4968 /* SPI or UART (SPI | UART) */ 4969 #define SCB11_SPI_UART 1u 4970 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4971 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4972 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4973 #define SCB11_EZ_DATA_NR 256u 4974 /* Command/response mode support? ('0': no, '1': yes) */ 4975 #define SCB11_CMD_RESP 0u 4976 /* EZ mode support? ('0': no, '1': yes) */ 4977 #define SCB11_EZ 1u 4978 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4979 #define SCB11_EZ_CMD_RESP 1u 4980 /* I2C slave with EZ mode (I2C_S & EZ) */ 4981 #define SCB11_I2C_S_EZ 1u 4982 /* SPI slave with EZ mode (SPI_S & EZ) */ 4983 #define SCB11_SPI_S_EZ 1u 4984 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4985 #define SCB11_MASTER_WIDTH 8u 4986 /* Number of used spi_select signals (max 4) */ 4987 #define SCB11_CHIP_TOP_SPI_SEL_NR 2u 4988 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4989 #define SCB11_CHIP_TOP_I2C_FAST_PLUS 1u 4990 /* SONOS Flash is used or not ('0': no, '1': yes) */ 4991 #define SFLASH_FLASHC_IS_SONOS 0u 4992 /* WOUND_PRESENT or not ('0': no, '1': yes) */ 4993 #define SFLASH_WOUND_PRESENT 1u 4994 /* RAM_VEND_PRESENT or not ('0': no, '1': yes) */ 4995 #define SFLASH_RAM_VEND_PRESENT 1u 4996 /* Number of sound generator structures ({1, 2, 3, 4, 5, 6, 7, 8}]). */ 4997 #define SG_NR 5u 4998 /* Spare Enable 0=no spare, 1=max, 2=min */ 4999 #define SG_SPARE_EN 1u 5000 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 5001 #define SG_MASTER_WIDTH 8u 5002 /* Number of connected clocks at the IP's top level ([1, 4]). */ 5003 #define SG_CHIP_TOP_CLK_NR 3u 5004 /* Slow AHB XIP cache is present ([0,1]). If SLOW_AHB_XIP_IF_PRESENT=0 then set 5005 this to 0 as well. */ 5006 #define SMIF_SLOW_CACHE_PRESENT 1u 5007 /* Fast AHB XIP cache is present ([0,1]). If FAST_AHB_XIP_IF_PRESENT=0 then set 5008 this to 0 as well. */ 5009 #define SMIF_FAST_CACHE_PRESENT 0u 5010 /* Base address of the SMIF0 XIP memory region. This address must be a multiple of 5011 the SMIF0 XIP memory region capacity (see SMIF0_XIP_MASK below). The SMIF0 5012 XIP memory region should NOT overlap with other memory regions. This adress 5013 must be in the [0x0000:0000, 0xffff:0000] memory region. However, for MXS40 5014 CM4 based platform variant, this address must be in the [0x0000:0000, 5015 0x1fff:0000] memory region (to ensure a connection to the ARM CM4 CPU 5016 ICode/DCode memory region [0x0000:0000, 0x1fff:ffff]). The external memory 5017 devices are located within the SMIF0 XIP memory region. */ 5018 #define SMIF_SMIF0_XIP_ADDR 0x60000000u 5019 /* Capacity of the SMIF0 XIP memory region. The capacity must be a power of 2 and 5020 greater or equal than 64 KB). The more significant bits of this parameter are 5021 '1' and the lesser significant bits of this parameter are '0'. E.g., 5022 0xfff0:0000 specifies a 1 MB memory region. Must be set to 512MB when 5023 BRIDGE_PRESENT=1. */ 5024 #define SMIF_SMIF0_XIP_MASK 0xE0000000u 5025 /* Same as SMIF0_XIP_ADDR except for SMIF1. Only applicable if BRIDGE_PRESENT=1. */ 5026 #define SMIF_SMIF1_XIP_ADDR 0x80000000u 5027 /* Same as SMIF0_XIP_MASK except for SMIF1. Only applicable if BRIDGE_PRESENT=1. */ 5028 #define SMIF_SMIF1_XIP_MASK 0xE0000000u 5029 /* Cryptography (AES) support. This is a 1-bit parameter: '0' = no support, '1' = 5030 support. */ 5031 #define SMIF_CRYPTO 1u 5032 /* Number of cryptography keys [0,1,2,4,8]; set to 0 if CRYPTO=0 */ 5033 #define SMIF_CRYPTO_KEY_NR 4u 5034 /* Hardcoded 8-bit parameter (do NOT override) that allows crypto key 0 to take on 5035 additional registers to support MMIO encryption */ 5036 #define SMIF_CRYPTO_KEY_MMIO_CAPABLE 1u 5037 /* Bus CRC support is present ([0,1]) Note: In MXS40 SMIF version 2 this option is 5038 currently not available (BUS_CRC_PRESENT=0). Based on project schedules this 5039 feature may be added already to MXS40 SMIF version 2 or to a later SMIF 5040 version. */ 5041 #define SMIF_BUS_CRC_PRESENT 0u 5042 /* Number of external memory devices supported. This parameter is in the range 5043 [1,4]. */ 5044 #define SMIF_DEVICE_NR 2u 5045 /* External memory devices write support. This is a 4-bit field. Each external 5046 memory device has a dedicated bit. E.g., if bit 2 is '1', external device 2 5047 has write support. */ 5048 #define SMIF_DEVICE_WR_EN 3u 5049 /* DLP capture scheme present ([0,1]) */ 5050 #define SMIF_DLP_PRESENT 1u 5051 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 5052 #define SMIF_MASTER_WIDTH 8u 5053 /* AXI ID width. Legal range [11,16] */ 5054 #define SMIF_AXIS_ID_WIDTH 13u 5055 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 5056 pins) */ 5057 #define SMIF_CHIP_TOP_DATA8_PRESENT 1u 5058 /* Number of used spi_select signals (max 4) */ 5059 #define SMIF_CHIP_TOP_SPI_SEL_NR 2u 5060 /* Slow AHB XIP cache is present ([0,1]). If SLOW_AHB_XIP_IF_PRESENT=0 then set 5061 this to 0 as well. */ 5062 #define SMIF_CORE_SLOW_CACHE_PRESENT 1u 5063 /* Fast AHB XIP cache is present ([0,1]). If FAST_AHB_XIP_IF_PRESENT=0 then set 5064 this to 0 as well. */ 5065 #define SMIF_CORE_FAST_CACHE_PRESENT 0u 5066 /* Number of cryptography keys [0,1,2,4,8]; set to 0 if CRYPTO=0 */ 5067 #define SMIF_CORE_CRYPTO_KEY_NR 4u 5068 /* Bus CRC support is present ([0,1]) Note: In MXS40 SMIF version 2 this option is 5069 currently not available (BUS_CRC_PRESENT=0). Based on project schedules this 5070 feature may be added already to MXS40 SMIF version 2 or to a later SMIF 5071 version. */ 5072 #define SMIF_CORE_BUS_CRC_PRESENT 0u 5073 /* Number of external memory devices supported. This parameter is in the range 5074 [1,4]. */ 5075 #define SMIF_CORE_DEVICE_NR 2u 5076 /* DLP capture scheme present ([0,1]) */ 5077 #define SMIF_CORE_DLP_PRESENT 1u 5078 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 5079 #define SRSS_ULP_VARIANT 0u 5080 /* HT variant. Must be 1 when targeting S40E and 0 otherwise. */ 5081 #define SRSS_HT_VARIANT 1u 5082 /* Number of regulator modules instantiated within SRSS. Must be > 0. */ 5083 #define SRSS_NUM_ACTREG_PWRMOD 6u 5084 /* Number of shorting switches between vccd and vccact. Must be > 0. */ 5085 #define SRSS_NUM_ACTIVE_SWITCH 6u 5086 /* ULP linear regulator system is present */ 5087 #define SRSS_ULPLINREG_PRESENT 0u 5088 /* HT linear regulator system is present */ 5089 #define SRSS_HTLINREG_PRESENT 1u 5090 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator 5091 system (ULPLINREG_PRESENT==1). */ 5092 #define SRSS_SIMOBUCK_PRESENT 0u 5093 /* Precision ILO (PILO) is present */ 5094 #define SRSS_PILO_PRESENT 0u 5095 /* External Crystal Oscillator is present (high frequency) */ 5096 #define SRSS_ECO_PRESENT 1u 5097 /* System Buck-Boost is present */ 5098 #define SRSS_SYSBB_PRESENT 0u 5099 /* Number of additional HIBERNATE wakeup sources */ 5100 #define SRSS_NUM_HIB_WAKE 10u 5101 /* Number of PWR_HIB_DATA registers. Min is zero. */ 5102 #define SRSS_NUM_HIBDATA 1u 5103 /* Number of clock paths. Must be > 0. Recommend 5104 NUM_CLKPATH>=NUM_PLL+CSV_PRESENT+2. CSV and FLL requires special paths, and 5105 one extra is recommended for programming flexibility. */ 5106 #define SRSS_NUM_CLKPATH 11u 5107 /* Number of PLLs present. Must be < NUM_CLKPATH */ 5108 #define SRSS_NUM_PLL 3u 5109 /* Number of HFCLK roots present. Must be > 0. Recommend NUM_HFROOT=<# chipwide 5110 roots>+CSV_PRESENT. */ 5111 #define SRSS_NUM_HFROOT 14u 5112 /* Number of DSI inputs into clock muxes. This is used for logic optimization. 5113 Must be > 0 */ 5114 #define SRSS_NUM_DSI 0u 5115 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 5116 #define SRSS_ALTHF_PRESENT 0u 5117 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 5118 #define SRSS_ALTLF_PRESENT 0u 5119 /* Backup domain is present. See VBCK_PRESENT for whether it is supplied by vddd 5120 or by an independent vbackup supply. */ 5121 #define SRSS_BACKUP_PRESENT 1u 5122 /* CSV present. User must add one NUM_CLKPATH and one NUM_HFROOT to monitor ILO0 5123 with CSV_HF_REF clock. */ 5124 #define SRSS_CSV_PRESENT 1u 5125 /* CSV_BAK is present. Monitors clk_bak_hv using clk_ilo0_hv. */ 5126 #define SRSS_CSV_BAK_PRESENT 1u 5127 /* Number of multi-counter watchdog timers. Min is zero. */ 5128 #define SRSS_NUM_MCWDT 3u 5129 /* Use the hardened clkactfllmux block */ 5130 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 5131 /* Number of clock paths, including direct paths in hardened clkactfllmux block */ 5132 #define SRSS_HARD_CLKPATH 13u 5133 /* Number of clock paths with muxes in hardened clkactfllmux block */ 5134 #define SRSS_HARD_CLKPATHMUX 13u 5135 /* Number of HFCLKS present in hardened clkactfllmux block */ 5136 #define SRSS_HARD_HFROOT 16u 5137 /* ECO mux is present in hardened clkactfllmux block */ 5138 #define SRSS_HARD_ECOMUX_PRESENT 1u 5139 /* ALTHF mux is present in hardened clkactfllmux block */ 5140 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 5141 /* LPECO mux is present in hardened clkactfllmux block */ 5142 #define SRSS_HARD_LPECOMUX_PRESENT 1u 5143 /* POR present. */ 5144 #define SRSS_POR_PRESENT 1u 5145 /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT 5146 or SIMOBUCK_PRESENT. */ 5147 #define SRSS_BUCKCTL_PRESENT 0u 5148 /* Low-current SISO buck core regulator is present. Only compatible with ULP 5149 linear regulator system (ULPLINREG_PRESENT==1). */ 5150 #define SRSS_S40S_SISOBUCKLC_PRESENT 0u 5151 /* HT linear regulator system is present */ 5152 #define SRSS_S40E_HTREGHC_PRESENT 0u 5153 /* PMIC control of vccd is present (without REGHC). */ 5154 #define SRSS_S40E_PMIC_PRESENT 1u 5155 /* Low power external crystal oscillator (LPECO) is present. */ 5156 #define SRSS_S40E_LPECO_PRESENT 1u 5157 /* Number of 400MHz PLLs present. */ 5158 #define SRSS_NUM_PLL400M 5u 5159 /* Number of 400MHz digital PLLs present. */ 5160 #define SRSS_NUM_DPLL400M 0u 5161 /* Instantiates the DPLL400M after other PLLs. DPLL400M is recommended to be first 5162 so it can be used for TDF scan. This parameter is to allow putting a DPLL on 5163 an existing product for testing purposes, without affecting the 5164 customer-visible sources. */ 5165 #define SRSS_DPLL400M_LAST 1u 5166 /* Total number of PLLs present. */ 5167 #define SRSS_NUM_TOTAL_PLL 8u 5168 /* Mask of DIRECT_MUX defaults. For each clock root i, if bit[i] is low the 5169 DIRECT_MUX defaults to IMO. If bit[0] is high, the DIRECT_MUX selects the 5170 output of ROOT_MUX. For backward compatibility, M4 systems can have all mask 5171 bits high. BootROM needs either Bit0 high or a code change to pick predivider 5172 output before using the FLL. */ 5173 #define SRSS_MASK_DIRECTMUX_DEF 1u 5174 /* Mask of which HFCLK roots are enabled when the debugger requests power up 5175 (CDBGPWRUPREQ). For each clock root i, SRSS enables the clock in response to 5176 CDBGPWRUPREQ, if bit[i] of mask is high. SRSS automatically enables clk_hf0, 5177 regardless of setting of mask bit0. */ 5178 #define SRSS_MASK_DEBUG_CLK 0x0000FFFFu 5179 /* Separate power supply Vbackup is present (only used when BACKUP_PRESENT==1) */ 5180 #define SRSS_BACKUP_VBCK_PRESENT 0u 5181 /* Alarm1 present in RTC */ 5182 #define SRSS_BACKUP_ALM1_PRESENT 1u 5183 /* Alarm2 present in RTC */ 5184 #define SRSS_BACKUP_ALM2_PRESENT 1u 5185 /* CSV_BAK is present. Monitors clk_bak_hv using clk_ilo0_hv. */ 5186 #define SRSS_BACKUP_CSV_BAK_PRESENT 1u 5187 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 5188 #define SRSS_BACKUP_BMEM_PRESENT 0u 5189 /* Number of Backup registers to include (each is 32b). Only used when 5190 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 5191 #define SRSS_BACKUP_NUM_BREG 4u 5192 /* Low power external crystal oscillator (LPECO) is present. */ 5193 #define SRSS_BACKUP_S40E_LPECO_PRESENT 1u 5194 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 5195 #define SRSS_CLK_TRIM_DPLL400M_ULP_VARIANT 0u 5196 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 5197 #define SRSS_CLK_TRIM_PLL400M_ULP_VARIANT 0u 5198 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 5199 mask indicates presence of a CSV. */ 5200 #define SRSS_CSV_HF_MASK_HFCSV 0x00003FFFu 5201 /* Number of input triggers per counter only routed to one counter (0..8) */ 5202 #define TCPWM_TR_ONE_CNT_NR 1u 5203 /* Number of input triggers routed to all counters (0..254), TR_ONE_CNT_NR+TR_ALL 5204 CNT_NR <= 254 */ 5205 #define TCPWM_TR_ALL_CNT_NR 60u 5206 /* Number of TCPWM counter groups (1..4) */ 5207 #define TCPWM_GRP_NR 3u 5208 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 5209 #define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 16u 5210 /* Second Capture / Compare Unit is present (0, 1) */ 5211 #define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 1u 5212 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 5213 GRP_CC1_PRESENT = 1 */ 5214 #define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u 5215 /* Stepper Motor Control features are present (0, 1). */ 5216 #define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u 5217 /* Number of counters per TCPWM group (1..256) */ 5218 #define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 38u 5219 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 5220 #define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u 5221 /* Second Capture / Compare Unit is present (0, 1) */ 5222 #define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u 5223 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 5224 GRP_CC1_PRESENT = 1 */ 5225 #define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u 5226 /* Stepper Motor Control features are present (0, 1). */ 5227 #define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 1u 5228 /* Number of counters per TCPWM group (1..256) */ 5229 #define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 12u 5230 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 5231 #define TCPWM_GRP_NR2_CNT_GRP_CNT_WIDTH 32u 5232 /* Second Capture / Compare Unit is present (0, 1) */ 5233 #define TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT 1u 5234 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 5235 GRP_CC1_PRESENT = 1 */ 5236 #define TCPWM_GRP_NR2_CNT_GRP_AMC_PRESENT 0u 5237 /* Stepper Motor Control features are present (0, 1). */ 5238 #define TCPWM_GRP_NR2_CNT_GRP_SMC_PRESENT 0u 5239 /* Number of counters per TCPWM group (1..256) */ 5240 #define TCPWM_GRP_NR2_GRP_GRP_CNT_NR 32u 5241 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 5242 #define TCPWM_MASTER_WIDTH 8u 5243 /* Number of TDM structures ({1, 2, 3, 4}]). */ 5244 #define TDM_NR 4u 5245 /* Number of channels per TDM structure. */ 5246 #define TDM_NR0_CH_NR 32u 5247 /* Number of channels per TDM structure. */ 5248 #define TDM_NR0_TDM_RX_STRUCT_CH_NR 32u 5249 /* Number of channels per TDM structure. */ 5250 #define TDM_NR0_TDM_TX_STRUCT_CH_NR 32u 5251 /* Number of channels per TDM structure. */ 5252 #define TDM_NR1_CH_NR 32u 5253 /* Number of channels per TDM structure. */ 5254 #define TDM_NR1_TDM_RX_STRUCT_CH_NR 32u 5255 /* Number of channels per TDM structure. */ 5256 #define TDM_NR1_TDM_TX_STRUCT_CH_NR 32u 5257 /* Number of channels per TDM structure. */ 5258 #define TDM_NR2_CH_NR 32u 5259 /* Number of channels per TDM structure. */ 5260 #define TDM_NR2_TDM_RX_STRUCT_CH_NR 32u 5261 /* Number of channels per TDM structure. */ 5262 #define TDM_NR2_TDM_TX_STRUCT_CH_NR 32u 5263 /* Number of channels per TDM structure. */ 5264 #define TDM_NR3_CH_NR 32u 5265 /* Number of channels per TDM structure. */ 5266 #define TDM_NR3_TDM_RX_STRUCT_CH_NR 32u 5267 /* Number of channels per TDM structure. */ 5268 #define TDM_NR3_TDM_TX_STRUCT_CH_NR 32u 5269 /* Spare Enable 0=no spare, 1=max, 2=min */ 5270 #define TDM_SPARE_EN 1u 5271 /* Use mxsramwrap IP */ 5272 #define TDM_MXSRAMWRAP_EN 0u 5273 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 5274 #define TDM_MASTER_WIDTH 8u 5275 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 5276 #define TDM_PLATFORM_VARIANT 2u 5277 /* RAM vendor (0=CYP, 1=SNPS, 2=ARM) */ 5278 #define TDM_RAM_VEND 2u 5279 /* Number of connected clocks at the IP's top level ([1, 4]). */ 5280 #define TDM_CHIP_TOP_CLK_NR 3u 5281 /* Replay functionality for transmitter. This functionality adds significant 5282 silicon area. */ 5283 #define TDM_TDM_TX_STRUCT_REPLAY_PRESENT 0u 5284 /* Integrate FPD-Link Interface #0 */ 5285 #define VIDEOSS_FPDLINK0 1u 5286 /* Integrate FPD-Link Interface #1 */ 5287 #define VIDEOSS_FPDLINK1 1u 5288 /* Number of protection contexts. */ 5289 #define VIDEOSS_PC_NR 8u 5290 /* VRPU structures. */ 5291 #define VIDEOSS_VRPU_STRUCT_NR 8u 5292 /* Capture engine present */ 5293 #define VIDEOSS_COMPENG_CAPTURE0 1u 5294 /* Warping present */ 5295 #define VIDEOSS_COMPENG_WARPING 1u 5296 /* Capture engine present */ 5297 #define VIDEOSS_COMPENGCFG_CAPTURE0 1u 5298 /* Warping present */ 5299 #define VIDEOSS_COMPENGCFG_WARPING 1u 5300 /* GFX_MPU_RD_MS_PRESENT[i] is 1 for each existing read master except CPUSS (ID 0) */ 5301 #define VIDEOSS_GFX_MPU_RD_GFX_MPU_RD_MS_PRESENT 0x00001FFEu 5302 /* Number of protection contexts minus 1 */ 5303 #define VIDEOSS_GFX_MPU_RD_PC_NR_MINUS_1 7u 5304 /* GFX_MPU_WR_MS_PRESENT[i] is 1 for each existing write master except CPUSS (ID 5305 0) */ 5306 #define VIDEOSS_GFX_MPU_WR_GFX_MPU_WR_MS_PRESENT 0x00007000u 5307 /* Number of protection contexts minus 1 */ 5308 #define VIDEOSS_GFX_MPU_WR_PC_NR_MINUS_1 7u 5309 /* Power Switch block includes power mode state machine */ 5310 #define VIDEOSS_PD_MODE_CTL_PRESENT 1u 5311 /* Capture engine present */ 5312 #define VIDEOSS_SUBIO_CAPTURE0 1u 5313 /* VRPU structures. */ 5314 #define VIDEOSS_VRPU_VRPU_STRUCT_NR 8u 5315 /* VRAM Protection for read master with ID=0 */ 5316 #define VIDEOSS_VRPU_VRPU_RD_MS0_PRESENT 1u 5317 /* VRAM Protection for read master with ID=1 */ 5318 #define VIDEOSS_VRPU_VRPU_RD_MS1_PRESENT 1u 5319 /* VRAM Protection for read master with ID=2 */ 5320 #define VIDEOSS_VRPU_VRPU_RD_MS2_PRESENT 1u 5321 /* VRAM Protection for read master with ID=3 */ 5322 #define VIDEOSS_VRPU_VRPU_RD_MS3_PRESENT 1u 5323 /* VRAM Protection for read master with ID=4 */ 5324 #define VIDEOSS_VRPU_VRPU_RD_MS4_PRESENT 1u 5325 /* VRAM Protection for read master with ID=5 */ 5326 #define VIDEOSS_VRPU_VRPU_RD_MS5_PRESENT 1u 5327 /* VRAM Protection for read master with ID=6 */ 5328 #define VIDEOSS_VRPU_VRPU_RD_MS6_PRESENT 1u 5329 /* VRAM Protection for read master with ID=7 */ 5330 #define VIDEOSS_VRPU_VRPU_RD_MS7_PRESENT 1u 5331 /* VRAM Protection for read master with ID=8 */ 5332 #define VIDEOSS_VRPU_VRPU_RD_MS8_PRESENT 1u 5333 /* VRAM Protection for read master with ID=9 */ 5334 #define VIDEOSS_VRPU_VRPU_RD_MS9_PRESENT 1u 5335 /* VRAM Protection for read master with ID=10 */ 5336 #define VIDEOSS_VRPU_VRPU_RD_MS10_PRESENT 1u 5337 /* VRAM Protection for read master with ID=11 */ 5338 #define VIDEOSS_VRPU_VRPU_RD_MS11_PRESENT 1u 5339 /* VRAM Protection for read master with ID=12 */ 5340 #define VIDEOSS_VRPU_VRPU_RD_MS12_PRESENT 1u 5341 /* VRAM Protection for read master with ID=13 */ 5342 #define VIDEOSS_VRPU_VRPU_RD_MS13_PRESENT 0u 5343 /* VRAM Protection for read master with ID=14 */ 5344 #define VIDEOSS_VRPU_VRPU_RD_MS14_PRESENT 0u 5345 /* VRAM Protection for read master with ID=15 */ 5346 #define VIDEOSS_VRPU_VRPU_RD_MS15_PRESENT 0u 5347 /* VRAM Protection for write master with ID=0 */ 5348 #define VIDEOSS_VRPU_VRPU_WR_MS0_PRESENT 1u 5349 /* VRAM Protection for write master with ID=1 */ 5350 #define VIDEOSS_VRPU_VRPU_WR_MS1_PRESENT 0u 5351 /* VRAM Protection for write master with ID=2 */ 5352 #define VIDEOSS_VRPU_VRPU_WR_MS2_PRESENT 0u 5353 /* VRAM Protection for write master with ID=3 */ 5354 #define VIDEOSS_VRPU_VRPU_WR_MS3_PRESENT 0u 5355 /* VRAM Protection for write master with ID=4 */ 5356 #define VIDEOSS_VRPU_VRPU_WR_MS4_PRESENT 0u 5357 /* VRAM Protection for write master with ID=5 */ 5358 #define VIDEOSS_VRPU_VRPU_WR_MS5_PRESENT 0u 5359 /* VRAM Protection for write master with ID=6 */ 5360 #define VIDEOSS_VRPU_VRPU_WR_MS6_PRESENT 0u 5361 /* VRAM Protection for write master with ID=7 */ 5362 #define VIDEOSS_VRPU_VRPU_WR_MS7_PRESENT 0u 5363 /* VRAM Protection for write master with ID=8 */ 5364 #define VIDEOSS_VRPU_VRPU_WR_MS8_PRESENT 0u 5365 /* VRAM Protection for write master with ID=9 */ 5366 #define VIDEOSS_VRPU_VRPU_WR_MS9_PRESENT 0u 5367 /* VRAM Protection for write master with ID=10 */ 5368 #define VIDEOSS_VRPU_VRPU_WR_MS10_PRESENT 0u 5369 /* VRAM Protection for write master with ID=11 */ 5370 #define VIDEOSS_VRPU_VRPU_WR_MS11_PRESENT 0u 5371 /* VRAM Protection for write master with ID=12 */ 5372 #define VIDEOSS_VRPU_VRPU_WR_MS12_PRESENT 1u 5373 /* VRAM Protection for write master with ID=13 */ 5374 #define VIDEOSS_VRPU_VRPU_WR_MS13_PRESENT 1u 5375 /* VRAM Protection for write master with ID=14 */ 5376 #define VIDEOSS_VRPU_VRPU_WR_MS14_PRESENT 1u 5377 /* VRAM Protection for write master with ID=15 */ 5378 #define VIDEOSS_VRPU_VRPU_WR_MS15_PRESENT 0u 5379 /* VRAM Protection context No. - 1 for read master with ID=1 */ 5380 #define VIDEOSS_VRPU_VRPU_RD_MS1_PC_NR_MINUS1 7u 5381 /* VRAM Protection context No. - 1 for read master with ID=2 */ 5382 #define VIDEOSS_VRPU_VRPU_RD_MS2_PC_NR_MINUS1 7u 5383 /* VRAM Protection context No. - 1 for read master with ID=3 */ 5384 #define VIDEOSS_VRPU_VRPU_RD_MS3_PC_NR_MINUS1 7u 5385 /* VRAM Protection context No. - 1 for read master with ID=4 */ 5386 #define VIDEOSS_VRPU_VRPU_RD_MS4_PC_NR_MINUS1 7u 5387 /* VRAM Protection context No. - 1 for read master with ID=5 */ 5388 #define VIDEOSS_VRPU_VRPU_RD_MS5_PC_NR_MINUS1 7u 5389 /* VRAM Protection context No. - 1 for read master with ID=6 */ 5390 #define VIDEOSS_VRPU_VRPU_RD_MS6_PC_NR_MINUS1 7u 5391 /* VRAM Protection context No. - 1 for read master with ID=7 */ 5392 #define VIDEOSS_VRPU_VRPU_RD_MS7_PC_NR_MINUS1 7u 5393 /* VRAM Protection context No. - 1 for read master with ID=8 */ 5394 #define VIDEOSS_VRPU_VRPU_RD_MS8_PC_NR_MINUS1 7u 5395 /* VRAM Protection context No. - 1 for read master with ID=9 */ 5396 #define VIDEOSS_VRPU_VRPU_RD_MS9_PC_NR_MINUS1 7u 5397 /* VRAM Protection context No. - 1 for read master with ID=10 */ 5398 #define VIDEOSS_VRPU_VRPU_RD_MS10_PC_NR_MINUS1 7u 5399 /* VRAM Protection context No. - 1 for read master with ID=11 */ 5400 #define VIDEOSS_VRPU_VRPU_RD_MS11_PC_NR_MINUS1 7u 5401 /* VRAM Protection context No. - 1 for read master with ID=12 */ 5402 #define VIDEOSS_VRPU_VRPU_RD_MS12_PC_NR_MINUS1 7u 5403 /* VRAM Protection context No. - 1 for read master with ID=13 */ 5404 #define VIDEOSS_VRPU_VRPU_RD_MS13_PC_NR_MINUS1 7u 5405 /* VRAM Protection context No. - 1 for read master with ID=14 */ 5406 #define VIDEOSS_VRPU_VRPU_RD_MS14_PC_NR_MINUS1 7u 5407 /* VRAM Protection context No. - 1 for read master with ID=15 */ 5408 #define VIDEOSS_VRPU_VRPU_RD_MS15_PC_NR_MINUS1 7u 5409 /* VRAM Protection context No. - 1 for write master with ID=1 */ 5410 #define VIDEOSS_VRPU_VRPU_WR_MS1_PC_NR_MINUS1 7u 5411 /* VRAM Protection context No. - 1 for write master with ID=2 */ 5412 #define VIDEOSS_VRPU_VRPU_WR_MS2_PC_NR_MINUS1 7u 5413 /* VRAM Protection context No. - 1 for write master with ID=3 */ 5414 #define VIDEOSS_VRPU_VRPU_WR_MS3_PC_NR_MINUS1 7u 5415 /* VRAM Protection context No. - 1 for write master with ID=4 */ 5416 #define VIDEOSS_VRPU_VRPU_WR_MS4_PC_NR_MINUS1 7u 5417 /* VRAM Protection context No. - 1 for write master with ID=5 */ 5418 #define VIDEOSS_VRPU_VRPU_WR_MS5_PC_NR_MINUS1 7u 5419 /* VRAM Protection context No. - 1 for write master with ID=6 */ 5420 #define VIDEOSS_VRPU_VRPU_WR_MS6_PC_NR_MINUS1 7u 5421 /* VRAM Protection context No. - 1 for write master with ID=7 */ 5422 #define VIDEOSS_VRPU_VRPU_WR_MS7_PC_NR_MINUS1 7u 5423 /* VRAM Protection context No. - 1 for write master with ID=8 */ 5424 #define VIDEOSS_VRPU_VRPU_WR_MS8_PC_NR_MINUS1 7u 5425 /* VRAM Protection context No. - 1 for write master with ID=9 */ 5426 #define VIDEOSS_VRPU_VRPU_WR_MS9_PC_NR_MINUS1 7u 5427 /* VRAM Protection context No. - 1 for write master with ID=10 */ 5428 #define VIDEOSS_VRPU_VRPU_WR_MS10_PC_NR_MINUS1 7u 5429 /* VRAM Protection context No. - 1 for write master with ID=11 */ 5430 #define VIDEOSS_VRPU_VRPU_WR_MS11_PC_NR_MINUS1 7u 5431 /* VRAM Protection context No. - 1 for write master with ID=12 */ 5432 #define VIDEOSS_VRPU_VRPU_WR_MS12_PC_NR_MINUS1 7u 5433 /* VRAM Protection context No. - 1 for write master with ID=13 */ 5434 #define VIDEOSS_VRPU_VRPU_WR_MS13_PC_NR_MINUS1 7u 5435 /* VRAM Protection context No. - 1 for write master with ID=14 */ 5436 #define VIDEOSS_VRPU_VRPU_WR_MS14_PC_NR_MINUS1 7u 5437 /* VRAM Protection context No. - 1 for write master with ID=15 */ 5438 #define VIDEOSS_VRPU_VRPU_WR_MS15_PC_NR_MINUS1 7u 5439 /* Number of protection contexts minus 1 */ 5440 #define VIDEOSS_VRPU_STRUCT_PC_NR_MINUS1 7u 5441 5442 /* MMIO Targets Defines */ 5443 /* MMIO1.CRYPTO */ 5444 #define CY_MMIO_CRYPTO_GROUP_NR 1u 5445 #define CY_MMIO_CRYPTO_SLAVE_NR 0u 5446 /* MMIO2.CPUSS */ 5447 #define CY_MMIO_CPUSS_GROUP_NR 2u 5448 #define CY_MMIO_CPUSS_SLAVE_NR 0u 5449 /* MMIO2.FAULT */ 5450 #define CY_MMIO_FAULT_GROUP_NR 2u 5451 #define CY_MMIO_FAULT_SLAVE_NR 1u 5452 /* MMIO2.IPC */ 5453 #define CY_MMIO_IPC_GROUP_NR 2u 5454 #define CY_MMIO_IPC_SLAVE_NR 2u 5455 /* MMIO2.PROT */ 5456 #define CY_MMIO_PROT_GROUP_NR 2u 5457 #define CY_MMIO_PROT_SLAVE_NR 3u 5458 /* MMIO2.FLASHC */ 5459 #define CY_MMIO_FLASHC_GROUP_NR 2u 5460 #define CY_MMIO_FLASHC_SLAVE_NR 4u 5461 /* MMIO2.SRSS */ 5462 #define CY_MMIO_SRSS_GROUP_NR 2u 5463 #define CY_MMIO_SRSS_SLAVE_NR 5u 5464 /* MMIO2.BACKUP */ 5465 #define CY_MMIO_BACKUP_GROUP_NR 2u 5466 #define CY_MMIO_BACKUP_SLAVE_NR 6u 5467 /* MMIO2.DW */ 5468 #define CY_MMIO_DW_GROUP_NR 2u 5469 #define CY_MMIO_DW_SLAVE_NR 7u 5470 /* MMIO2.DMAC */ 5471 #define CY_MMIO_DMAC_GROUP_NR 2u 5472 #define CY_MMIO_DMAC_SLAVE_NR 9u 5473 /* MMIO2.AXI_DMAC */ 5474 #define CY_MMIO_AXI_DMAC_GROUP_NR 2u 5475 #define CY_MMIO_AXI_DMAC_SLAVE_NR 10u 5476 /* MMIO2.EFUSE */ 5477 #define CY_MMIO_EFUSE_GROUP_NR 2u 5478 #define CY_MMIO_EFUSE_SLAVE_NR 11u 5479 /* MMIO2.DFT */ 5480 #define CY_MMIO_DFT_GROUP_NR 2u 5481 #define CY_MMIO_DFT_SLAVE_NR 12u 5482 /* MMIO3.HSIOM */ 5483 #define CY_MMIO_HSIOM_GROUP_NR 3u 5484 #define CY_MMIO_HSIOM_SLAVE_NR 0u 5485 /* MMIO3.GPIO */ 5486 #define CY_MMIO_GPIO_GROUP_NR 3u 5487 #define CY_MMIO_GPIO_SLAVE_NR 1u 5488 /* MMIO3.SMARTIO */ 5489 #define CY_MMIO_SMARTIO_GROUP_NR 3u 5490 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 5491 /* MMIO3.TCPWM0 */ 5492 #define CY_MMIO_TCPWM0_GROUP_NR 3u 5493 #define CY_MMIO_TCPWM0_SLAVE_NR 3u 5494 /* MMIO3.EVTGEN0 */ 5495 #define CY_MMIO_EVTGEN0_GROUP_NR 3u 5496 #define CY_MMIO_EVTGEN0_SLAVE_NR 4u 5497 /* MMIO4.SMIF0 */ 5498 #define CY_MMIO_SMIF0_GROUP_NR 4u 5499 #define CY_MMIO_SMIF0_SLAVE_NR 0u 5500 /* MMIO4.ETH0 */ 5501 #define CY_MMIO_ETH0_GROUP_NR 4u 5502 #define CY_MMIO_ETH0_SLAVE_NR 1u 5503 /* MMIO5.LIN0 */ 5504 #define CY_MMIO_LIN0_GROUP_NR 5u 5505 #define CY_MMIO_LIN0_SLAVE_NR 0u 5506 /* MMIO5.CXPI0 */ 5507 #define CY_MMIO_CXPI0_GROUP_NR 5u 5508 #define CY_MMIO_CXPI0_SLAVE_NR 1u 5509 /* MMIO5.CANFD0 */ 5510 #define CY_MMIO_CANFD0_GROUP_NR 5u 5511 #define CY_MMIO_CANFD0_SLAVE_NR 2u 5512 /* MMIO5.CANFD1 */ 5513 #define CY_MMIO_CANFD1_GROUP_NR 5u 5514 #define CY_MMIO_CANFD1_SLAVE_NR 3u 5515 /* MMIO6.SCB0 */ 5516 #define CY_MMIO_SCB0_GROUP_NR 6u 5517 #define CY_MMIO_SCB0_SLAVE_NR 0u 5518 /* MMIO6.SCB1 */ 5519 #define CY_MMIO_SCB1_GROUP_NR 6u 5520 #define CY_MMIO_SCB1_SLAVE_NR 1u 5521 /* MMIO6.SCB2 */ 5522 #define CY_MMIO_SCB2_GROUP_NR 6u 5523 #define CY_MMIO_SCB2_SLAVE_NR 2u 5524 /* MMIO6.SCB3 */ 5525 #define CY_MMIO_SCB3_GROUP_NR 6u 5526 #define CY_MMIO_SCB3_SLAVE_NR 3u 5527 /* MMIO6.SCB4 */ 5528 #define CY_MMIO_SCB4_GROUP_NR 6u 5529 #define CY_MMIO_SCB4_SLAVE_NR 4u 5530 /* MMIO6.SCB5 */ 5531 #define CY_MMIO_SCB5_GROUP_NR 6u 5532 #define CY_MMIO_SCB5_SLAVE_NR 5u 5533 /* MMIO6.SCB6 */ 5534 #define CY_MMIO_SCB6_GROUP_NR 6u 5535 #define CY_MMIO_SCB6_SLAVE_NR 6u 5536 /* MMIO6.SCB7 */ 5537 #define CY_MMIO_SCB7_GROUP_NR 6u 5538 #define CY_MMIO_SCB7_SLAVE_NR 7u 5539 /* MMIO6.SCB8 */ 5540 #define CY_MMIO_SCB8_GROUP_NR 6u 5541 #define CY_MMIO_SCB8_SLAVE_NR 8u 5542 /* MMIO6.SCB9 */ 5543 #define CY_MMIO_SCB9_GROUP_NR 6u 5544 #define CY_MMIO_SCB9_SLAVE_NR 9u 5545 /* MMIO6.SCB10 */ 5546 #define CY_MMIO_SCB10_GROUP_NR 6u 5547 #define CY_MMIO_SCB10_SLAVE_NR 10u 5548 /* MMIO6.SCB11 */ 5549 #define CY_MMIO_SCB11_GROUP_NR 6u 5550 #define CY_MMIO_SCB11_SLAVE_NR 11u 5551 /* MMIO8.TDM0 */ 5552 #define CY_MMIO_TDM0_GROUP_NR 8u 5553 #define CY_MMIO_TDM0_SLAVE_NR 0u 5554 /* MMIO8.SG0 */ 5555 #define CY_MMIO_SG0_GROUP_NR 8u 5556 #define CY_MMIO_SG0_SLAVE_NR 1u 5557 /* MMIO8.PWM0 */ 5558 #define CY_MMIO_PWM0_GROUP_NR 8u 5559 #define CY_MMIO_PWM0_SLAVE_NR 2u 5560 /* MMIO8.DAC0 */ 5561 #define CY_MMIO_DAC0_GROUP_NR 8u 5562 #define CY_MMIO_DAC0_SLAVE_NR 3u 5563 /* MMIO8.MIXER0 */ 5564 #define CY_MMIO_MIXER0_GROUP_NR 8u 5565 #define CY_MMIO_MIXER0_SLAVE_NR 4u 5566 /* MMIO8.MIXER1 */ 5567 #define CY_MMIO_MIXER1_GROUP_NR 8u 5568 #define CY_MMIO_MIXER1_SLAVE_NR 5u 5569 /* MMIO9.PASS0 */ 5570 #define CY_MMIO_PASS0_GROUP_NR 9u 5571 #define CY_MMIO_PASS0_SLAVE_NR 0u 5572 /* MMIO10.VIDEOSS_IP0 */ 5573 #define CY_MMIO_VIDEOSS_IP0_GROUP_NR 10u 5574 #define CY_MMIO_VIDEOSS_IP0_SLAVE_NR 0u 5575 /* MMIO10.VIDEOSS_PD0 */ 5576 #define CY_MMIO_VIDEOSS_PD0_GROUP_NR 10u 5577 #define CY_MMIO_VIDEOSS_PD0_SLAVE_NR 1u 5578 /* MMIO10.JPEGDEC */ 5579 #define CY_MMIO_JPEGDEC_GROUP_NR 10u 5580 #define CY_MMIO_JPEGDEC_SLAVE_NR 2u 5581 5582 /* Protection regions */ 5583 typedef enum 5584 { 5585 PROT_PERI_MAIN = 0, /* Address 0x40000200, size 0x00000040 */ 5586 PROT_PERI_SECURE = 1, /* Address 0x40002000, size 0x00000004 */ 5587 PROT_PERI_GR0_GROUP = 2, /* Address 0x40004010, size 0x00000004 */ 5588 PROT_PERI_GR1_GROUP = 3, /* Address 0x40004050, size 0x00000004 */ 5589 PROT_PERI_GR2_GROUP = 4, /* Address 0x40004090, size 0x00000004 */ 5590 PROT_PERI_GR3_GROUP = 5, /* Address 0x400040c0, size 0x00000020 */ 5591 PROT_PERI_GR4_GROUP = 6, /* Address 0x40004100, size 0x00000020 */ 5592 PROT_PERI_GR5_GROUP = 7, /* Address 0x40004140, size 0x00000020 */ 5593 PROT_PERI_GR6_GROUP = 8, /* Address 0x40004180, size 0x00000020 */ 5594 PROT_PERI_GR8_GROUP = 9, /* Address 0x40004200, size 0x00000020 */ 5595 PROT_PERI_GR9_GROUP = 10, /* Address 0x40004240, size 0x00000020 */ 5596 PROT_PERI_GR10_GROUP = 11, /* Address 0x40004280, size 0x00000020 */ 5597 PROT_PERI_GR0_BOOT = 12, /* Address 0x40004020, size 0x00000004 */ 5598 PROT_PERI_GR1_BOOT = 13, /* Address 0x40004060, size 0x00000004 */ 5599 PROT_PERI_GR2_BOOT = 14, /* Address 0x400040a0, size 0x00000004 */ 5600 PROT_PERI_GR3_BOOT = 15, /* Address 0x400040e0, size 0x00000004 */ 5601 PROT_PERI_GR4_BOOT = 16, /* Address 0x40004120, size 0x00000004 */ 5602 PROT_PERI_GR5_BOOT = 17, /* Address 0x40004160, size 0x00000004 */ 5603 PROT_PERI_GR6_BOOT = 18, /* Address 0x400041a0, size 0x00000004 */ 5604 PROT_PERI_GR8_BOOT = 19, /* Address 0x40004220, size 0x00000004 */ 5605 PROT_PERI_GR9_BOOT = 20, /* Address 0x40004260, size 0x00000004 */ 5606 PROT_PERI_GR10_BOOT = 21, /* Address 0x400042a0, size 0x00000004 */ 5607 PROT_PERI_TR = 22, /* Address 0x40008000, size 0x00008000 */ 5608 PROT_PERI_MS_BOOT = 23, /* Address 0x40030000, size 0x00001000 */ 5609 PROT_PERI_PCLK_MAIN = 24, /* Address 0x40040000, size 0x00004000 */ 5610 PROT_CRYPTO_MAIN = 25, /* Address 0x40100000, size 0x00000400 */ 5611 PROT_CRYPTO_CRYPTO = 26, /* Address 0x40101000, size 0x00000800 */ 5612 PROT_CRYPTO_BOOT = 27, /* Address 0x40102000, size 0x00000100 */ 5613 PROT_CRYPTO_KEY0 = 28, /* Address 0x40102100, size 0x00000004 */ 5614 PROT_CRYPTO_KEY1 = 29, /* Address 0x40102120, size 0x00000004 */ 5615 PROT_CRYPTO_BUF = 30, /* Address 0x40108000, size 0x00002000 */ 5616 PROT_CPUSS_CM7_0 = 31, /* Address 0x40200000, size 0x00000400 */ 5617 PROT_CPUSS_CM7_1 = 32, /* Address 0x40200400, size 0x00000400 */ 5618 PROT_CPUSS_CM0 = 33, /* Address 0x40201000, size 0x00001000 */ 5619 PROT_CPUSS_BOOT = 34, /* Address 0x40202000, size 0x00000200 */ 5620 PROT_CPUSS_CM0_INT = 35, /* Address 0x40208000, size 0x00001000 */ 5621 PROT_CPUSS_CM7_0_INT = 36, /* Address 0x4020a000, size 0x00001000 */ 5622 PROT_CPUSS_CM7_1_INT = 37, /* Address 0x4020c000, size 0x00001000 */ 5623 PROT_FAULT_STRUCT0_MAIN = 38, /* Address 0x40210000, size 0x00000100 */ 5624 PROT_FAULT_STRUCT1_MAIN = 39, /* Address 0x40210100, size 0x00000100 */ 5625 PROT_FAULT_STRUCT2_MAIN = 40, /* Address 0x40210200, size 0x00000100 */ 5626 PROT_FAULT_STRUCT3_MAIN = 41, /* Address 0x40210300, size 0x00000100 */ 5627 PROT_IPC_STRUCT0_IPC = 42, /* Address 0x40220000, size 0x00000020 */ 5628 PROT_IPC_STRUCT1_IPC = 43, /* Address 0x40220020, size 0x00000020 */ 5629 PROT_IPC_STRUCT2_IPC = 44, /* Address 0x40220040, size 0x00000020 */ 5630 PROT_IPC_STRUCT3_IPC = 45, /* Address 0x40220060, size 0x00000020 */ 5631 PROT_IPC_STRUCT4_IPC = 46, /* Address 0x40220080, size 0x00000020 */ 5632 PROT_IPC_STRUCT5_IPC = 47, /* Address 0x402200a0, size 0x00000020 */ 5633 PROT_IPC_STRUCT6_IPC = 48, /* Address 0x402200c0, size 0x00000020 */ 5634 PROT_IPC_STRUCT7_IPC = 49, /* Address 0x402200e0, size 0x00000020 */ 5635 PROT_IPC_INTR_STRUCT0_INTR = 50, /* Address 0x40221000, size 0x00000010 */ 5636 PROT_IPC_INTR_STRUCT1_INTR = 51, /* Address 0x40221020, size 0x00000010 */ 5637 PROT_IPC_INTR_STRUCT2_INTR = 52, /* Address 0x40221040, size 0x00000010 */ 5638 PROT_IPC_INTR_STRUCT3_INTR = 53, /* Address 0x40221060, size 0x00000010 */ 5639 PROT_IPC_INTR_STRUCT4_INTR = 54, /* Address 0x40221080, size 0x00000010 */ 5640 PROT_IPC_INTR_STRUCT5_INTR = 55, /* Address 0x402210a0, size 0x00000010 */ 5641 PROT_IPC_INTR_STRUCT6_INTR = 56, /* Address 0x402210c0, size 0x00000010 */ 5642 PROT_IPC_INTR_STRUCT7_INTR = 57, /* Address 0x402210e0, size 0x00000010 */ 5643 PROT_PROT_SMPU_MAIN = 58, /* Address 0x40230000, size 0x00000040 */ 5644 PROT_PROT_MPU0_MAIN = 59, /* Address 0x40234000, size 0x00000004 */ 5645 PROT_PROT_MPU9_MAIN = 60, /* Address 0x40236400, size 0x00000400 */ 5646 PROT_PROT_MPU10_MAIN = 61, /* Address 0x40236800, size 0x00000400 */ 5647 PROT_PROT_MPU11_MAIN = 62, /* Address 0x40236c00, size 0x00000004 */ 5648 PROT_PROT_MPU12_MAIN = 63, /* Address 0x40237000, size 0x00000400 */ 5649 PROT_PROT_MPU13_MAIN = 64, /* Address 0x40237400, size 0x00000004 */ 5650 PROT_PROT_MPU14_MAIN = 65, /* Address 0x40237800, size 0x00000004 */ 5651 PROT_PROT_MPU15_MAIN = 66, /* Address 0x40237c00, size 0x00000400 */ 5652 PROT_FLASHC_MAIN = 67, /* Address 0x40240000, size 0x00000008 */ 5653 PROT_FLASHC_CMD = 68, /* Address 0x40240008, size 0x00000004 */ 5654 PROT_FLASHC_DFT = 69, /* Address 0x40240200, size 0x00000100 */ 5655 PROT_FLASHC_CM0 = 70, /* Address 0x40240400, size 0x00000080 */ 5656 PROT_FLASHC_CM7_0 = 71, /* Address 0x402404e0, size 0x00000004 */ 5657 PROT_FLASHC_CM7_1 = 72, /* Address 0x40240560, size 0x00000004 */ 5658 PROT_FLASHC_CRYPTO = 73, /* Address 0x40240580, size 0x00000004 */ 5659 PROT_FLASHC_DW0 = 74, /* Address 0x40240600, size 0x00000004 */ 5660 PROT_FLASHC_DW1 = 75, /* Address 0x40240680, size 0x00000004 */ 5661 PROT_FLASHC_DMAC = 76, /* Address 0x40240700, size 0x00000004 */ 5662 PROT_FLASHC_FlashMgmt = 77, /* Address 0x4024f000, size 0x00000080 */ 5663 PROT_FLASHC_MainSafety = 78, /* Address 0x4024f400, size 0x00000008 */ 5664 PROT_FLASHC_WorkSafety = 79, /* Address 0x4024f500, size 0x00000004 */ 5665 PROT_SRSS_GENERAL = 80, /* Address 0x40260000, size 0x00000400 */ 5666 PROT_SRSS_MAIN = 81, /* Address 0x40261000, size 0x00001000 */ 5667 PROT_SRSS_SECURE = 82, /* Address 0x40262000, size 0x00002000 */ 5668 PROT_MCWDT0_CONFIG = 83, /* Address 0x40268000, size 0x00000080 */ 5669 PROT_MCWDT1_CONFIG = 84, /* Address 0x40268100, size 0x00000080 */ 5670 PROT_MCWDT2_CONFIG = 85, /* Address 0x40268200, size 0x00000080 */ 5671 PROT_MCWDT0_MAIN = 86, /* Address 0x40268080, size 0x00000040 */ 5672 PROT_MCWDT1_MAIN = 87, /* Address 0x40268180, size 0x00000040 */ 5673 PROT_MCWDT2_MAIN = 88, /* Address 0x40268280, size 0x00000040 */ 5674 PROT_WDT_CONFIG = 89, /* Address 0x4026c000, size 0x00000020 */ 5675 PROT_WDT_MAIN = 90, /* Address 0x4026c040, size 0x00000020 */ 5676 PROT_BACKUP_BACKUP = 91, /* Address 0x40270000, size 0x00010000 */ 5677 PROT_DW0_DW = 92, /* Address 0x40280000, size 0x00000100 */ 5678 PROT_DW1_DW = 93, /* Address 0x40290000, size 0x00000100 */ 5679 PROT_DW0_DW_CRC = 94, /* Address 0x40280100, size 0x00000080 */ 5680 PROT_DW1_DW_CRC = 95, /* Address 0x40290100, size 0x00000080 */ 5681 PROT_DW0_CH_STRUCT0_CH = 96, /* Address 0x40288000, size 0x00000040 */ 5682 PROT_DW0_CH_STRUCT1_CH = 97, /* Address 0x40288040, size 0x00000040 */ 5683 PROT_DW0_CH_STRUCT2_CH = 98, /* Address 0x40288080, size 0x00000040 */ 5684 PROT_DW0_CH_STRUCT3_CH = 99, /* Address 0x402880c0, size 0x00000040 */ 5685 PROT_DW0_CH_STRUCT4_CH = 100, /* Address 0x40288100, size 0x00000040 */ 5686 PROT_DW0_CH_STRUCT5_CH = 101, /* Address 0x40288140, size 0x00000040 */ 5687 PROT_DW0_CH_STRUCT6_CH = 102, /* Address 0x40288180, size 0x00000040 */ 5688 PROT_DW0_CH_STRUCT7_CH = 103, /* Address 0x402881c0, size 0x00000040 */ 5689 PROT_DW0_CH_STRUCT8_CH = 104, /* Address 0x40288200, size 0x00000040 */ 5690 PROT_DW0_CH_STRUCT9_CH = 105, /* Address 0x40288240, size 0x00000040 */ 5691 PROT_DW0_CH_STRUCT10_CH = 106, /* Address 0x40288280, size 0x00000040 */ 5692 PROT_DW0_CH_STRUCT11_CH = 107, /* Address 0x402882c0, size 0x00000040 */ 5693 PROT_DW0_CH_STRUCT12_CH = 108, /* Address 0x40288300, size 0x00000040 */ 5694 PROT_DW0_CH_STRUCT13_CH = 109, /* Address 0x40288340, size 0x00000040 */ 5695 PROT_DW0_CH_STRUCT14_CH = 110, /* Address 0x40288380, size 0x00000040 */ 5696 PROT_DW0_CH_STRUCT15_CH = 111, /* Address 0x402883c0, size 0x00000040 */ 5697 PROT_DW0_CH_STRUCT16_CH = 112, /* Address 0x40288400, size 0x00000040 */ 5698 PROT_DW0_CH_STRUCT17_CH = 113, /* Address 0x40288440, size 0x00000040 */ 5699 PROT_DW0_CH_STRUCT18_CH = 114, /* Address 0x40288480, size 0x00000040 */ 5700 PROT_DW0_CH_STRUCT19_CH = 115, /* Address 0x402884c0, size 0x00000040 */ 5701 PROT_DW0_CH_STRUCT20_CH = 116, /* Address 0x40288500, size 0x00000040 */ 5702 PROT_DW0_CH_STRUCT21_CH = 117, /* Address 0x40288540, size 0x00000040 */ 5703 PROT_DW0_CH_STRUCT22_CH = 118, /* Address 0x40288580, size 0x00000040 */ 5704 PROT_DW0_CH_STRUCT23_CH = 119, /* Address 0x402885c0, size 0x00000040 */ 5705 PROT_DW0_CH_STRUCT24_CH = 120, /* Address 0x40288600, size 0x00000040 */ 5706 PROT_DW0_CH_STRUCT25_CH = 121, /* Address 0x40288640, size 0x00000040 */ 5707 PROT_DW0_CH_STRUCT26_CH = 122, /* Address 0x40288680, size 0x00000040 */ 5708 PROT_DW0_CH_STRUCT27_CH = 123, /* Address 0x402886c0, size 0x00000040 */ 5709 PROT_DW0_CH_STRUCT28_CH = 124, /* Address 0x40288700, size 0x00000040 */ 5710 PROT_DW0_CH_STRUCT29_CH = 125, /* Address 0x40288740, size 0x00000040 */ 5711 PROT_DW0_CH_STRUCT30_CH = 126, /* Address 0x40288780, size 0x00000040 */ 5712 PROT_DW0_CH_STRUCT31_CH = 127, /* Address 0x402887c0, size 0x00000040 */ 5713 PROT_DW0_CH_STRUCT32_CH = 128, /* Address 0x40288800, size 0x00000040 */ 5714 PROT_DW0_CH_STRUCT33_CH = 129, /* Address 0x40288840, size 0x00000040 */ 5715 PROT_DW0_CH_STRUCT34_CH = 130, /* Address 0x40288880, size 0x00000040 */ 5716 PROT_DW0_CH_STRUCT35_CH = 131, /* Address 0x402888c0, size 0x00000040 */ 5717 PROT_DW0_CH_STRUCT36_CH = 132, /* Address 0x40288900, size 0x00000040 */ 5718 PROT_DW0_CH_STRUCT37_CH = 133, /* Address 0x40288940, size 0x00000040 */ 5719 PROT_DW0_CH_STRUCT38_CH = 134, /* Address 0x40288980, size 0x00000040 */ 5720 PROT_DW0_CH_STRUCT39_CH = 135, /* Address 0x402889c0, size 0x00000040 */ 5721 PROT_DW0_CH_STRUCT40_CH = 136, /* Address 0x40288a00, size 0x00000040 */ 5722 PROT_DW0_CH_STRUCT41_CH = 137, /* Address 0x40288a40, size 0x00000040 */ 5723 PROT_DW0_CH_STRUCT42_CH = 138, /* Address 0x40288a80, size 0x00000040 */ 5724 PROT_DW0_CH_STRUCT43_CH = 139, /* Address 0x40288ac0, size 0x00000040 */ 5725 PROT_DW0_CH_STRUCT44_CH = 140, /* Address 0x40288b00, size 0x00000040 */ 5726 PROT_DW0_CH_STRUCT45_CH = 141, /* Address 0x40288b40, size 0x00000040 */ 5727 PROT_DW0_CH_STRUCT46_CH = 142, /* Address 0x40288b80, size 0x00000040 */ 5728 PROT_DW0_CH_STRUCT47_CH = 143, /* Address 0x40288bc0, size 0x00000040 */ 5729 PROT_DW0_CH_STRUCT48_CH = 144, /* Address 0x40288c00, size 0x00000040 */ 5730 PROT_DW0_CH_STRUCT49_CH = 145, /* Address 0x40288c40, size 0x00000040 */ 5731 PROT_DW0_CH_STRUCT50_CH = 146, /* Address 0x40288c80, size 0x00000040 */ 5732 PROT_DW0_CH_STRUCT51_CH = 147, /* Address 0x40288cc0, size 0x00000040 */ 5733 PROT_DW0_CH_STRUCT52_CH = 148, /* Address 0x40288d00, size 0x00000040 */ 5734 PROT_DW0_CH_STRUCT53_CH = 149, /* Address 0x40288d40, size 0x00000040 */ 5735 PROT_DW0_CH_STRUCT54_CH = 150, /* Address 0x40288d80, size 0x00000040 */ 5736 PROT_DW0_CH_STRUCT55_CH = 151, /* Address 0x40288dc0, size 0x00000040 */ 5737 PROT_DW0_CH_STRUCT56_CH = 152, /* Address 0x40288e00, size 0x00000040 */ 5738 PROT_DW0_CH_STRUCT57_CH = 153, /* Address 0x40288e40, size 0x00000040 */ 5739 PROT_DW0_CH_STRUCT58_CH = 154, /* Address 0x40288e80, size 0x00000040 */ 5740 PROT_DW0_CH_STRUCT59_CH = 155, /* Address 0x40288ec0, size 0x00000040 */ 5741 PROT_DW0_CH_STRUCT60_CH = 156, /* Address 0x40288f00, size 0x00000040 */ 5742 PROT_DW0_CH_STRUCT61_CH = 157, /* Address 0x40288f40, size 0x00000040 */ 5743 PROT_DW0_CH_STRUCT62_CH = 158, /* Address 0x40288f80, size 0x00000040 */ 5744 PROT_DW0_CH_STRUCT63_CH = 159, /* Address 0x40288fc0, size 0x00000040 */ 5745 PROT_DW0_CH_STRUCT64_CH = 160, /* Address 0x40289000, size 0x00000040 */ 5746 PROT_DW0_CH_STRUCT65_CH = 161, /* Address 0x40289040, size 0x00000040 */ 5747 PROT_DW0_CH_STRUCT66_CH = 162, /* Address 0x40289080, size 0x00000040 */ 5748 PROT_DW0_CH_STRUCT67_CH = 163, /* Address 0x402890c0, size 0x00000040 */ 5749 PROT_DW0_CH_STRUCT68_CH = 164, /* Address 0x40289100, size 0x00000040 */ 5750 PROT_DW0_CH_STRUCT69_CH = 165, /* Address 0x40289140, size 0x00000040 */ 5751 PROT_DW0_CH_STRUCT70_CH = 166, /* Address 0x40289180, size 0x00000040 */ 5752 PROT_DW0_CH_STRUCT71_CH = 167, /* Address 0x402891c0, size 0x00000040 */ 5753 PROT_DW0_CH_STRUCT72_CH = 168, /* Address 0x40289200, size 0x00000040 */ 5754 PROT_DW0_CH_STRUCT73_CH = 169, /* Address 0x40289240, size 0x00000040 */ 5755 PROT_DW0_CH_STRUCT74_CH = 170, /* Address 0x40289280, size 0x00000040 */ 5756 PROT_DW0_CH_STRUCT75_CH = 171, /* Address 0x402892c0, size 0x00000040 */ 5757 PROT_DW1_CH_STRUCT0_CH = 172, /* Address 0x40298000, size 0x00000040 */ 5758 PROT_DW1_CH_STRUCT1_CH = 173, /* Address 0x40298040, size 0x00000040 */ 5759 PROT_DW1_CH_STRUCT2_CH = 174, /* Address 0x40298080, size 0x00000040 */ 5760 PROT_DW1_CH_STRUCT3_CH = 175, /* Address 0x402980c0, size 0x00000040 */ 5761 PROT_DW1_CH_STRUCT4_CH = 176, /* Address 0x40298100, size 0x00000040 */ 5762 PROT_DW1_CH_STRUCT5_CH = 177, /* Address 0x40298140, size 0x00000040 */ 5763 PROT_DW1_CH_STRUCT6_CH = 178, /* Address 0x40298180, size 0x00000040 */ 5764 PROT_DW1_CH_STRUCT7_CH = 179, /* Address 0x402981c0, size 0x00000040 */ 5765 PROT_DW1_CH_STRUCT8_CH = 180, /* Address 0x40298200, size 0x00000040 */ 5766 PROT_DW1_CH_STRUCT9_CH = 181, /* Address 0x40298240, size 0x00000040 */ 5767 PROT_DW1_CH_STRUCT10_CH = 182, /* Address 0x40298280, size 0x00000040 */ 5768 PROT_DW1_CH_STRUCT11_CH = 183, /* Address 0x402982c0, size 0x00000040 */ 5769 PROT_DW1_CH_STRUCT12_CH = 184, /* Address 0x40298300, size 0x00000040 */ 5770 PROT_DW1_CH_STRUCT13_CH = 185, /* Address 0x40298340, size 0x00000040 */ 5771 PROT_DW1_CH_STRUCT14_CH = 186, /* Address 0x40298380, size 0x00000040 */ 5772 PROT_DW1_CH_STRUCT15_CH = 187, /* Address 0x402983c0, size 0x00000040 */ 5773 PROT_DW1_CH_STRUCT16_CH = 188, /* Address 0x40298400, size 0x00000040 */ 5774 PROT_DW1_CH_STRUCT17_CH = 189, /* Address 0x40298440, size 0x00000040 */ 5775 PROT_DW1_CH_STRUCT18_CH = 190, /* Address 0x40298480, size 0x00000040 */ 5776 PROT_DW1_CH_STRUCT19_CH = 191, /* Address 0x402984c0, size 0x00000040 */ 5777 PROT_DW1_CH_STRUCT20_CH = 192, /* Address 0x40298500, size 0x00000040 */ 5778 PROT_DW1_CH_STRUCT21_CH = 193, /* Address 0x40298540, size 0x00000040 */ 5779 PROT_DW1_CH_STRUCT22_CH = 194, /* Address 0x40298580, size 0x00000040 */ 5780 PROT_DW1_CH_STRUCT23_CH = 195, /* Address 0x402985c0, size 0x00000040 */ 5781 PROT_DW1_CH_STRUCT24_CH = 196, /* Address 0x40298600, size 0x00000040 */ 5782 PROT_DW1_CH_STRUCT25_CH = 197, /* Address 0x40298640, size 0x00000040 */ 5783 PROT_DW1_CH_STRUCT26_CH = 198, /* Address 0x40298680, size 0x00000040 */ 5784 PROT_DW1_CH_STRUCT27_CH = 199, /* Address 0x402986c0, size 0x00000040 */ 5785 PROT_DW1_CH_STRUCT28_CH = 200, /* Address 0x40298700, size 0x00000040 */ 5786 PROT_DW1_CH_STRUCT29_CH = 201, /* Address 0x40298740, size 0x00000040 */ 5787 PROT_DW1_CH_STRUCT30_CH = 202, /* Address 0x40298780, size 0x00000040 */ 5788 PROT_DW1_CH_STRUCT31_CH = 203, /* Address 0x402987c0, size 0x00000040 */ 5789 PROT_DW1_CH_STRUCT32_CH = 204, /* Address 0x40298800, size 0x00000040 */ 5790 PROT_DW1_CH_STRUCT33_CH = 205, /* Address 0x40298840, size 0x00000040 */ 5791 PROT_DW1_CH_STRUCT34_CH = 206, /* Address 0x40298880, size 0x00000040 */ 5792 PROT_DW1_CH_STRUCT35_CH = 207, /* Address 0x402988c0, size 0x00000040 */ 5793 PROT_DW1_CH_STRUCT36_CH = 208, /* Address 0x40298900, size 0x00000040 */ 5794 PROT_DW1_CH_STRUCT37_CH = 209, /* Address 0x40298940, size 0x00000040 */ 5795 PROT_DW1_CH_STRUCT38_CH = 210, /* Address 0x40298980, size 0x00000040 */ 5796 PROT_DW1_CH_STRUCT39_CH = 211, /* Address 0x402989c0, size 0x00000040 */ 5797 PROT_DW1_CH_STRUCT40_CH = 212, /* Address 0x40298a00, size 0x00000040 */ 5798 PROT_DW1_CH_STRUCT41_CH = 213, /* Address 0x40298a40, size 0x00000040 */ 5799 PROT_DW1_CH_STRUCT42_CH = 214, /* Address 0x40298a80, size 0x00000040 */ 5800 PROT_DW1_CH_STRUCT43_CH = 215, /* Address 0x40298ac0, size 0x00000040 */ 5801 PROT_DW1_CH_STRUCT44_CH = 216, /* Address 0x40298b00, size 0x00000040 */ 5802 PROT_DW1_CH_STRUCT45_CH = 217, /* Address 0x40298b40, size 0x00000040 */ 5803 PROT_DW1_CH_STRUCT46_CH = 218, /* Address 0x40298b80, size 0x00000040 */ 5804 PROT_DW1_CH_STRUCT47_CH = 219, /* Address 0x40298bc0, size 0x00000040 */ 5805 PROT_DW1_CH_STRUCT48_CH = 220, /* Address 0x40298c00, size 0x00000040 */ 5806 PROT_DW1_CH_STRUCT49_CH = 221, /* Address 0x40298c40, size 0x00000040 */ 5807 PROT_DW1_CH_STRUCT50_CH = 222, /* Address 0x40298c80, size 0x00000040 */ 5808 PROT_DW1_CH_STRUCT51_CH = 223, /* Address 0x40298cc0, size 0x00000040 */ 5809 PROT_DW1_CH_STRUCT52_CH = 224, /* Address 0x40298d00, size 0x00000040 */ 5810 PROT_DW1_CH_STRUCT53_CH = 225, /* Address 0x40298d40, size 0x00000040 */ 5811 PROT_DW1_CH_STRUCT54_CH = 226, /* Address 0x40298d80, size 0x00000040 */ 5812 PROT_DW1_CH_STRUCT55_CH = 227, /* Address 0x40298dc0, size 0x00000040 */ 5813 PROT_DW1_CH_STRUCT56_CH = 228, /* Address 0x40298e00, size 0x00000040 */ 5814 PROT_DW1_CH_STRUCT57_CH = 229, /* Address 0x40298e40, size 0x00000040 */ 5815 PROT_DW1_CH_STRUCT58_CH = 230, /* Address 0x40298e80, size 0x00000040 */ 5816 PROT_DW1_CH_STRUCT59_CH = 231, /* Address 0x40298ec0, size 0x00000040 */ 5817 PROT_DW1_CH_STRUCT60_CH = 232, /* Address 0x40298f00, size 0x00000040 */ 5818 PROT_DW1_CH_STRUCT61_CH = 233, /* Address 0x40298f40, size 0x00000040 */ 5819 PROT_DW1_CH_STRUCT62_CH = 234, /* Address 0x40298f80, size 0x00000040 */ 5820 PROT_DW1_CH_STRUCT63_CH = 235, /* Address 0x40298fc0, size 0x00000040 */ 5821 PROT_DW1_CH_STRUCT64_CH = 236, /* Address 0x40299000, size 0x00000040 */ 5822 PROT_DW1_CH_STRUCT65_CH = 237, /* Address 0x40299040, size 0x00000040 */ 5823 PROT_DW1_CH_STRUCT66_CH = 238, /* Address 0x40299080, size 0x00000040 */ 5824 PROT_DW1_CH_STRUCT67_CH = 239, /* Address 0x402990c0, size 0x00000040 */ 5825 PROT_DW1_CH_STRUCT68_CH = 240, /* Address 0x40299100, size 0x00000040 */ 5826 PROT_DW1_CH_STRUCT69_CH = 241, /* Address 0x40299140, size 0x00000040 */ 5827 PROT_DW1_CH_STRUCT70_CH = 242, /* Address 0x40299180, size 0x00000040 */ 5828 PROT_DW1_CH_STRUCT71_CH = 243, /* Address 0x402991c0, size 0x00000040 */ 5829 PROT_DW1_CH_STRUCT72_CH = 244, /* Address 0x40299200, size 0x00000040 */ 5830 PROT_DW1_CH_STRUCT73_CH = 245, /* Address 0x40299240, size 0x00000040 */ 5831 PROT_DW1_CH_STRUCT74_CH = 246, /* Address 0x40299280, size 0x00000040 */ 5832 PROT_DW1_CH_STRUCT75_CH = 247, /* Address 0x402992c0, size 0x00000040 */ 5833 PROT_DW1_CH_STRUCT76_CH = 248, /* Address 0x40299300, size 0x00000040 */ 5834 PROT_DW1_CH_STRUCT77_CH = 249, /* Address 0x40299340, size 0x00000040 */ 5835 PROT_DW1_CH_STRUCT78_CH = 250, /* Address 0x40299380, size 0x00000040 */ 5836 PROT_DW1_CH_STRUCT79_CH = 251, /* Address 0x402993c0, size 0x00000040 */ 5837 PROT_DW1_CH_STRUCT80_CH = 252, /* Address 0x40299400, size 0x00000040 */ 5838 PROT_DW1_CH_STRUCT81_CH = 253, /* Address 0x40299440, size 0x00000040 */ 5839 PROT_DW1_CH_STRUCT82_CH = 254, /* Address 0x40299480, size 0x00000040 */ 5840 PROT_DW1_CH_STRUCT83_CH = 255, /* Address 0x402994c0, size 0x00000040 */ 5841 PROT_DMAC_TOP = 256, /* Address 0x402a0000, size 0x00000010 */ 5842 PROT_DMAC_CH0_CH = 257, /* Address 0x402a1000, size 0x00000100 */ 5843 PROT_DMAC_CH1_CH = 258, /* Address 0x402a1100, size 0x00000100 */ 5844 PROT_DMAC_CH2_CH = 259, /* Address 0x402a1200, size 0x00000100 */ 5845 PROT_DMAC_CH3_CH = 260, /* Address 0x402a1300, size 0x00000100 */ 5846 PROT_DMAC_CH4_CH = 261, /* Address 0x402a1400, size 0x00000100 */ 5847 PROT_DMAC_CH5_CH = 262, /* Address 0x402a1500, size 0x00000100 */ 5848 PROT_DMAC_CH6_CH = 263, /* Address 0x402a1600, size 0x00000100 */ 5849 PROT_DMAC_CH7_CH = 264, /* Address 0x402a1700, size 0x00000100 */ 5850 PROT_AXI_DMAC_TOP = 265, /* Address 0x402b0000, size 0x00000008 */ 5851 PROT_AXI_DMAC_SEC = 266, /* Address 0x402b0008, size 0x00000004 */ 5852 PROT_AXI_DMAC_NONSEC = 267, /* Address 0x402b000c, size 0x00000004 */ 5853 PROT_AXI_DMAC_CH0_CH = 268, /* Address 0x402b1000, size 0x00000100 */ 5854 PROT_AXI_DMAC_CH1_CH = 269, /* Address 0x402b1100, size 0x00000100 */ 5855 PROT_AXI_DMAC_CH2_CH = 270, /* Address 0x402b1200, size 0x00000100 */ 5856 PROT_AXI_DMAC_CH3_CH = 271, /* Address 0x402b1300, size 0x00000100 */ 5857 PROT_EFUSE_CTL = 272, /* Address 0x402c0000, size 0x00000200 */ 5858 PROT_EFUSE_DATA = 273, /* Address 0x402c0800, size 0x00000200 */ 5859 PROT_DFT = 274, /* Address 0x402f0000, size 0x00001000 */ 5860 PROT_HSIOM_PRT0_PRT = 275, /* Address 0x40300000, size 0x00000008 */ 5861 PROT_HSIOM_PRT1_PRT = 276, /* Address 0x40300010, size 0x00000008 */ 5862 PROT_HSIOM_PRT2_PRT = 277, /* Address 0x40300020, size 0x00000008 */ 5863 PROT_HSIOM_PRT3_PRT = 278, /* Address 0x40300030, size 0x00000008 */ 5864 PROT_HSIOM_PRT4_PRT = 279, /* Address 0x40300040, size 0x00000008 */ 5865 PROT_HSIOM_PRT5_PRT = 280, /* Address 0x40300050, size 0x00000008 */ 5866 PROT_HSIOM_PRT6_PRT = 281, /* Address 0x40300060, size 0x00000008 */ 5867 PROT_HSIOM_PRT7_PRT = 282, /* Address 0x40300070, size 0x00000008 */ 5868 PROT_HSIOM_PRT8_PRT = 283, /* Address 0x40300080, size 0x00000008 */ 5869 PROT_HSIOM_PRT9_PRT = 284, /* Address 0x40300090, size 0x00000008 */ 5870 PROT_HSIOM_PRT10_PRT = 285, /* Address 0x403000a0, size 0x00000008 */ 5871 PROT_HSIOM_PRT11_PRT = 286, /* Address 0x403000b0, size 0x00000008 */ 5872 PROT_HSIOM_PRT12_PRT = 287, /* Address 0x403000c0, size 0x00000008 */ 5873 PROT_HSIOM_PRT13_PRT = 288, /* Address 0x403000d0, size 0x00000008 */ 5874 PROT_HSIOM_PRT14_PRT = 289, /* Address 0x403000e0, size 0x00000008 */ 5875 PROT_HSIOM_PRT15_PRT = 290, /* Address 0x403000f0, size 0x00000008 */ 5876 PROT_HSIOM_PRT16_PRT = 291, /* Address 0x40300100, size 0x00000008 */ 5877 PROT_HSIOM_PRT17_PRT = 292, /* Address 0x40300110, size 0x00000008 */ 5878 PROT_HSIOM_PRT18_PRT = 293, /* Address 0x40300120, size 0x00000008 */ 5879 PROT_HSIOM_PRT19_PRT = 294, /* Address 0x40300130, size 0x00000008 */ 5880 PROT_HSIOM_PRT20_PRT = 295, /* Address 0x40300140, size 0x00000008 */ 5881 PROT_HSIOM_PRT21_PRT = 296, /* Address 0x40300150, size 0x00000008 */ 5882 PROT_HSIOM_PRT22_PRT = 297, /* Address 0x40300160, size 0x00000008 */ 5883 PROT_HSIOM_PRT23_PRT = 298, /* Address 0x40300170, size 0x00000008 */ 5884 PROT_HSIOM_PRT24_PRT = 299, /* Address 0x40300180, size 0x00000008 */ 5885 PROT_HSIOM_PRT25_PRT = 300, /* Address 0x40300190, size 0x00000008 */ 5886 PROT_HSIOM_PRT26_PRT = 301, /* Address 0x403001a0, size 0x00000008 */ 5887 PROT_HSIOM_PRT27_PRT = 302, /* Address 0x403001b0, size 0x00000008 */ 5888 PROT_HSIOM_PRT28_PRT = 303, /* Address 0x403001c0, size 0x00000008 */ 5889 PROT_HSIOM_PRT29_PRT = 304, /* Address 0x403001d0, size 0x00000008 */ 5890 PROT_HSIOM_PRT30_PRT = 305, /* Address 0x403001e0, size 0x00000008 */ 5891 PROT_HSIOM_AMUX = 306, /* Address 0x40302000, size 0x00000020 */ 5892 PROT_HSIOM_MON = 307, /* Address 0x40302200, size 0x00000010 */ 5893 PROT_GPIO_PRT0_PRT = 308, /* Address 0x40310000, size 0x00000040 */ 5894 PROT_GPIO_PRT1_PRT = 309, /* Address 0x40310080, size 0x00000040 */ 5895 PROT_GPIO_PRT2_PRT = 310, /* Address 0x40310100, size 0x00000040 */ 5896 PROT_GPIO_PRT3_PRT = 311, /* Address 0x40310180, size 0x00000040 */ 5897 PROT_GPIO_PRT4_PRT = 312, /* Address 0x40310200, size 0x00000040 */ 5898 PROT_GPIO_PRT5_PRT = 313, /* Address 0x40310280, size 0x00000040 */ 5899 PROT_GPIO_PRT6_PRT = 314, /* Address 0x40310300, size 0x00000040 */ 5900 PROT_GPIO_PRT7_PRT = 315, /* Address 0x40310380, size 0x00000040 */ 5901 PROT_GPIO_PRT8_PRT = 316, /* Address 0x40310400, size 0x00000040 */ 5902 PROT_GPIO_PRT9_PRT = 317, /* Address 0x40310480, size 0x00000040 */ 5903 PROT_GPIO_PRT10_PRT = 318, /* Address 0x40310500, size 0x00000040 */ 5904 PROT_GPIO_PRT11_PRT = 319, /* Address 0x40310580, size 0x00000040 */ 5905 PROT_GPIO_PRT12_PRT = 320, /* Address 0x40310600, size 0x00000040 */ 5906 PROT_GPIO_PRT13_PRT = 321, /* Address 0x40310680, size 0x00000040 */ 5907 PROT_GPIO_PRT14_PRT = 322, /* Address 0x40310700, size 0x00000040 */ 5908 PROT_GPIO_PRT15_PRT = 323, /* Address 0x40310780, size 0x00000040 */ 5909 PROT_GPIO_PRT16_PRT = 324, /* Address 0x40310800, size 0x00000040 */ 5910 PROT_GPIO_PRT17_PRT = 325, /* Address 0x40310880, size 0x00000040 */ 5911 PROT_GPIO_PRT18_PRT = 326, /* Address 0x40310900, size 0x00000040 */ 5912 PROT_GPIO_PRT19_PRT = 327, /* Address 0x40310980, size 0x00000040 */ 5913 PROT_GPIO_PRT20_PRT = 328, /* Address 0x40310a00, size 0x00000040 */ 5914 PROT_GPIO_PRT21_PRT = 329, /* Address 0x40310a80, size 0x00000040 */ 5915 PROT_GPIO_PRT22_PRT = 330, /* Address 0x40310b00, size 0x00000040 */ 5916 PROT_GPIO_PRT23_PRT = 331, /* Address 0x40310b80, size 0x00000040 */ 5917 PROT_GPIO_PRT24_PRT = 332, /* Address 0x40310c00, size 0x00000040 */ 5918 PROT_GPIO_PRT25_PRT = 333, /* Address 0x40310c80, size 0x00000040 */ 5919 PROT_GPIO_PRT26_PRT = 334, /* Address 0x40310d00, size 0x00000040 */ 5920 PROT_GPIO_PRT27_PRT = 335, /* Address 0x40310d80, size 0x00000040 */ 5921 PROT_GPIO_PRT28_PRT = 336, /* Address 0x40310e00, size 0x00000040 */ 5922 PROT_GPIO_PRT29_PRT = 337, /* Address 0x40310e80, size 0x00000040 */ 5923 PROT_GPIO_PRT30_PRT = 338, /* Address 0x40310f00, size 0x00000040 */ 5924 PROT_GPIO_PRT0_CFG = 339, /* Address 0x40310040, size 0x00000020 */ 5925 PROT_GPIO_PRT1_CFG = 340, /* Address 0x403100c0, size 0x00000020 */ 5926 PROT_GPIO_PRT2_CFG = 341, /* Address 0x40310140, size 0x00000020 */ 5927 PROT_GPIO_PRT3_CFG = 342, /* Address 0x403101c0, size 0x00000020 */ 5928 PROT_GPIO_PRT4_CFG = 343, /* Address 0x40310240, size 0x00000020 */ 5929 PROT_GPIO_PRT5_CFG = 344, /* Address 0x403102c0, size 0x00000020 */ 5930 PROT_GPIO_PRT6_CFG = 345, /* Address 0x40310340, size 0x00000020 */ 5931 PROT_GPIO_PRT7_CFG = 346, /* Address 0x403103c0, size 0x00000020 */ 5932 PROT_GPIO_PRT8_CFG = 347, /* Address 0x40310440, size 0x00000020 */ 5933 PROT_GPIO_PRT9_CFG = 348, /* Address 0x403104c0, size 0x00000020 */ 5934 PROT_GPIO_PRT10_CFG = 349, /* Address 0x40310540, size 0x00000020 */ 5935 PROT_GPIO_PRT11_CFG = 350, /* Address 0x403105c0, size 0x00000020 */ 5936 PROT_GPIO_PRT12_CFG = 351, /* Address 0x40310640, size 0x00000020 */ 5937 PROT_GPIO_PRT13_CFG = 352, /* Address 0x403106c0, size 0x00000020 */ 5938 PROT_GPIO_PRT14_CFG = 353, /* Address 0x40310740, size 0x00000020 */ 5939 PROT_GPIO_PRT15_CFG = 354, /* Address 0x403107c0, size 0x00000040 */ 5940 PROT_GPIO_PRT16_CFG = 355, /* Address 0x40310840, size 0x00000040 */ 5941 PROT_GPIO_PRT17_CFG = 356, /* Address 0x403108c0, size 0x00000040 */ 5942 PROT_GPIO_PRT18_CFG = 357, /* Address 0x40310940, size 0x00000040 */ 5943 PROT_GPIO_PRT19_CFG = 358, /* Address 0x403109c0, size 0x00000040 */ 5944 PROT_GPIO_PRT20_CFG = 359, /* Address 0x40310a40, size 0x00000040 */ 5945 PROT_GPIO_PRT21_CFG = 360, /* Address 0x40310ac0, size 0x00000040 */ 5946 PROT_GPIO_PRT22_CFG = 361, /* Address 0x40310b40, size 0x00000040 */ 5947 PROT_GPIO_PRT23_CFG = 362, /* Address 0x40310bc0, size 0x00000040 */ 5948 PROT_GPIO_PRT24_CFG = 363, /* Address 0x40310c40, size 0x00000040 */ 5949 PROT_GPIO_PRT25_CFG = 364, /* Address 0x40310cc0, size 0x00000040 */ 5950 PROT_GPIO_PRT26_CFG = 365, /* Address 0x40310d40, size 0x00000040 */ 5951 PROT_GPIO_PRT27_CFG = 366, /* Address 0x40310dc0, size 0x00000040 */ 5952 PROT_GPIO_PRT28_CFG = 367, /* Address 0x40310e40, size 0x00000040 */ 5953 PROT_GPIO_PRT29_CFG = 368, /* Address 0x40310ec0, size 0x00000020 */ 5954 PROT_GPIO_PRT30_CFG = 369, /* Address 0x40310f40, size 0x00000020 */ 5955 PROT_GPIO_GPIO = 370, /* Address 0x40314000, size 0x00000040 */ 5956 PROT_GPIO_TEST = 371, /* Address 0x40315000, size 0x00000008 */ 5957 PROT_SMARTIO_PRT7_PRT = 372, /* Address 0x40320700, size 0x00000100 */ 5958 PROT_TCPWM0_GRP0_CNT0_CNT = 373, /* Address 0x40380000, size 0x00000080 */ 5959 PROT_TCPWM0_GRP0_CNT1_CNT = 374, /* Address 0x40380080, size 0x00000080 */ 5960 PROT_TCPWM0_GRP0_CNT2_CNT = 375, /* Address 0x40380100, size 0x00000080 */ 5961 PROT_TCPWM0_GRP0_CNT3_CNT = 376, /* Address 0x40380180, size 0x00000080 */ 5962 PROT_TCPWM0_GRP0_CNT4_CNT = 377, /* Address 0x40380200, size 0x00000080 */ 5963 PROT_TCPWM0_GRP0_CNT5_CNT = 378, /* Address 0x40380280, size 0x00000080 */ 5964 PROT_TCPWM0_GRP0_CNT6_CNT = 379, /* Address 0x40380300, size 0x00000080 */ 5965 PROT_TCPWM0_GRP0_CNT7_CNT = 380, /* Address 0x40380380, size 0x00000080 */ 5966 PROT_TCPWM0_GRP0_CNT8_CNT = 381, /* Address 0x40380400, size 0x00000080 */ 5967 PROT_TCPWM0_GRP0_CNT9_CNT = 382, /* Address 0x40380480, size 0x00000080 */ 5968 PROT_TCPWM0_GRP0_CNT10_CNT = 383, /* Address 0x40380500, size 0x00000080 */ 5969 PROT_TCPWM0_GRP0_CNT11_CNT = 384, /* Address 0x40380580, size 0x00000080 */ 5970 PROT_TCPWM0_GRP0_CNT12_CNT = 385, /* Address 0x40380600, size 0x00000080 */ 5971 PROT_TCPWM0_GRP0_CNT13_CNT = 386, /* Address 0x40380680, size 0x00000080 */ 5972 PROT_TCPWM0_GRP0_CNT14_CNT = 387, /* Address 0x40380700, size 0x00000080 */ 5973 PROT_TCPWM0_GRP0_CNT15_CNT = 388, /* Address 0x40380780, size 0x00000080 */ 5974 PROT_TCPWM0_GRP0_CNT16_CNT = 389, /* Address 0x40380800, size 0x00000080 */ 5975 PROT_TCPWM0_GRP0_CNT17_CNT = 390, /* Address 0x40380880, size 0x00000080 */ 5976 PROT_TCPWM0_GRP0_CNT18_CNT = 391, /* Address 0x40380900, size 0x00000080 */ 5977 PROT_TCPWM0_GRP0_CNT19_CNT = 392, /* Address 0x40380980, size 0x00000080 */ 5978 PROT_TCPWM0_GRP0_CNT20_CNT = 393, /* Address 0x40380a00, size 0x00000080 */ 5979 PROT_TCPWM0_GRP0_CNT21_CNT = 394, /* Address 0x40380a80, size 0x00000080 */ 5980 PROT_TCPWM0_GRP0_CNT22_CNT = 395, /* Address 0x40380b00, size 0x00000080 */ 5981 PROT_TCPWM0_GRP0_CNT23_CNT = 396, /* Address 0x40380b80, size 0x00000080 */ 5982 PROT_TCPWM0_GRP0_CNT24_CNT = 397, /* Address 0x40380c00, size 0x00000080 */ 5983 PROT_TCPWM0_GRP0_CNT25_CNT = 398, /* Address 0x40380c80, size 0x00000080 */ 5984 PROT_TCPWM0_GRP0_CNT26_CNT = 399, /* Address 0x40380d00, size 0x00000080 */ 5985 PROT_TCPWM0_GRP0_CNT27_CNT = 400, /* Address 0x40380d80, size 0x00000080 */ 5986 PROT_TCPWM0_GRP0_CNT28_CNT = 401, /* Address 0x40380e00, size 0x00000080 */ 5987 PROT_TCPWM0_GRP0_CNT29_CNT = 402, /* Address 0x40380e80, size 0x00000080 */ 5988 PROT_TCPWM0_GRP0_CNT30_CNT = 403, /* Address 0x40380f00, size 0x00000080 */ 5989 PROT_TCPWM0_GRP0_CNT31_CNT = 404, /* Address 0x40380f80, size 0x00000080 */ 5990 PROT_TCPWM0_GRP0_CNT32_CNT = 405, /* Address 0x40381000, size 0x00000080 */ 5991 PROT_TCPWM0_GRP0_CNT33_CNT = 406, /* Address 0x40381080, size 0x00000080 */ 5992 PROT_TCPWM0_GRP0_CNT34_CNT = 407, /* Address 0x40381100, size 0x00000080 */ 5993 PROT_TCPWM0_GRP0_CNT35_CNT = 408, /* Address 0x40381180, size 0x00000080 */ 5994 PROT_TCPWM0_GRP0_CNT36_CNT = 409, /* Address 0x40381200, size 0x00000080 */ 5995 PROT_TCPWM0_GRP0_CNT37_CNT = 410, /* Address 0x40381280, size 0x00000080 */ 5996 PROT_TCPWM0_GRP1_CNT0_CNT = 411, /* Address 0x40388000, size 0x00000080 */ 5997 PROT_TCPWM0_GRP1_CNT1_CNT = 412, /* Address 0x40388080, size 0x00000080 */ 5998 PROT_TCPWM0_GRP1_CNT2_CNT = 413, /* Address 0x40388100, size 0x00000080 */ 5999 PROT_TCPWM0_GRP1_CNT3_CNT = 414, /* Address 0x40388180, size 0x00000080 */ 6000 PROT_TCPWM0_GRP1_CNT4_CNT = 415, /* Address 0x40388200, size 0x00000080 */ 6001 PROT_TCPWM0_GRP1_CNT5_CNT = 416, /* Address 0x40388280, size 0x00000080 */ 6002 PROT_TCPWM0_GRP1_CNT6_CNT = 417, /* Address 0x40388300, size 0x00000080 */ 6003 PROT_TCPWM0_GRP1_CNT7_CNT = 418, /* Address 0x40388380, size 0x00000080 */ 6004 PROT_TCPWM0_GRP1_CNT8_CNT = 419, /* Address 0x40388400, size 0x00000080 */ 6005 PROT_TCPWM0_GRP1_CNT9_CNT = 420, /* Address 0x40388480, size 0x00000080 */ 6006 PROT_TCPWM0_GRP1_CNT10_CNT = 421, /* Address 0x40388500, size 0x00000080 */ 6007 PROT_TCPWM0_GRP1_CNT11_CNT = 422, /* Address 0x40388580, size 0x00000080 */ 6008 PROT_TCPWM0_GRP2_CNT0_CNT = 423, /* Address 0x40390000, size 0x00000080 */ 6009 PROT_TCPWM0_GRP2_CNT1_CNT = 424, /* Address 0x40390080, size 0x00000080 */ 6010 PROT_TCPWM0_GRP2_CNT2_CNT = 425, /* Address 0x40390100, size 0x00000080 */ 6011 PROT_TCPWM0_GRP2_CNT3_CNT = 426, /* Address 0x40390180, size 0x00000080 */ 6012 PROT_TCPWM0_GRP2_CNT4_CNT = 427, /* Address 0x40390200, size 0x00000080 */ 6013 PROT_TCPWM0_GRP2_CNT5_CNT = 428, /* Address 0x40390280, size 0x00000080 */ 6014 PROT_TCPWM0_GRP2_CNT6_CNT = 429, /* Address 0x40390300, size 0x00000080 */ 6015 PROT_TCPWM0_GRP2_CNT7_CNT = 430, /* Address 0x40390380, size 0x00000080 */ 6016 PROT_TCPWM0_GRP2_CNT8_CNT = 431, /* Address 0x40390400, size 0x00000080 */ 6017 PROT_TCPWM0_GRP2_CNT9_CNT = 432, /* Address 0x40390480, size 0x00000080 */ 6018 PROT_TCPWM0_GRP2_CNT10_CNT = 433, /* Address 0x40390500, size 0x00000080 */ 6019 PROT_TCPWM0_GRP2_CNT11_CNT = 434, /* Address 0x40390580, size 0x00000080 */ 6020 PROT_TCPWM0_GRP2_CNT12_CNT = 435, /* Address 0x40390600, size 0x00000080 */ 6021 PROT_TCPWM0_GRP2_CNT13_CNT = 436, /* Address 0x40390680, size 0x00000080 */ 6022 PROT_TCPWM0_GRP2_CNT14_CNT = 437, /* Address 0x40390700, size 0x00000080 */ 6023 PROT_TCPWM0_GRP2_CNT15_CNT = 438, /* Address 0x40390780, size 0x00000080 */ 6024 PROT_TCPWM0_GRP2_CNT16_CNT = 439, /* Address 0x40390800, size 0x00000080 */ 6025 PROT_TCPWM0_GRP2_CNT17_CNT = 440, /* Address 0x40390880, size 0x00000080 */ 6026 PROT_TCPWM0_GRP2_CNT18_CNT = 441, /* Address 0x40390900, size 0x00000080 */ 6027 PROT_TCPWM0_GRP2_CNT19_CNT = 442, /* Address 0x40390980, size 0x00000080 */ 6028 PROT_TCPWM0_GRP2_CNT20_CNT = 443, /* Address 0x40390a00, size 0x00000080 */ 6029 PROT_TCPWM0_GRP2_CNT21_CNT = 444, /* Address 0x40390a80, size 0x00000080 */ 6030 PROT_TCPWM0_GRP2_CNT22_CNT = 445, /* Address 0x40390b00, size 0x00000080 */ 6031 PROT_TCPWM0_GRP2_CNT23_CNT = 446, /* Address 0x40390b80, size 0x00000080 */ 6032 PROT_TCPWM0_GRP2_CNT24_CNT = 447, /* Address 0x40390c00, size 0x00000080 */ 6033 PROT_TCPWM0_GRP2_CNT25_CNT = 448, /* Address 0x40390c80, size 0x00000080 */ 6034 PROT_TCPWM0_GRP2_CNT26_CNT = 449, /* Address 0x40390d00, size 0x00000080 */ 6035 PROT_TCPWM0_GRP2_CNT27_CNT = 450, /* Address 0x40390d80, size 0x00000080 */ 6036 PROT_TCPWM0_GRP2_CNT28_CNT = 451, /* Address 0x40390e00, size 0x00000080 */ 6037 PROT_TCPWM0_GRP2_CNT29_CNT = 452, /* Address 0x40390e80, size 0x00000080 */ 6038 PROT_TCPWM0_GRP2_CNT30_CNT = 453, /* Address 0x40390f00, size 0x00000080 */ 6039 PROT_TCPWM0_GRP2_CNT31_CNT = 454, /* Address 0x40390f80, size 0x00000080 */ 6040 PROT_EVTGEN0 = 455, /* Address 0x403f0000, size 0x00001000 */ 6041 PROT_SMIF0_MAIN = 456, /* Address 0x40400000, size 0x00040000 */ 6042 PROT_ETH0 = 457, /* Address 0x40480000, size 0x00010000 */ 6043 PROT_LIN0_MAIN = 458, /* Address 0x40500000, size 0x00000008 */ 6044 PROT_LIN0_CH0_CH = 459, /* Address 0x40508000, size 0x00000100 */ 6045 PROT_LIN0_CH1_CH = 460, /* Address 0x40508100, size 0x00000100 */ 6046 PROT_CXPI0_MAIN = 461, /* Address 0x40510000, size 0x00000008 */ 6047 PROT_CXPI0_CH0_CH = 462, /* Address 0x40518000, size 0x00000100 */ 6048 PROT_CXPI0_CH1_CH = 463, /* Address 0x40518100, size 0x00000100 */ 6049 PROT_CANFD0_CH0_CH = 464, /* Address 0x40520000, size 0x00000200 */ 6050 PROT_CANFD0_CH1_CH = 465, /* Address 0x40520200, size 0x00000200 */ 6051 PROT_CANFD1_CH0_CH = 466, /* Address 0x40540000, size 0x00000200 */ 6052 PROT_CANFD1_CH1_CH = 467, /* Address 0x40540200, size 0x00000200 */ 6053 PROT_CANFD0_MAIN = 468, /* Address 0x40521000, size 0x00000100 */ 6054 PROT_CANFD1_MAIN = 469, /* Address 0x40541000, size 0x00000100 */ 6055 PROT_CANFD0_BUF = 470, /* Address 0x40530000, size 0x00010000 */ 6056 PROT_CANFD1_BUF = 471, /* Address 0x40550000, size 0x00010000 */ 6057 PROT_SCB0 = 472, /* Address 0x40600000, size 0x00010000 */ 6058 PROT_SCB1 = 473, /* Address 0x40610000, size 0x00010000 */ 6059 PROT_SCB2 = 474, /* Address 0x40620000, size 0x00010000 */ 6060 PROT_SCB3 = 475, /* Address 0x40630000, size 0x00010000 */ 6061 PROT_SCB4 = 476, /* Address 0x40640000, size 0x00010000 */ 6062 PROT_SCB5 = 477, /* Address 0x40650000, size 0x00010000 */ 6063 PROT_SCB6 = 478, /* Address 0x40660000, size 0x00010000 */ 6064 PROT_SCB7 = 479, /* Address 0x40670000, size 0x00010000 */ 6065 PROT_SCB8 = 480, /* Address 0x40680000, size 0x00010000 */ 6066 PROT_SCB9 = 481, /* Address 0x40690000, size 0x00010000 */ 6067 PROT_SCB10 = 482, /* Address 0x406a0000, size 0x00010000 */ 6068 PROT_SCB11 = 483, /* Address 0x406b0000, size 0x00010000 */ 6069 PROT_TDM0_TDM_STRUCT0_TDM_TX_STRUCT_TX = 484, /* Address 0x40818000, size 0x00000100 */ 6070 PROT_TDM0_TDM_STRUCT1_TDM_TX_STRUCT_TX = 485, /* Address 0x40818200, size 0x00000100 */ 6071 PROT_TDM0_TDM_STRUCT2_TDM_TX_STRUCT_TX = 486, /* Address 0x40818400, size 0x00000100 */ 6072 PROT_TDM0_TDM_STRUCT3_TDM_TX_STRUCT_TX = 487, /* Address 0x40818600, size 0x00000100 */ 6073 PROT_TDM0_TDM_STRUCT0_TDM_RX_STRUCT_RX = 488, /* Address 0x40818100, size 0x00000100 */ 6074 PROT_TDM0_TDM_STRUCT1_TDM_RX_STRUCT_RX = 489, /* Address 0x40818300, size 0x00000100 */ 6075 PROT_TDM0_TDM_STRUCT2_TDM_RX_STRUCT_RX = 490, /* Address 0x40818500, size 0x00000100 */ 6076 PROT_TDM0_TDM_STRUCT3_TDM_RX_STRUCT_RX = 491, /* Address 0x40818700, size 0x00000100 */ 6077 PROT_SG0_SG_STRUCT0_TX = 492, /* Address 0x40828000, size 0x00000100 */ 6078 PROT_SG0_SG_STRUCT1_TX = 493, /* Address 0x40828100, size 0x00000100 */ 6079 PROT_SG0_SG_STRUCT2_TX = 494, /* Address 0x40828200, size 0x00000100 */ 6080 PROT_SG0_SG_STRUCT3_TX = 495, /* Address 0x40828300, size 0x00000100 */ 6081 PROT_SG0_SG_STRUCT4_TX = 496, /* Address 0x40828400, size 0x00000100 */ 6082 PROT_PWM0_MAIN = 497, /* Address 0x40830000, size 0x00000010 */ 6083 PROT_PWM0_TX0_TX = 498, /* Address 0x40838000, size 0x00000100 */ 6084 PROT_PWM0_TX1_TX = 499, /* Address 0x40838100, size 0x00000100 */ 6085 PROT_DAC0_MAIN = 500, /* Address 0x40840000, size 0x00000100 */ 6086 PROT_MIXER0_MIXER_SRC_STRUCT0_SRC = 501, /* Address 0x40888000, size 0x00000100 */ 6087 PROT_MIXER0_MIXER_SRC_STRUCT1_SRC = 502, /* Address 0x40888100, size 0x00000100 */ 6088 PROT_MIXER0_MIXER_SRC_STRUCT2_SRC = 503, /* Address 0x40888200, size 0x00000100 */ 6089 PROT_MIXER0_MIXER_SRC_STRUCT3_SRC = 504, /* Address 0x40888300, size 0x00000100 */ 6090 PROT_MIXER0_MIXER_SRC_STRUCT4_SRC = 505, /* Address 0x40888400, size 0x00000100 */ 6091 PROT_MIXER1_MIXER_SRC_STRUCT0_SRC = 506, /* Address 0x40898000, size 0x00000100 */ 6092 PROT_MIXER1_MIXER_SRC_STRUCT1_SRC = 507, /* Address 0x40898100, size 0x00000100 */ 6093 PROT_MIXER1_MIXER_SRC_STRUCT2_SRC = 508, /* Address 0x40898200, size 0x00000100 */ 6094 PROT_MIXER1_MIXER_SRC_STRUCT3_SRC = 509, /* Address 0x40898300, size 0x00000100 */ 6095 PROT_MIXER1_MIXER_SRC_STRUCT4_SRC = 510, /* Address 0x40898400, size 0x00000100 */ 6096 PROT_MIXER0_MIXER_DST_STRUCT_DST = 511, /* Address 0x4088c000, size 0x00000100 */ 6097 PROT_MIXER1_MIXER_DST_STRUCT_DST = 512, /* Address 0x4089c000, size 0x00000100 */ 6098 PROT_PASS0_SAR0_SAR = 513, /* Address 0x40900000, size 0x00000400 */ 6099 PROT_PASS0_SAR1_SAR = 514, /* Address 0x40901000, size 0x00000008 */ 6100 PROT_PASS0_SAR0_CH0_CH = 515, /* Address 0x40900800, size 0x00000040 */ 6101 PROT_PASS0_SAR0_CH1_CH = 516, /* Address 0x40900840, size 0x00000040 */ 6102 PROT_PASS0_SAR0_CH2_CH = 517, /* Address 0x40900880, size 0x00000040 */ 6103 PROT_PASS0_SAR0_CH3_CH = 518, /* Address 0x409008c0, size 0x00000040 */ 6104 PROT_PASS0_SAR0_CH4_CH = 519, /* Address 0x40900900, size 0x00000040 */ 6105 PROT_PASS0_SAR0_CH5_CH = 520, /* Address 0x40900940, size 0x00000040 */ 6106 PROT_PASS0_SAR0_CH6_CH = 521, /* Address 0x40900980, size 0x00000040 */ 6107 PROT_PASS0_SAR0_CH7_CH = 522, /* Address 0x409009c0, size 0x00000040 */ 6108 PROT_PASS0_SAR0_CH8_CH = 523, /* Address 0x40900a00, size 0x00000040 */ 6109 PROT_PASS0_SAR0_CH9_CH = 524, /* Address 0x40900a40, size 0x00000040 */ 6110 PROT_PASS0_SAR0_CH10_CH = 525, /* Address 0x40900a80, size 0x00000040 */ 6111 PROT_PASS0_SAR0_CH11_CH = 526, /* Address 0x40900ac0, size 0x00000040 */ 6112 PROT_PASS0_SAR0_CH12_CH = 527, /* Address 0x40900b00, size 0x00000040 */ 6113 PROT_PASS0_SAR0_CH13_CH = 528, /* Address 0x40900b40, size 0x00000040 */ 6114 PROT_PASS0_SAR0_CH14_CH = 529, /* Address 0x40900b80, size 0x00000040 */ 6115 PROT_PASS0_SAR0_CH15_CH = 530, /* Address 0x40900bc0, size 0x00000040 */ 6116 PROT_PASS0_SAR0_CH16_CH = 531, /* Address 0x40900c00, size 0x00000040 */ 6117 PROT_PASS0_SAR0_CH17_CH = 532, /* Address 0x40900c40, size 0x00000040 */ 6118 PROT_PASS0_SAR0_CH18_CH = 533, /* Address 0x40900c80, size 0x00000040 */ 6119 PROT_PASS0_SAR0_CH19_CH = 534, /* Address 0x40900cc0, size 0x00000040 */ 6120 PROT_PASS0_SAR0_CH20_CH = 535, /* Address 0x40900d00, size 0x00000040 */ 6121 PROT_PASS0_SAR0_CH21_CH = 536, /* Address 0x40900d40, size 0x00000040 */ 6122 PROT_PASS0_SAR0_CH22_CH = 537, /* Address 0x40900d80, size 0x00000040 */ 6123 PROT_PASS0_SAR0_CH23_CH = 538, /* Address 0x40900dc0, size 0x00000040 */ 6124 PROT_PASS0_SAR0_CH24_CH = 539, /* Address 0x40900e00, size 0x00000040 */ 6125 PROT_PASS0_SAR0_CH25_CH = 540, /* Address 0x40900e40, size 0x00000040 */ 6126 PROT_PASS0_SAR0_CH26_CH = 541, /* Address 0x40900e80, size 0x00000040 */ 6127 PROT_PASS0_SAR0_CH27_CH = 542, /* Address 0x40900ec0, size 0x00000040 */ 6128 PROT_PASS0_SAR0_CH28_CH = 543, /* Address 0x40900f00, size 0x00000040 */ 6129 PROT_PASS0_SAR0_CH29_CH = 544, /* Address 0x40900f40, size 0x00000040 */ 6130 PROT_PASS0_SAR0_CH30_CH = 545, /* Address 0x40900f80, size 0x00000040 */ 6131 PROT_PASS0_SAR0_CH31_CH = 546, /* Address 0x40900fc0, size 0x00000040 */ 6132 PROT_PASS0_TOP = 547, /* Address 0x409f0000, size 0x00001000 */ 6133 PROT_VIDEOSS0_VCFG_VIDEOSSCFG = 548, /* Address 0x40a00000, size 0x00000400 */ 6134 PROT_VIDEOSS0_VCFG_VRAM = 549, /* Address 0x40a00400, size 0x00000400 */ 6135 PROT_VIDEOSS0_GPU_GFX2D = 550, /* Address 0x40a40000, size 0x00040000 */ 6136 PROT_VIDEOSS0_VIDEOIOCFG_VIRQ_VIDEOIOCFG = 551, /* Address 0x40a80020, size 0x00000020 */ 6137 PROT_VIDEOSS0_CAPIFC0_FRAMEDUMP = 552, /* Address 0x40a80400, size 0x00000400 */ 6138 PROT_VIDEOSS0_CAPIFC0_CAPENG0 = 553, /* Address 0x40a81000, size 0x00001000 */ 6139 PROT_VIDEOSS0_DSPCFG_COMPENGCFG = 554, /* Address 0x40a90000, size 0x00002000 */ 6140 PROT_VIDEOSS0_DSPSEC0_CONSTFRAME0 = 555, /* Address 0x40a92000, size 0x00000400 */ 6141 PROT_VIDEOSS0_DSPSEC0_EXTDST0 = 556, /* Address 0x40a92400, size 0x00000400 */ 6142 PROT_VIDEOSS0_DSPPRIM0_CONSTFRAME4 = 557, /* Address 0x40a92800, size 0x00000400 */ 6143 PROT_VIDEOSS0_DSPPRIM0_EXTDST4 = 558, /* Address 0x40a92c00, size 0x00000400 */ 6144 PROT_VIDEOSS0_DSPSEC1_CONSTFRAME1 = 559, /* Address 0x40a93000, size 0x00000400 */ 6145 PROT_VIDEOSS0_DSPSEC1_EXTDST1 = 560, /* Address 0x40a93400, size 0x00000400 */ 6146 PROT_VIDEOSS0_DSPPRIM1_CONSTFRAME5 = 561, /* Address 0x40a93800, size 0x00000400 */ 6147 PROT_VIDEOSS0_DSPPRIM1_EXTDST5 = 562, /* Address 0x40a93c00, size 0x00000400 */ 6148 PROT_VIDEOSS0_CAPIFC0_EXTSRC4 = 563, /* Address 0x40a94000, size 0x00000400 */ 6149 PROT_VIDEOSS0_CAPIFC0_STORE4 = 564, /* Address 0x40a94400, size 0x00000400 */ 6150 PROT_VIDEOSS0_DSPLAYER1_FETCHLAYER0 = 565, /* Address 0x40a94800, size 0x00000400 */ 6151 PROT_VIDEOSS0_DSPLAYER2_FETCHDECODE4 = 566, /* Address 0x40a94c00, size 0x00000400 */ 6152 PROT_VIDEOSS0_DSPLAYER2_FETCHECO4 = 567, /* Address 0x40a95000, size 0x00000400 */ 6153 PROT_VIDEOSS0_DSPLAYER3_FETCHWARP1 = 568, /* Address 0x40a95800, size 0x00000400 */ 6154 PROT_VIDEOSS0_DSPLAYER3_FETCHECO1 = 569, /* Address 0x40a95c00, size 0x00000400 */ 6155 PROT_VIDEOSS0_DSPLAYER4_FETCHLAYER1 = 570, /* Address 0x40a96000, size 0x00000400 */ 6156 PROT_VIDEOSS0_DSPLAYER5_FETCHDECODE0 = 571, /* Address 0x40a96400, size 0x00000400 */ 6157 PROT_VIDEOSS0_DSPVPB_GAMMACOR4 = 572, /* Address 0x40a96800, size 0x00000400 */ 6158 PROT_VIDEOSS0_DSPVPB_MATRIX4 = 573, /* Address 0x40a96c00, size 0x00000400 */ 6159 PROT_VIDEOSS0_DSPVPB_GPSCALER4 = 574, /* Address 0x40a97000, size 0x00000400 */ 6160 PROT_VIDEOSS0_DSPVPB_HISTOGRAM4 = 575, /* Address 0x40a97400, size 0x00000400 */ 6161 PROT_VIDEOSS0_DSPBLEND1_LAYERBLEND1 = 576, /* Address 0x40a97800, size 0x00000400 */ 6162 PROT_VIDEOSS0_DSPBLEND2_LAYERBLEND2 = 577, /* Address 0x40a97c00, size 0x00000400 */ 6163 PROT_VIDEOSS0_DSPBLEND3_LAYERBLEND3 = 578, /* Address 0x40a98000, size 0x00000400 */ 6164 PROT_VIDEOSS0_DSPBLEND4_LAYERBLEND4 = 579, /* Address 0x40a98400, size 0x00000400 */ 6165 PROT_VIDEOSS0_DSPBLEND5_LAYERBLEND5 = 580, /* Address 0x40a98800, size 0x00000400 */ 6166 PROT_VIDEOSS0_CAPIFC0_EXTSRC8 = 581, /* Address 0x40a98c00, size 0x00000400 */ 6167 PROT_VIDEOSS0_DSPCFG0_DISENGCFG0 = 582, /* Address 0x40aa0000, size 0x00000400 */ 6168 PROT_VIDEOSS0_DSPMON0_SIG0 = 583, /* Address 0x40aa1000, size 0x00000400 */ 6169 PROT_VIDEOSS0_DSPCFG0_FRAMEGEN0 = 584, /* Address 0x40aa2000, size 0x00000400 */ 6170 PROT_VIDEOSS0_DSPCOL0_GAMMACOR0 = 585, /* Address 0x40aa2400, size 0x00000400 */ 6171 PROT_VIDEOSS0_DSPCOL0_DITHER0 = 586, /* Address 0x40aa2800, size 0x00000400 */ 6172 PROT_VIDEOSS0_DSPIFC0_TCON0 = 587, /* Address 0x40aa3000, size 0x00000800 */ 6173 PROT_VIDEOSS0_DSPCFG1_DISENGCFG1 = 588, /* Address 0x40aa4000, size 0x00000400 */ 6174 PROT_VIDEOSS0_DSPMON1_SIG1 = 589, /* Address 0x40aa5000, size 0x00000400 */ 6175 PROT_VIDEOSS0_DSPCFG1_FRAMEGEN1 = 590, /* Address 0x40aa6000, size 0x00000400 */ 6176 PROT_VIDEOSS0_DSPCOL1_GAMMACOR1 = 591, /* Address 0x40aa6400, size 0x00000400 */ 6177 PROT_VIDEOSS0_DSPCOL1_DITHER1 = 592, /* Address 0x40aa6800, size 0x00000400 */ 6178 PROT_VIDEOSS0_DSPIFC1_TCON1 = 593, /* Address 0x40aa7000, size 0x00000800 */ 6179 PROT_VIDEOSS0_DSPIFC0_FPDLINK0 = 594, /* Address 0x40ac0000, size 0x00000400 */ 6180 PROT_VIDEOSS0_DSPIFC1_FPDLINK1 = 595, /* Address 0x40ac8000, size 0x00000400 */ 6181 PROT_VIDEOSS0_MIPICSI0_MIPICSI_STRUCT_MIPICSI_WRAP_MAIN = 596, /* Address 0x40ad0000, size 0x00000100 */ 6182 PROT_VIDEOSS0_MIPICSI0_MIPICSI_STRUCT_MIPICSI_CORE_3PIP = 597, /* Address 0x40ad0200, size 0x00000080 */ 6183 PROT_VIDEOSS0_VRPU_MAIN = 598, /* Address 0x40af0000, size 0x00000080 */ 6184 PROT_VIDEOSS0_GFX_MPU_RD0_MAIN = 599, /* Address 0x40af4000, size 0x00000004 */ 6185 PROT_VIDEOSS0_GFX_MPU_RD1_MAIN = 600, /* Address 0x40af4400, size 0x00000004 */ 6186 PROT_VIDEOSS0_GFX_MPU_RD2_MAIN = 601, /* Address 0x40af4800, size 0x00000004 */ 6187 PROT_VIDEOSS0_GFX_MPU_RD3_MAIN = 602, /* Address 0x40af4c00, size 0x00000004 */ 6188 PROT_VIDEOSS0_GFX_MPU_RD4_MAIN = 603, /* Address 0x40af5000, size 0x00000004 */ 6189 PROT_VIDEOSS0_GFX_MPU_RD5_MAIN = 604, /* Address 0x40af5400, size 0x00000004 */ 6190 PROT_VIDEOSS0_GFX_MPU_RD6_MAIN = 605, /* Address 0x40af5800, size 0x00000004 */ 6191 PROT_VIDEOSS0_GFX_MPU_RD7_MAIN = 606, /* Address 0x40af5c00, size 0x00000004 */ 6192 PROT_VIDEOSS0_GFX_MPU_RD8_MAIN = 607, /* Address 0x40af6000, size 0x00000004 */ 6193 PROT_VIDEOSS0_GFX_MPU_RD9_MAIN = 608, /* Address 0x40af6400, size 0x00000004 */ 6194 PROT_VIDEOSS0_GFX_MPU_RD10_MAIN = 609, /* Address 0x40af6800, size 0x00000004 */ 6195 PROT_VIDEOSS0_GFX_MPU_RD11_MAIN = 610, /* Address 0x40af6c00, size 0x00000004 */ 6196 PROT_VIDEOSS0_GFX_MPU_RD12_MAIN = 611, /* Address 0x40af7000, size 0x00000004 */ 6197 PROT_VIDEOSS0_GFX_MPU_RD13_MAIN = 612, /* Address 0x40af7400, size 0x00000004 */ 6198 PROT_VIDEOSS0_GFX_MPU_RD14_MAIN = 613, /* Address 0x40af7800, size 0x00000004 */ 6199 PROT_VIDEOSS0_GFX_MPU_RD15_MAIN = 614, /* Address 0x40af7c00, size 0x00000004 */ 6200 PROT_VIDEOSS0_GFX_MPU_WR0_MAIN = 615, /* Address 0x40af8000, size 0x00000004 */ 6201 PROT_VIDEOSS0_GFX_MPU_WR1_MAIN = 616, /* Address 0x40af8400, size 0x00000004 */ 6202 PROT_VIDEOSS0_GFX_MPU_WR2_MAIN = 617, /* Address 0x40af8800, size 0x00000004 */ 6203 PROT_VIDEOSS0_GFX_MPU_WR3_MAIN = 618, /* Address 0x40af8c00, size 0x00000004 */ 6204 PROT_VIDEOSS0_GFX_MPU_WR4_MAIN = 619, /* Address 0x40af9000, size 0x00000004 */ 6205 PROT_VIDEOSS0_GFX_MPU_WR5_MAIN = 620, /* Address 0x40af9400, size 0x00000004 */ 6206 PROT_VIDEOSS0_GFX_MPU_WR6_MAIN = 621, /* Address 0x40af9800, size 0x00000004 */ 6207 PROT_VIDEOSS0_GFX_MPU_WR7_MAIN = 622, /* Address 0x40af9c00, size 0x00000004 */ 6208 PROT_VIDEOSS0_GFX_MPU_WR8_MAIN = 623, /* Address 0x40afa000, size 0x00000004 */ 6209 PROT_VIDEOSS0_GFX_MPU_WR9_MAIN = 624, /* Address 0x40afa400, size 0x00000004 */ 6210 PROT_VIDEOSS0_GFX_MPU_WR10_MAIN = 625, /* Address 0x40afa800, size 0x00000004 */ 6211 PROT_VIDEOSS0_GFX_MPU_WR11_MAIN = 626, /* Address 0x40afac00, size 0x00000004 */ 6212 PROT_VIDEOSS0_GFX_MPU_WR12_MAIN = 627, /* Address 0x40afb000, size 0x00000004 */ 6213 PROT_VIDEOSS0_GFX_MPU_WR13_MAIN = 628, /* Address 0x40afb400, size 0x00000004 */ 6214 PROT_VIDEOSS0_GFX_MPU_WR14_MAIN = 629, /* Address 0x40afb800, size 0x00000004 */ 6215 PROT_VIDEOSS0_GFX_MPU_WR15_MAIN = 630, /* Address 0x40afbc00, size 0x00000004 */ 6216 PROT_PD_PD = 631, /* Address 0x40b00000, size 0x00000100 */ 6217 PROT_JPEGDEC_JPEGDEC = 632 /* Address 0x40b10000, size 0x00002000 */ 6218 } cy_en_prot_region_t; 6219 6220 #endif /* _TVIIC2D6M_CONFIG_H_ */ 6221 6222 6223 /* [] END OF FILE */ 6224
