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Searched refs:delay (Results 1 – 22 of 22) sorted by relevance

/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_lptimer.c340 uint32_t _cyhal_lptimer_get_toggle_bit(uint32_t c2_current, uint32_t delay) in _cyhal_lptimer_get_toggle_bit() argument
342 uint32_t val = c2_current ^ (c2_current + delay); in _cyhal_lptimer_get_toggle_bit()
351 static uint32_t _cyhal_lptimer_set_delay_common(cyhal_lptimer_t *obj, uint32_t delay) in _cyhal_lptimer_set_delay_common() argument
362 if (delay <= _CYHAL_LPTIMER_MIN_DELAY) in _cyhal_lptimer_set_delay_common()
364 delay = _CYHAL_LPTIMER_MIN_DELAY; in _cyhal_lptimer_set_delay_common()
368 if (delay > _CYHAL_LPTIMER_MAX_DELAY_TICKS) in _cyhal_lptimer_set_delay_common()
370 delay = _CYHAL_LPTIMER_MAX_DELAY_TICKS; in _cyhal_lptimer_set_delay_common()
375 obj->counter = (delay > ((1 << 16)-1)) ? CY_MCWDT_COUNTER2 : CY_MCWDT_COUNTER1; in _cyhal_lptimer_set_delay_common()
380 uint32_t match_value = counter_value + delay; in _cyhal_lptimer_set_delay_common()
389 match_value = delay - _CYHAL_LPTIMER_MIN_DELAY; in _cyhal_lptimer_set_delay_common()
[all …]
Dcyhal_sdhc.c1013 … cy_en_sd_host_status_t _cyhal_sdxx_polltransfercomplete(_cyhal_sdxx_t *sdxx, const uint16_t delay) in _cyhal_sdxx_polltransfercomplete() argument
1034 cyhal_system_delay_us(delay); in _cyhal_sdxx_polltransfercomplete()
/hal_infineon-latest/XMCLib/devices/XMC4700/Source/
Dsystem_XMC4700.c374 static void delay(uint32_t cycles) in delay() function
451 delay(DELAY_CNT_150US_50MHZ); in SystemCoreClockSetup()
481 delay(DELAY_CNT_50US_50MHZ); in SystemCoreClockSetup()
500 delay(DELAY_CNT_50US_50MHZ); in SystemCoreClockSetup()
583 delay(DELAY_CNT_50US_48MHZ); in SystemCoreClockSetup()
589 delay(DELAY_CNT_50US_72MHZ); in SystemCoreClockSetup()
595 delay(DELAY_CNT_50US_96MHZ); in SystemCoreClockSetup()
601 delay(DELAY_CNT_50US_120MHZ); in SystemCoreClockSetup()
607 delay(DELAY_CNT_50US_144MHZ); in SystemCoreClockSetup()
/hal_infineon-latest/XMCLib/devices/XMC4800/Source/
Dsystem_XMC4800.c427 static void delay(uint32_t cycles) in delay() function
504 delay(DELAY_CNT_150US_50MHZ); in SystemCoreClockSetup()
534 delay(DELAY_CNT_50US_50MHZ); in SystemCoreClockSetup()
553 delay(DELAY_CNT_50US_50MHZ); in SystemCoreClockSetup()
647 delay(DELAY_CNT_50US_48MHZ); in SystemCoreClockSetup()
658 delay(DELAY_CNT_50US_72MHZ); in SystemCoreClockSetup()
669 delay(DELAY_CNT_50US_96MHZ); in SystemCoreClockSetup()
680 delay(DELAY_CNT_50US_120MHZ); in SystemCoreClockSetup()
691 delay(DELAY_CNT_50US_144MHZ); in SystemCoreClockSetup()
/hal_infineon-latest/XMCLib/devices/XMC4500/Source/
Dsystem_XMC4500.c311 static void delay(uint32_t cycles) in delay() function
388 delay(DELAY_CNT_150US_50MHZ); in SystemCoreClockSetup()
418 delay(DELAY_CNT_50US_50MHZ); in SystemCoreClockSetup()
438 delay(DELAY_CNT_50US_50MHZ); in SystemCoreClockSetup()
528 delay(DELAY_CNT_50US_60MHZ); in SystemCoreClockSetup()
539 delay(DELAY_CNT_50US_90MHZ); in SystemCoreClockSetup()
550 delay(DELAY_CNT_50US_120MHZ); in SystemCoreClockSetup()
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_ephy.c128 uint32_t delay, max_delay=10; in Cy_EPHY_Reset() local
137 for( delay=0; delay < max_delay; delay++ ) in Cy_EPHY_Reset()
/hal_infineon-latest/btstack-integration/COMPONENT_BTSS-IPC/platform/ipc/
Dcybt_platform_hci.c261 volatile int delay = 1000; in cybt_platform_hci_get_buffer() local
262 while(delay--); in cybt_platform_hci_get_buffer()
489 volatile int delay = 1000; in cybt_platform_hci_write() local
490 while(delay--); in cybt_platform_hci_write()
/hal_infineon-latest/XMCLib/drivers/src/
Dxmc_dsd.c312 …XMC_ASSERT("XMC_DSD_RECTIFY_Init:NULL Pointer", (((uint16_t)config->delay + (uint16_t)config->half… in XMC_DSD_CH_Rectify_Init()
315 channel->CGSYNC = (((uint32_t) config->delay << (uint32_t)DSD_CH_CGSYNC_SDPOS_Pos) in XMC_DSD_CH_Rectify_Init()
316 …| (((uint32_t)config->delay + (uint32_t)config->half_cycle) << (uint32_t)DSD_CH_CGSYNC_SDNEG_Pos)); in XMC_DSD_CH_Rectify_Init()
Dxmc1_scu.c281 __STATIC_FORCEINLINE void delay(uint32_t cycles) in delay() function
567 delay(538); in XMC_SCU_CLOCK_Init()
577 delay(2685); in XMC_SCU_CLOCK_Init()
591 delay(6500000); in XMC_SCU_CLOCK_Init()
Dxmc_bccu.c111 …U_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mode, XMC_BCCU_TRIGDELAY_t delay) in XMC_BCCU_ConfigGlobalTrigger() argument
114 bccu->GLOBCON |= ((uint32_t)mode | ((uint32_t)delay << BCCU_GLOBCON_TRDEL_Pos)); in XMC_BCCU_ConfigGlobalTrigger()
248 bccu->GLOBCON |= ((uint32_t)trig->mode | ((uint32_t)trig->delay << BCCU_GLOBCON_TRDEL_Pos)); in XMC_BCCU_ConcurrentConfigTrigger()
Dxmc4_scu.c212 void XMC_SCU_lDelay(uint32_t delay) in XMC_SCU_lDelay() argument
217 delay = delay * (uint32_t)(SystemCoreClock / FREQ_1MHZ); in XMC_SCU_lDelay()
219 for (i = 0U; i < delay; ++i) in XMC_SCU_lDelay()
/hal_infineon-latest/XMCLib/drivers/inc/
Dxmc_dsd.h544 uint8_t delay; member
1082 __STATIC_INLINE void XMC_DSD_CH_GetRectifyDelay(XMC_DSD_CH_t *const channel, uint8_t* delay) in XMC_DSD_CH_GetRectifyDelay() argument
1085 *delay = (uint8_t)((channel->CGSYNC & DSD_CH_CGSYNC_SDCAP_Msk ) >> DSD_CH_CGSYNC_SDCAP_Pos); in XMC_DSD_CH_GetRectifyDelay()
Dxmc1_scu.h1246 …C_SCU_POWER_EnableMonitor(XMC_SCU_POWER_MONITOR_RANGE_t range, XMC_SCU_POWER_MONITOR_DELAY_t delay) in XMC_SCU_POWER_EnableMonitor() argument
1250 (uint32_t)delay; in XMC_SCU_POWER_EnableMonitor()
Dxmc_bccu.h401 …XMC_BCCU_TRIGDELAY_t delay; /**< Selects global trigger delay between channel trigger & BCCU trigg… member
551 …_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mode, XMC_BCCU_TRIGDELAY_t delay);
/hal_infineon-latest/mtb-hal-cat1/include/
Dcyhal_lptimer.h179 cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay);
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_crypto_core_trng.h203 #define CY_CRYPTO_IS_INIT_DELAY_VALID(delay) ((delay) <= 255U) argument
Dcy_canfd.h1069 __STATIC_INLINE void Cy_CANFD_EnableMRAM(CANFD_Type *base, uint32_t channelMask, uint16_t delay);
1264 __STATIC_INLINE void Cy_CANFD_EnableMRAM(CANFD_Type *base, uint32_t channelMask, uint16_t delay) in Cy_CANFD_EnableMRAM() argument
1274 Cy_SysLib_DelayUs(delay); in Cy_CANFD_EnableMRAM()
Dcy_cryptolite_trng.h229 #define CY_CRYPTOLITE_IS_INIT_DELAY_VALID(delay) ((delay) <= 255U) argument
Dcy_smif.h754 #define CY_SMIF_DESELECT_DELAY_VALID(delay) ((delay) <= CY_SMIF_MAX_DESELECT_DELAY) argument
/hal_infineon-latest/mtb-hal-cat1/
DRELEASE.md83 …1. Do not use RTOS delay even in RTOS-aware mode, to avoid ordering requirements between RTC and R…
148 * Added optional implementations for SDHC control pin APIs and RTOS aware delay API provided as wea…
185 * Extended System driver to provide delay functions
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/
Dcy_syslib_ext.s36 ; uint32_t cycles: The number of cycles to delay.
/hal_infineon-latest/wifi-host-driver/WiFi_Host_Driver/src/include/
Dwhd_wlioctl.h3285 uint32_t delay; member