1 /***************************************************************************//** 2 * \file cy_sysclk.h 3 * \version 3.110 4 * 5 * Provides an API declaration of the sysclk driver. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 *******************************************************************************/ 25 26 /** 27 * \addtogroup group_sysclk 28 * \{ 29 * The System Clock (SysClk) driver contains the API for configuring system and 30 * peripheral clocks. 31 * 32 * The functions and other declarations used in this driver are in cy_sysclk.h. 33 * You can include cy_pdl.h to get access to all functions 34 * and declarations in the PDL. 35 * 36 * Firmware uses the API to configure, enable, or disable a clock. 37 * 38 * The clock system includes a variety of resources that can vary per device, including: 39 * - Internal clock sources such as internal oscillators 40 * - External clock sources such as crystal oscillators or a signal on an I/O pin 41 * - Generated clocks such as an FLL, a PLL, and peripheral clocks 42 * 43 * Consult the Technical Reference Manual for your device for details of the 44 * clock system. 45 * 46 * The PDL defines clock system capabilities in:\n 47 * devices/COMPONENT_CAT1\<subcategory\>/include/\<series\>_config.h. (E.g. 48 * devices/COMPONENT_CAT1A/include/psoc6_01_config.h). 49 * 50 * As an illustration of the clocking system, the following diagram shows the 51 * PSoC 63 series clock tree. The actual tree may vary depending on the device series. 52 * Consult the Technical Reference Manual for your device for details. 53 *  54 * 55 * The sysclk driver supports multiple peripheral clocks, as well as the fast 56 * clock, slow clock, backup domain clock, timer clock, and pump clock. The API 57 * for any given clock contains the functions to manage that clock. Functions 58 * for clock measurement and trimming are also provided. 59 * 60 * \section group_sysclk_configuration Configuration Considerations 61 * The availability of clock functions depend on the availability of the chip 62 * resources that support those functions. Consult the device TRM before 63 * attempting to use these functions. 64 * For PSoC 64 devices the clocks configurations are restricted and limited. 65 * Refer to the PRA driver, and the TRM and datasheet for details. 66 * 67 * \warning 68 * On the diagram above, the yellow muxes are glitch-safe. All glitch-safe 69 * mux transitions take four cycles of the source clock. 70 * It is not allowed to turn off the source clock during that time. 71 * 72 * PSoC 6 power modes limit the maximum clock frequency. 73 * Refer to the SysPm driver and the TRM for details. 74 * 75 * \section group_sysclk_more_information More Information 76 * Refer to the technical reference manual (TRM) and the device datasheet. 77 * 78 * \section group_sysclk_changelog Changelog 79 * <table class="doxtable"> 80 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 81 * <tr> 82 * <td>3.110</td> 83 * <td> 84 * Added support for LPECO feature.<br>Newly added APIs: 85 * \n Cy_SysClk_LpEcoConfigure() 86 * \n Cy_SysClk_LpEcoEnable() 87 * \n Cy_SysClk_LpEcoDisable() 88 * \n Cy_SysClk_LpEcoSetFrequency() 89 * \n Cy_SysClk_LpEcoGetFrequency() 90 * \n Cy_SysClk_LpEcoPrescaleConfigure() 91 * \n Cy_SysClk_LpEcoPrescaleIsEnabled() 92 * \n Cy_SysClk_LpEcoAmplitudeOkay() 93 * \n Cy_SysClk_LpEcoIsReady() 94 * </td> 95 * </tr> 96 * <tr> 97 * <td>3.100</td> 98 * <td>Added support for CSV feature and fixed coverity bugs.</td> 99 * <td>Added CSV feature support for CAT1D and bug fixes.</td> 100 * </tr> 101 * <tr> 102 * <td>3.90</td> 103 * <td>Added support for TRAVEO™ II Body Entry devices.<br> 104 * Pre-processor check for MXS40SRSS version now groups ver. 2 with ver. 3. Previously ver. 2 was grouped with ver. 1.<br> 105 * In cy_sysclk_v2 source, added pre-processor logic to include/exclude certain SRSS versions.<br> 106 * Renamed PERI_DIV Defines to PERI_PCLK_GR_DIV for CAT1B and CAT1C. 107 * Changed pre-processor logic and set initial values to 0 for grpNum, instNum, locFrac, and locDiv variables to prevent uninitialized value access. 108 * Added pre-processor logic to prevent use of PLL400M API for non-compatible devices.</td> 109 * Added "Unsupported Core Type" warning messages. 110 * In cy_sysclk_v2 source, added API \ref Cy_SysClk_ClkFastGetDivider. 111 * <td>Code enhancement and support for new devices.</td> 112 * </tr> 113 * <tr> 114 * <td>3.80</td> 115 * <td>Added \ref Cy_SysClk_PiloOkay new API and few macros. Updated \ref Cy_SysClk_PiloEnable.</td> 116 * <td>Usability enhancement.</td> 117 * </tr> 118 * <tr> 119 * <td>3.70</td> 120 * <td>Added new APIs \ref Cy_SysClk_ClkPwrSetDivider, \ref Cy_SysClk_ClkPwrGetDivider, \ref Cy_SysClk_ClkPwrGetFrequency, \ref Cy_SysClk_ClkPwrSetSource, \ref Cy_SysClk_ClkPwrGetSource. \n and enum \ref cy_en_clkpwr_in_sources_t </td> 121 * <td>Support Added for future devices of the CAT1B.</td> 122 * </tr> 123 * <tr> 124 * <td rowspan="2">3.60</td> 125 * <td>Support for CAT1D devices is added</td> 126 * <td>New devices support added</td> 127 * </tr> 128 * <tr> 129 * <td>Remove local structure initialization to avoid optimization</td> 130 * <td>Code cleanup</td> 131 * </tr> 132 * <tr> 133 * <td>3.50</td> 134 * <td> 135 * Bug fixes and few new APIs addition.<br>Newly added APIs: 136 * \n Cy_SysClk_PllGetFrequency() for CAT1A,CAT1C and CAT1D devices, 137 * \n Cy_SysClk_Pll200MGetFrequency() for CAT1C devices, 138 * \n Cy_SysClk_Pll400MGetFrequency() for CAT1C devices, 139 * \n Cy_SysClk_ImoEnable() for CAT1D devices, 140 * \n Cy_SysClk_ImoDisable() for CAT1D devices, 141 * \n Cy_SysClk_ImoIsEnabled() for CAT1D devices, 142 * \n Cy_SysClk_ImoDeepsleepEnable() for CAT1D devices, 143 * \n Cy_SysClk_ImoIsDeepsleepEnabled() for CAT1D devices, 144 * \n Cy_SysClk_ImoDeepsleepDisable() for CAT1D devices, 145 * \n Cy_SysClk_ClkFastSrcGetDivider() for CAT1C devices, 146 * \n Cy_SysClk_ClkFastSrcSetDivider() for CAT1C devices, 147 * \n Cy_SysClk_ClkFastSrcGetFrequency() for CAT1C devices, 148 * </td> 149 * <td>Bug fixes and new devices support.</td> 150 * </tr> 151 * <tr> 152 * <td rowspan="3">3.40</td> 153 * <td> 154 * Added CAT1C and CAT1D devices support. 155 * </td> 156 * <td>Support for new devices.</td> 157 * </tr> 158 * <tr> 159 * <td>New API's for PLL400M and PLL200M.</td> 160 * <td>To handle the new PLL's for CAT1C devices.</td> 161 * </tr> 162 * <tr> 163 * <td>New API's Added 164 * * Cy_SysClk_Pll200MConfigure() 165 * * Cy_SysClk_Pll200MManualConfigure() 166 * * Cy_SysClk_Pll200MGetConfiguration() 167 * * Cy_SysClk_Pll200MEnable() 168 * * Cy_SysClk_Pll200MIsEnabled() 169 * * Cy_SysClk_Pll200MLocked() 170 * * Cy_SysClk_Pll200MLostLock() 171 * * Cy_SysClk_Pll200MDisable() 172 * * Cy_SysClk_Pll400MConfigure() 173 * * Cy_SysClk_Pll400MManualConfigure() 174 * * Cy_SysClk_Pll400MGetConfiguration() 175 * * Cy_SysClk_Pll400MEnable() 176 * * Cy_SysClk_Pll400MIsEnabled() 177 * * Cy_SysClk_Pll400MLocked() 178 * * Cy_SysClk_Pll400MLostLock() 179 * * Cy_SysClk_Pll200MDisable() 180 * * Cy_SysClk_IhoDeepsleepEnable() 181 * * Cy_SysClk_IhoIsDeepsleepEnabled() 182 * * Cy_SysClk_IhoDeepsleepDisable() 183 * * Cy_SysClk_IloSrcEnable() 184 * * Cy_SysClk_IloSrcIsEnabled() 185 * * Cy_SysClk_IloSrcDisable() 186 * * Cy_SysClk_IloSrcHibernateOn() 187 * * Cy_SysClk_PiloBackupEnable() 188 * * Cy_SysClk_PiloBackupDisable() 189 * * Cy_SysClk_PiloTcscEnable() 190 * * Cy_SysClk_PiloTcscDisable() 191 * * Cy_SysClk_AltHfEnable() 192 * * Cy_SysClk_IsAltHfEnabled() 193 * * Cy_SysClk_IloSetTrim() 194 * * Cy_SysClk_IloGetTrim() 195 * * Cy_SysClk_ClkMfSetSource() 196 * * Cy_SysClk_ClkMfGetSource() 197 * * Cy_SysClk_ClkHfDirectSel() 198 * * Cy_SysClk_IsClkHfDirectSelEnabled() 199 * * Cy_SysClk_PeriGroupGetSlaveCtl() 200 * * Cy_SysClk_IsPeriGroupSlaveCtlSet() 201 * * Cy_SysClk_PeriPclkGetFrequency() 202 * * Cy_SysClk_PeriPclkGetDividerEnabled() 203 * * Cy_Sysclk_PeriPclkGetClkHfNum() 204 * * Cy_SysClk_ClkMemSetDivider() 205 * * Cy_SysClk_ClkMemGetDivider() 206 * * Cy_SysClk_ClkMemGetFrequency() 207 * 208 * </td> 209 * <td>New API's to handle CAT1B, CAT1C and CAT1D devices.</td> 210 * </tr> 211 * <tr> 212 * <td rowspan="3">3.30</td> 213 * <td> 214 * For PSoC64 device, allow CM0+ to call CY_PRA_FUNCTION_CALL_X_X API in functions 215 * accessing FUNCTION_POLICY registers. So that System Configuration structure is 216 * updated with new parameters. 217 * </td> 218 * <td>For PSoC64 device, System configuration can be done from CM0+ application.</td> 219 * </tr> 220 * <tr> 221 * <td>Fixed MISRA 2012 violations.</td> 222 * <td>MISRA 2012 compliance.</td> 223 * </tr> 224 * <tr> 225 * <td>Return type doxygen updated for PSoC64 devices.</td> 226 * <td>Doxygen update for PSoC64 devices.</td> 227 * </tr> 228 * <tr> 229 * <td>3.20</td> 230 * <td>Added new API's \ref Cy_SysClk_FllGetFrequency and \ref Cy_SysClk_PllGetFrequency.</td> 231 * <td>Fetch the FLL and PLL frequency.</td> 232 * </tr> 233 * <tr> 234 * <td>3.10</td> 235 * <td>Support for CM33.</td> 236 * <td>New devices support.</td> 237 * </tr> 238 * <tr> 239 * <td rowspan="2">3.0</td> 240 * <td>The behavior of \ref Cy_SysClk_EcoEnable and \ref Cy_SysClk_PllEnable is changed - 241 * these functions disable the resource in case of enabling failure (timeout).</td> 242 * <td>Usability enhancement.</td> 243 * </tr> 244 * <tr> 245 * <td>The implementation of \ref Cy_SysClk_ClkPathGetSource, 246 * \ref Cy_SysClk_FllConfigure, 247 * \ref Cy_SysClk_FllGetConfiguration, 248 * \ref Cy_SysClk_PllConfigure 249 * and \ref Cy_SysClk_ClkMeasurementCountersGetFreq 250 * is updated in accordance to the MISRA 2012 requirements. No behavioral changes.</td> 251 * <td>MISRA 2012 compliance.</td> 252 * </tr> 253 * <tr> 254 * <td>2.20.1</td> 255 * <td>Updated source code comments.</td> 256 * <td>Documentation update.</td> 257 * </tr> 258 * <tr> 259 * <td rowspan="3">2.20</td> 260 * <td>Added the assertion mechanism to the following functions: 261 * * Cy_SysClk_EcoDisable() 262 * * Cy_SysClk_IloEnable() 263 * * Cy_SysClk_IloHibernateOn() 264 * * Cy_SysClk_PiloEnable() 265 * * Cy_SysClk_PiloDisable() 266 * * Cy_SysClk_WcoDisable() 267 * * Cy_SysClk_WcoBypass() 268 * * Cy_SysClk_ClkFastSetDivider() 269 * * Cy_SysClk_ClkPeriSetDivider() 270 * * Cy_SysClk_ClkLfSetSource() 271 * * Cy_SysClk_ClkTimerSetSource() 272 * * Cy_SysClk_ClkTimerSetDivider() 273 * * Cy_SysClk_ClkTimerEnable() 274 * * Cy_SysClk_ClkTimerDisable() 275 * * Cy_SysClk_ClkPumpSetSource() 276 * * Cy_SysClk_ClkPumpSetDivider() 277 * * Cy_SysClk_ClkPumpEnable() 278 * * Cy_SysClk_ClkPumpDisable() 279 * * Cy_SysClk_ClkBakSetSource() 280 * 281 * Now, the functions described above halt in assertion when a PRA 282 * request returns not successful operation. This change is 283 * applicable only for the PSoC 64 family devices. 284 * </td> 285 * <td>Enhancements for the debugging process.</td> 286 * </tr> 287 * <tr> 288 * <td>Added \ref Cy_SysClk_PiloInitialTrim and \ref Cy_SysClk_PiloUpdateTrimStep functions. 289 * Extended the \ref Cy_SysClk_PiloTrim function to use the step-size value calculated for PILO 290 * based on the \ref Cy_SysClk_PiloInitialTrim and \ref Cy_SysClk_PiloUpdateTrimStep 291 * functions call. </td> 292 * </td> 293 * <td>User experience enhancement.</td> 294 * </tr> 295 * <tr> 296 * <td> 297 * * Added the warning that during a glitch-safe mux, the transition is not allowed 298 * to disable the previous clock source. See more info 299 * in the \ref group_sysclk_configuration. 300 * * Removed Known Issues table. 301 * </td> 302 * <td>Documentation updates.</td> 303 * </tr> 304 * <tr> 305 * <td rowspan="3">2.10</td> 306 * <td>Updated SysClk functions for PSoC 64 devices. Now the SysClk functions can return 307 * PRA driver status value.</td> 308 * <td>The SysClk driver uses the PRA driver to change the protected registers. 309 * A SysClk driver function that calls a PRA driver function will return the PRA 310 * error status code if the called PRA function returns an error. In these cases, 311 * refer to PRA return statuses. Refer to functions description for details.</td> 312 * </tr> 313 * <tr> 314 * <td>Updated the code of \ref Cy_SysClk_ClkPathGetFrequency function.</td> 315 * <td>Make the code more error-resistant to user errors for some corner cases.</td> 316 * </tr> 317 * <tr> 318 * <td>Minor documentation updates.</td> 319 * <td>Documentation enhancement.</td> 320 * </tr> 321 * <tr> 322 * <td>2.0</td> 323 * <td>Updated the ECO trimming values calculation algorithm in the \ref Cy_SysClk_EcoConfigure implementation. \n 324 * This change may invalidate the already used crystals, in cases: \n 325 * * The crystal frequency is less than 16 MHz. \n 326 * * The maximum amplitude (internal calculation value) is less than 0.65 V. \n 327 * 328 * For detail, refer the \ref Cy_SysClk_EcoConfigure documentation and the ECO Trimming section of the device TRM.</td> 329 * <td>Enhanced the ECO performance for high-noise conditions that result from simultaneous switching of GPIOs and/or high switching activity on the chip.</td> 330 * </tr> 331 * <tr> 332 * <td>1.60</td> 333 * <td>Added the following functions: \ref Cy_SysClk_ExtClkGetFrequency, \ref Cy_SysClk_EcoGetFrequency,\n 334 * \ref Cy_SysClk_ClkPathMuxGetFrequency, \ref Cy_SysClk_ClkPathGetFrequency, \ref Cy_SysClk_IloIsEnabled.\n 335 * \ref Cy_SysClk_PiloIsEnabled, \ref Cy_SysClk_AltHfGetFrequency, \ref Cy_SysClk_ClkHfIsEnabled,\n 336 * \ref Cy_SysClk_ClkTimerIsEnabled, \ref Cy_SysClk_ClkTimerGetFrequency, \ref Cy_SysClk_ClkPumpIsEnabled and\n 337 * \ref Cy_SysClk_ClkPumpGetFrequency.</td> 338 * <td>API enhancement.</td> 339 * </tr> 340 * <tr> 341 * <td>1.50</td> 342 * <td>\ref Cy_SysClk_ClkHfGetFrequency is updated to reuse the \ref cy_BleEcoClockFreqHz global system variable.</td> 343 * <td>API enhancement.</td> 344 * </tr> 345 * <tr> 346 * <td>1.40.2</td> 347 * <td>Update documentation based on collateral review feedback.</td> 348 * <td>User experience enhancement.</td> 349 * </tr> 350 * <tr> 351 * <td>1.40.1</td> 352 * <td>Fix compiler warning.</td> 353 * <td></td> 354 * </tr> 355 * <tr> 356 * <td rowspan="4">1.40</td> 357 * <td>Updated the following functions implementation: \ref Cy_SysClk_PllConfigure and \ref Cy_SysClk_PllEnable.</td> 358 * <td> 359 * Fixed the \ref Cy_SysClk_PllConfigure API function behaviour when it is called with a bypass mode, \n 360 * Fixed the \ref Cy_SysClk_PllEnable API function behaviour when it is called with a zero timeout. 361 * </td> 362 * </tr> 363 * <tr> 364 * <td>Added the following functions: \ref Cy_SysClk_MfoEnable, \ref Cy_SysClk_MfoIsEnabled,\n 365 * \ref Cy_SysClk_MfoDisable, \ref Cy_SysClk_ClkMfEnable, \ref Cy_SysClk_ClkMfIsEnabled,\n 366 * \ref Cy_SysClk_ClkMfDisable, \ref Cy_SysClk_ClkMfGetDivider, \ref Cy_SysClk_ClkMfSetDivider,\n. 367 * \ref Cy_SysClk_ClkMfGetFrequency</td> 368 * <td>New device support.</td> 369 * </tr> 370 * <tr> 371 * <td>Added the following new API functions \ref Cy_SysClk_FllIsEnabled, \ref Cy_SysClk_PllIsEnabled,\n 372 * \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_ClkHfGetFrequency, \ref Cy_SysClk_ClkFastGetFrequency,\n 373 * \ref Cy_SysClk_ClkPeriGetFrequency and \ref Cy_SysClk_ClkSlowGetFrequency</td> 374 * <td>Enhancement based on usability feedback</td> 375 * </tr> 376 * <tr> 377 * <td>Deprecated the following macros: CY_SYSCLK_DIV_ROUND and CY_SYSCLK_DIV_ROUNDUP</td> 378 * <td>Macros were moved into \ref group_syslib</td> 379 * </tr> 380 * <tr> 381 * <td rowspan="2">1.30</td> 382 * <td>Updated the following functions implementation: \ref Cy_SysClk_EcoConfigure and \ref Cy_SysClk_FllConfigure.</td> 383 * <td>Math library dependency is removed, the floating-point math is replaced with integer math.</td> 384 * </tr> 385 * <tr> 386 * <td>Updated the following functions implementation: \ref Cy_SysClk_EcoEnable, \ref Cy_SysClk_EcoGetStatus, \ref Cy_SysClk_FllGetConfiguration \n 387 * and \ref Cy_SysClk_DeepSleepCallback. \n 388 * The \ref Cy_SysClk_DeepSleepCallback now implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t. \n 389 * The actions that were done in \ref CY_SYSPM_CHECK_READY case are moved to \ref CY_SYSPM_BEFORE_TRANSITION. \n 390 * So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL.</td> 391 * <td>Defect fixing.</td> 392 * </tr> 393 * <tr> 394 * <td rowspan="4">1.20</td> 395 * <td>Flattened the organization of the driver source code into the single 396 * source directory and the single include directory. 397 * </td> 398 * <td>Driver library directory-structure simplification.</td> 399 * </tr> 400 * <tr> 401 * <td>Updated \ref Cy_SysClk_FllLocked function description</td> 402 * <td>The SRSS_ver1 HW details clarification</td> 403 * </tr> 404 * <tr> 405 * <td>Removed the following functions: 406 * - Cy_SysClk_FllLostLock 407 * - Cy_SysClk_WcoConfigureCsv 408 * - Cy_SysClk_ClkHfConfigureCsv 409 * </td> 410 * <td>No hardware support for the removed functions.</td> 411 * </tr> 412 * <tr> 413 * <td>Added register access layer. Use register access macros instead 414 * of direct register access using dereferenced pointers.</td> 415 * <td>Makes register access device-independent, so that the PDL does 416 * not need to be recompiled for each supported part number.</td> 417 * </tr> 418 * <tr> 419 * <td>1.11</td> 420 * <td>Updated the following functions. Now they use a semaphore when 421 * try to read the status or configure the SysClk measurement counters: 422 * * Cy_SysClk_StartClkMeasurementCounters() 423 * * Cy_SysClk_ClkMeasurementCountersGetFreq() 424 * 425 * Now Cy_SysClk_ClkMeasurementCountersGetFreq() returns zero value, 426 * if during measurement device was in the Deep Sleep or partially 427 * blocking flash operation occurred </td> 428 * <td>Added arbiter mechanism for correct usage of the SysClk measurement 429 * counters</td> 430 * </tr> 431 * <tr> 432 * <td>1.10.1</td> 433 * <td>Renamed Power Management section to Low Power Callback section</td> 434 * <td>Documentation update and clarification</td> 435 * </tr> 436 * <tr> 437 * <td rowspan="5">1.10</td> 438 * <td>Updated FLL parameter calculation</td> 439 * <td>Support low frequency sources</td> 440 * </tr> 441 * <tr> 442 * <td>Added Cy_SysClk_PiloSetTrim() and Cy_SysclkPiloGetTrim() functions</td> 443 * <td>Support PILO manual trims</td> 444 * </tr> 445 * <tr> 446 * <td>Made Cy_SysClk_FllLostLock() function dependent on SRSS v1</td> 447 * <td>Feature is not supported in SRSS v1</td> 448 * </tr> 449 * <tr> 450 * <td>Updated Cy_SysClk_DeepSleepCallback() to save/restore both FLL and PLL settings</td> 451 * <td>The function should return when the lock is established or a timeout has occurred</td> 452 * </tr> 453 * <tr> 454 * <td>General documentation updates</td> 455 * <td></td> 456 * </tr> 457 * <tr> 458 * <td>1.0</td> 459 * <td>Initial version</td> 460 * <td></td> 461 * </tr> 462 * </table> 463 * 464 * \defgroup group_sysclk_macros Macros 465 * \{ 466 * \} 467 * \defgroup group_sysclk_enums General Enumerated Types 468 * \{ 469 * \defgroup group_sysclk_returns Function return values 470 * \} 471 * \defgroup group_sysclk_ext External Clock Source (EXTCLK) 472 * \{ 473 * The External Clock Source (EXTCLK) is a clock source routed into SOC 474 * through a GPIO pin. The EXTCLK is a source clock that can be used to 475 * source one or more clock paths (Refer to \ref group_sysclk_path_src). 476 * These clock paths can then source the processors and peripherals in 477 * the device. 478 * 479 * The EXTCLK relies on the presence of an external clock signal applied 480 * to the GPIO pin. The pin must be configured to operate in Digital 481 * High-Z drive mode with input buffer on and HSIOM connection 482 * set to HSIOM_SEL_ACT_4. 483 * 484 * \defgroup group_sysclk_ext_funcs Functions 485 * \} 486 * \defgroup group_sysclk_eco External Crystal Oscillator (ECO) 487 * \{ 488 * The External Crystal Oscillator (ECO) is a clock source that consists 489 * of an oscillator circuit that drives an external crystal through its 490 * dedicated ECO pins. The ECO is a source clock that can be used to 491 * source one or more clock paths (Refer to \ref group_sysclk_path_src). 492 * These clock paths can then source the processors and peripherals in 493 * the device. 494 * 495 * The ECO relies on the presence of an external crystal. The pins 496 * connected to this crystal must be configured to operate in analog 497 * drive mode with HSIOM connection set to GPIO control (HSIOM_SEL_GPIO). 498 * 499 * \note 500 * For CAT1D devices, two models are possible for ECO as shown in the diagram below 501 *  502 * 503 * \defgroup group_sysclk_eco_funcs Functions 504 * \defgroup group_sysclk_eco_enums Enumerated Types 505 * \} 506 * \defgroup group_sysclk_path_src Clock Path Source 507 * \{ 508 * Clock paths are a series of multiplexers that allow a source clock 509 * to drive multiple clocking resources down the chain. These paths are 510 * used for active domain clocks that are not operational during chip 511 * Deep Sleep, hibernate and off modes. Illustrated below is a diagram 512 * of the clock paths for the PSoC 63 series, showing the first three 513 * clock paths. The source clocks for these paths are highlighted in 514 * the red box. 515 * 516 * - IMO: 8 MHz Internal Main Oscillator (Default) 517 * - EXTCLK: External clock (signal brought in through dedicated pins) 518 * - ECO: External Crystal Oscillator (requires external crystal on dedicated pins) 519 * - ALTHF: Select on-chip signals (e.g. \ref group_ble_clk) 520 * - Digital Signal (DSI): Digital signal from a UDB source 521 * 522 * Some clock paths such as path 0 and path 1 have additional resources 523 * that can be utilized to provide a higher frequency clock. For example, 524 * path 0 source clock can be used as the reference clock for the FLL and 525 * path 1 source clock can be used as the reference clock for the PLL. 526 * 527 *  528 * 529 * \note The PDL driver cannot configure a clock path to use Digital Signal 530 * Interconnect (DSI) outputs as sources. This must be done through DSI 531 * configuration tool such as PSoC Creator. 532 * 533 * \defgroup group_sysclk_path_src_funcs Functions 534 * \defgroup group_sysclk_path_src_enums Enumerated Types 535 * \} 536 * \defgroup group_sysclk_fll Frequency Locked Loop (FLL) 537 * \{ 538 * The FLL is a clock generation circuit that can be used to produce a 539 * higher frequency clock from a reference clock. The output clock exhibits 540 * some characteristics of the reference clock such as the accuracy of the 541 * source. However other attributes such as the clock phase are not preserved. 542 * The FLL is similar in purpose to a (Phase locked loop) PLL but they are 543 * not equivalent. 544 * 545 * - They may have different frequency ranges. 546 * - The FLL starts up (locks) faster and consumes less current than the PLL. 547 * - The FLL accepts a source clock with lower frequency than PLL, such as the WCO (32 KHz). 548 * - The FLL does not lock phase. The hardware consist of a counter with a 549 * current-controlled oscillator (CCO). The counter counts the number of output 550 * clock edges in a reference clock period and adjusts the CCO until the 551 * expected ratio is achieved (locked). After initial lock, the CCO is 552 * adjusted dynamically to keep the ratio within tolerance. The lock tolerance 553 * is user-adjustable. 554 *  555 * 556 * The SysClk driver supports two models for configuring the FLL. The first 557 * model is to call the Cy_SysClk_FllConfigure() function, which calculates the 558 * necessary parameters for the FLL at run-time. This may be necessary for dynamic 559 * run-time changes to the FLL. However this method is slow as it needs to perform 560 * the calculation before configuring the FLL. The other model is to call 561 * Cy_SysClk_FllManualConfigure() function with pre-calculated parameter values. 562 * This method is faster but requires prior knowledge of the necessary parameters. 563 * Consult the device TRM for the FLL calculation equations. 564 * 565 * \defgroup group_sysclk_fll_funcs Functions 566 * \defgroup group_sysclk_fll_structs Data Structures 567 * \defgroup group_sysclk_fll_enums Enumerated Types 568 * \} 569 * \defgroup group_sysclk_pll Phase Locked Loop (PLL) 570 * \{ 571 * The PLL is a clock generation circuit that can be used to produce a 572 * higher frequency clock from a reference clock. The output clock exhibits 573 * characteristics of the reference clock such as the accuracy of the source 574 * and its phase. The PLL is similar in purpose to a (Frequency locked loop) FLL 575 * but they are not equivalent. 576 * 577 * - They may have different frequency ranges. 578 * - The PLL starts up more slowly and consumes more current than the FLL. 579 * - The PLL requires a higher frequency source clock than FLL. 580 *  581 * 582 * The SysClk driver supports two models for configuring the PLL. The first 583 * model is to call the Cy_SysClk_PllConfigure() function, which calculates the 584 * necessary parameters for the PLL at run-time. This may be necessary for dynamic 585 * run-time changes to the PLL. However this method is slow as it needs to perform 586 * the calculation before configuring the PLL. The other model is to call 587 * Cy_SysClk_PllManualConfigure() function with pre-calculated parameter values. 588 * This method is faster but requires prior knowledge of the necessary parameters. 589 * Consult the device TRM for the PLL calculation equations. 590 * 591 * \defgroup group_sysclk_pll_funcs Functions 592 * \defgroup group_sysclk_pll_structs Data Structures 593 * \} 594 * \defgroup group_sysclk_ilo Internal Low-Speed Oscillator (ILO) 595 * \{ 596 * The ILO operates with no external components and outputs a stable clock at 597 * 32.768 kHz nominal. The ILO is relatively low power and low accuracy. It is 598 * available in all power modes and can be used as a source for the Backup domain clock. 599 *  600 * 601 * To ensure the ILO remains active in Hibernate mode, and across power-on-reset 602 * (POR) or brown out detect (BOD), firmware must call Cy_SysClk_IloHibernateOn(). 603 * 604 * Additionally, the ILO clock can be trimmed to +/- 1.5% of nominal frequency using 605 * a higher precision clock source. Use the \ref group_sysclk_calclk API to measure 606 * the current ILO frequency before trimming. 607 * 608 * \note The ILO is always the source clock for the \ref group_wdt. Therefore: 609 * - The WDT must be unlocked when making an ILO function call in the PDL 610 * - It is recommended to always have the ILO enabled 611 * 612 * \defgroup group_sysclk_ilo_funcs Functions 613 * \} 614 * \defgroup group_sysclk_pilo Precision Internal Low-Speed Oscillator (PILO) 615 * \{ 616 * PILO provides a higher accuracy 32.768 kHz clock than the \ref group_sysclk_ilo "ILO". 617 * When periodically calibrated using a high-accuracy clock such as the 618 * \ref group_sysclk_eco "ECO", the PILO can achieve 250 ppm accuracy of nominal frequency. 619 * The PILO is capable of operating in device Active, Sleep and Deep-Sleep power modes. 620 * It is not available in Hibernate mode. 621 * 622 * The PILO can be used as a source for the \ref group_sysclk_clk_lf. However, 623 * because PILO is disabled in Hibernate mode, RTC timers cannot operate in this mode 624 * when clocked using the PILO. Instead, either the \ref group_sysclk_ilo "ILO" or 625 * \ref group_sysclk_wco "WCO" should be used when hibernate operation is required. 626 * 627 *  628 * 629 * Periodic calibration to a high-accuracy clock (such as ECO) is required to 630 * maintain accuracy. The application should use the functions described in the 631 * \ref group_sysclk_calclk API to measure the current PILO frequency before trimming. 632 * 633 * \defgroup group_sysclk_pilo_funcs Functions 634 * \} 635 * \defgroup group_sysclk_calclk Clock Measurement 636 * \{ 637 * These functions measure the frequency of a specified clock relative to a 638 * reference clock. They are typically called in the following order: 639 * 640 * 1. Specify the measured clock, the count, and the reference clock 641 * 2. Start the counters 642 * 3. Wait for the measurement counter to finish counting 643 * 4. Retrieve the measured frequency 644 * 645 * \note These functions may also be used as part of a clock trimming 646 * process. Refer to the \ref group_sysclk_trim "Clock Trim" API. 647 * 648 * \defgroup group_sysclk_calclk_funcs Functions 649 * \defgroup group_sysclk_calclk_enums Enumerated Types 650 * \defgroup group_sysclk_calclk_structs Data Structures 651 * \} 652 * \defgroup group_sysclk_trim Clock Trim (ILO, PILO) 653 * \{ 654 * These functions perform a single trim operation on the ILO or PILO. Each 655 * function's parameter is the actual frequency of the clock. To measure the 656 * frequency, use the functions described in the \ref group_sysclk_calclk API. 657 * 658 * To trim the clock as close as possible to the target frequency, multiple 659 * calls to the trim function may be needed. A typical usage example is to: 660 * 1. Call the clock measurement functions to get the actual frequency of the clock 661 * 2. Call the trim function, passing in the measured frequency 662 * 3. Repeat the above until the trim function reports that the clock is trimmed to within limits. 663 * 664 * \defgroup group_sysclk_trim_funcs Functions 665 * \} 666 * \defgroup group_sysclk_pm Low Power Callback 667 * \{ 668 * Entering and exiting low power modes require compatible clock configurations 669 * to be set before entering low power and restored upon wake-up and exit. The 670 * SysClk driver provides a Cy_SysClk_DeepSleepCallback() function to support 671 * Deep Sleep mode entry. 672 * 673 * This function can be called either by itself before initiating low-power mode 674 * entry or it can be used in conjunction with the SysPm driver as a registered 675 * callback. To do so, register this function as a callback before calling 676 * Cy_SysPm_DeepSleep(). Specify \ref CY_SYSPM_DEEPSLEEP as the callback type, 677 * and call Cy_SysPm_RegisterCallback(). 678 * 679 * \note If the FLL or PLL source is the ECO, this function must be called. 680 * 681 * \defgroup group_sysclk_pm_funcs Functions 682 * \} 683 * \defgroup group_sysclk_wco Watch Crystal Oscillator (WCO) 684 * \{ 685 * The WCO is a highly accurate 32.768 kHz clock source capable of operating 686 * in all power modes (excluding the Off mode). It is the primary clock source for 687 * the backup domain clock, which is used by the real-time clock (RTC). The 688 * WCO can also be used as a source for the low-frequency clock to support other 689 * low power mode peripherals. 690 * 691 *  692 * 693 * The WCO requires the configuration of the dedicated WCO pins (SRSS_WCO_IN_PIN, 694 * SRSS_WCO_OUT_PIN). These must be configured as Analog Hi-Z drive modes and the 695 * HSIOM selection set to GPIO. The WCO can also be used in bypass mode, where 696 * an external 32.768 kHz square wave is brought in directly through the 697 * SRSS_WCO_OUT_PIN pin. 698 * 699 * \defgroup group_sysclk_wco_funcs Functions 700 * \defgroup group_sysclk_wco_enums Enumerated Types 701 * \} 702 * \defgroup group_sysclk_lpeco Low-Power External Crystal Oscillator (LPECO) 703 * \{ 704 * The LPECO provides high-frequency clocking using an external crystal connected to 705 * the LPECO_IN and LPECO_OUT pins. It can be thought of as an ECO that operates 706 * during low power modes and, when used in conjunction with the PLL, it generates 707 * CPU and peripheral clocks up to the device's maximum frequency. A fractional 708 * divider allows the real-time clock (RTC) to use the LPECO during low power modes, 709 * however, the LPECO has significantly higher current consumption than the WCO. 710 * 711 * The pins connected to the external crystal must be configured to operate in analog 712 * drive mode with HSIOM connection set to GPIO control (HSIOM_SEL_GPIO). 713 * 714 * \defgroup group_sysclk_lpeco_funcs Functions 715 * \defgroup group_sysclk_lpeco_enums Enumerated Types 716 * \} 717 * \defgroup group_sysclk_clk_hf High-Frequency Clocks 718 * \{ 719 * Multiple high frequency clocks (CLK_HF) are available in the device. For example, 720 * PSoC 63 series has five high-frequency root clocks. Each CLK_HF has a particular 721 * connection and chip-specific destination on the device. 722 * 723 * |Name |Description | 724 * |:--------|:-------------------------------------------------------| 725 * |CLK_HF[0]| Root clock for CPUs, PERI, and AHB infrastructure | 726 * |CLK_HF[1]| Root clock for the PDM/PCM and I2S audio subsystem | 727 * |CLK_HF[2]| Root clock for the Serial Memory Interface subsystem | 728 * |CLK_HF[3]| Root clock for USB communications | 729 * |CLK_HF[4]| Clock output on clk_ext pin (when used as an output) | 730 * 731 *  732 * 733 * Note this is a particular example. The actual tree may vary depending on the device series. 734 * Consult the Technical Reference Manual for your device for details. 735 * 736 * High frequency clocks are sourced by path clocks, which should be configured 737 * first. An exception to this rule is CLK_HF[0], which cannot be disabled. 738 * This divided clock drives the core processors and the peripherals in the system. 739 * In order to update its clock source, CLK_HF[0] source must be selected without 740 * disabling the clock. 741 * 742 *  743 * 744 * \defgroup group_sysclk_clk_hf_funcs Functions 745 * \defgroup group_sysclk_clk_hf_enums Enumerated Types 746 * \} 747 * \defgroup group_sysclk_clk_fast Fast Clock 748 * \{ 749 * The fast clock drives the "fast" processor (e.g. Cortex-M4 processor in PSoC 6). 750 * This clock is sourced by CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). 751 * A divider value of 1~256 can be used to further divide the CLK_HF[0] to a 752 * desired clock speed for the processor. 753 * 754 *  755 * 756 * \defgroup group_sysclk_clk_fast_funcs Functions 757 * \} 758 * \defgroup group_sysclk_clk_peri Peripheral Clock 759 * \{ 760 * The peripheral clock is a divided clock of CLK_HF0 (\ref group_sysclk_clk_hf "HF Clocks"). 761 * It is the source clock for the \ref group_sysclk_clk_slow, and most active domain 762 * peripheral clocks (\ref group_sysclk_clk_peripheral). A divider value of 1~256 763 * can be used to further divide the CLK_HF[0] to a desired clock speed for the peripherals. 764 * 765 *  766 * 767 * \defgroup group_sysclk_clk_peri_funcs Functions 768 * \} 769 * \defgroup group_sysclk_clk_peripheral Peripherals Clock Dividers 770 * \{ 771 * There are multiple peripheral clock dividers that, in effect, create 772 * multiple separate peripheral clocks. The available dividers vary per device 773 * series. As an example, for the PSoC 63 series there are 29 dividers: 774 * 775 * - eight 8-bit dividers 776 * - sixteen 16-bit dividers 777 * - four fractional 16.5-bit dividers (16 integer bits, 5 fractional bits) 778 * - one fractional 24.5-bit divider (24 integer bits, 5 fractional bits) 779 * 780 * 781 * The 8-bit and 16-bit dividers are integer dividers. A divider value of 1 782 * means the output frequency matches the input frequency (that is, there is 783 * no change). Otherwise the frequency is divided by the value of the divider. 784 * For example, if the input frequency is 50 MHz, and the divider is value 10, 785 * the output frequency is 5 MHz. 786 * 787 * The five fractional bits supports further precision in 1/32nd increments. For 788 * example, a divider with an integer value of 3 and a fractional value of 789 * 4 (4/32) results in a divider of 3.125. Fractional dividers are useful when 790 * a high-precision clock is required, for example, for a UART/SPI serial 791 * interface. 792 * 793 *  794 * 795 * Each peripheral can connect to any one of the programmable dividers. A 796 * particular peripheral clock divider can drive multiple peripherals. 797 * 798 * The SysClk driver also supports phase aligning two peripheral clock dividers using 799 * Cy_SysClk_PeriphEnablePhaseAlignDivider(). Alignment works for both integer 800 * and fractional dividers. The divider to which a second divider is aligned 801 * must already be enabled. 802 * 803 * \defgroup group_sysclk_clk_peripheral_funcs Functions 804 * \defgroup group_sysclk_clk_peripheral_enums Enumerated Types 805 * \} 806 * \defgroup group_sysclk_clk_peripheral_group Peripheral Group(MMIO Group) Controls 807 * \{ 808 * All the peripherals in the SOC belongs to certain MMIO groups. 809 * Below control operations can be done on each MMIO group 810 * - MMIO Group level clock division, 8-bit Integer divider 811 * - Peripheral Slave Enabling/Disabling 812 * - Peripheral Slave Reset Enabling/Disabling 813 * 814 * The 8-bit divider is an integer divider. Actual divider will be (divider + 1). 815 * For example with a divider of 0, actual divider = 0 + 1 = 1,means the output 816 * frequency matches the input frequency (that is, there is 817 * no change). Otherwise the frequency is divided by the value of the (divider + 1). 818 * For example, if the input frequency is 50 MHz, and the divider is value 9, 819 * the output frequency is 5 MHz i.e. 50/(9+1). 820 * 821 * 822 *  823 * 824 * \defgroup group_sysclk_clk_peripheral_group_funcs Functions 825 * \defgroup group_sysclk_clk_peripheral_group_enums Enumerated Types 826 * \} 827 * \defgroup group_sysclk_clk_slow Slow Clock 828 * \{ 829 * The slow clock is the source clock for the "slow" processor (e.g. Cortex-M0+ in PSoC 6). 830 * This clock is a divided version of the \ref group_sysclk_clk_peri, which in turn is 831 * a divided version of CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). A divider 832 * value of 1~256 can be used to further divide the Peri clock to a desired clock speed 833 * for the processor. 834 * 835 *  836 * 837 * \defgroup group_sysclk_clk_slow_funcs Functions 838 * \} 839 * \defgroup group_sysclk_alt_hf Alternative High-Frequency Clock 840 * \{ 841 * In the BLE-enabled PSoC6 devices, the \ref group_ble_clk clock is 842 * connected to the system Alternative High-Frequency Clock input. In CAT1B devices, 843 * the BTSS IP will provide clock input to ALTHF. 844 * 845 * \defgroup group_sysclk_alt_hf_funcs Functions 846 * \} 847 * \defgroup group_sysclk_clk_lf Low-Frequency Clock 848 * \{ 849 * The low-frequency clock is the source clock for the \ref group_mcwdt 850 * and can be the source clock for \ref group_sysclk_clk_bak, which drives the 851 * \ref group_rtc. 852 * 853 * The low-frequency clock has three possible source clocks: 854 * \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", and 855 * \ref group_sysclk_wco "WCO". 856 * 857 *  858 * 859 * \defgroup group_sysclk_clk_lf_funcs Functions 860 * \defgroup group_sysclk_clk_lf_enums Enumerated Types 861 * \} 862 * \defgroup group_sysclk_clk_timer Timer Clock 863 * \{ 864 * The timer clock can be a source for the alternative clock driving 865 * the \ref group_arm_system_timer. It can also be used as a reference clock 866 * for a counter in the \ref group_energy_profiler "Energy Profiler". 867 * 868 * The timer clock is a divided clock of either the IMO or CLK_HF[0] 869 * (\ref group_sysclk_clk_hf "HF Clocks"). 870 * 871 * \defgroup group_sysclk_clk_timer_funcs Functions 872 * \defgroup group_sysclk_clk_timer_enums Enumerated Types 873 * \} 874 * \defgroup group_sysclk_clk_pump Pump Clock 875 * \{ 876 * The pump clock is a clock source used to provide analog precision in low voltage 877 * applications. Depending on the usage scenario, it may be required to drive the 878 * internal voltage pump for the Continuous Time Block mini (CTBm) in the analog 879 * subsystem. The pump clock is a divided clock of one of the clock paths 880 * (\ref group_sysclk_path_src). 881 * 882 * \defgroup group_sysclk_clk_pump_funcs Functions 883 * \defgroup group_sysclk_clk_pump_enums Enumerated Types 884 * \} 885 * \defgroup group_sysclk_clk_bak Backup Domain Clock 886 * \{ 887 * The backup domain clock drives the \ref group_rtc. 888 * This clock has two possible source clocks: \ref group_sysclk_wco "WCO" 889 * or the \ref group_sysclk_clk_lf. In turn the low frequency clock is sourced by 890 * \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", or 891 * \ref group_sysclk_wco "WCO". Typically the ILO is not suitable as an RTC source, 892 * because of its low accuracy. However the ILO does operate in hibernate mode and 893 * may be used as an alternative to the WCO with a tradeoff in precision. 894 * 895 * \defgroup group_sysclk_clk_bak_funcs Functions 896 * \defgroup group_sysclk_clk_bak_enums Enumerated Types 897 * \} 898 * \defgroup group_sysclk_mf Medium Frequency Domain Clock 899 * \{ 900 * The Medium Frequency Domain Clock is present only in SRSS_ver1_3. 901 * Consists of MFO - the Medium Frequency Oscillator, 902 * and CLK_MF - the Medium Frequency Clock divider. 903 * This clock chain is designed to source the LCD block 904 * in Deep Sleep mode, see \ref cy_en_seglcd_lsclk_t. 905 * 906 * \defgroup group_sysclk_mf_funcs Functions 907 * \defgroup group_sysclk_clk_mf_enums Enumerated Types 908 * \} 909 * \defgroup group_sysclk_iho Internal High Frequency(IHO) Clock 910 * \{ 911 * The IHO Clock is Internal High-speed Oscillator, which is present in CAT1B(48MHz) 912 * and CAT1D(50MHz) devices. 913 * 914 * \defgroup group_sysclk_iho_funcs Functions 915 * \defgroup group_sysclk_clk_iho_enums Enumerated Types 916 * \} 917 * \defgroup group_sysclk_imo Internal Main Oscillator(IMO) Clock 918 * \{ 919 * The IMO Clock is Internal Main Oscillator, which is present in CAT1A/CAT1B/CAT1C and 920 * CAT1D devices, where as it is it is 8MHz in CAT1A/CAT1B/CAT1C, and CAT1D supports 921 * two instances of IMO i.e. 2MHz frequency (deep sleep capable) and separate 922 * instance with 4Mhz for LPPASS. 923 * 924 * \defgroup group_sysclk_imo_funcs Functions 925 * \defgroup group_sysclk_clk_imo_enums Enumerated Types 926 * \} 927 * \defgroup group_sysclk_clk_mem Mem Clock 928 * \{ 929 * Clock for the Memories 930 931 * \defgroup group_sysclk_clk_mem_funcs Functions 932 * \} 933 * \defgroup group_sysclk_clk_pwr Power Clock 934 * \{ 935 * Clock for the power architecture components. 936 937 * \defgroup group_sysclk_clk_pwr_funcs Functions 938 * \defgroup group_sysclk_clk_pwr_enums Enumerated Types 939 * \} 940 941 */ 942 943 #if !defined (CY_SYSCLK_H) 944 #define CY_SYSCLK_H 945 946 #include "cy_device.h" 947 948 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) 949 #include <stdbool.h> 950 #include "cy_syslib.h" 951 #include "cy_syspm.h" 952 953 #if defined(CY_DEVICE_SECURE) 954 #include "cy_pra.h" 955 #endif /* defined(CY_DEVICE_SECURE) */ 956 957 958 #if defined(__cplusplus) 959 extern "C" { 960 #endif /* __cplusplus */ 961 962 /** 963 * \addtogroup group_sysclk_macros 964 * \{ 965 */ 966 /** Driver major version */ 967 #define CY_SYSCLK_DRV_VERSION_MAJOR 3 968 /** Driver minor version */ 969 #define CY_SYSCLK_DRV_VERSION_MINOR 110 970 /** Sysclk driver identifier */ 971 #define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U) 972 973 /** ILO clock frequency */ 974 #define CY_SYSCLK_ILO_FREQ (32768UL) /* Hz */ 975 /** WCO clock frequency */ 976 #define CY_SYSCLK_WCO_FREQ (32768UL) /* Hz */ 977 /** PILO clock frequency */ 978 #define CY_SYSCLK_PILO_FREQ (32768UL) /* Hz */ 979 980 /** IMO clock frequency */ 981 #define CY_SYSCLK_IMO_FREQ (8000000UL) /* Hz */ 982 983 /** MFO clock frequency */ 984 #define CY_SYSCLK_MFO_FREQ (2000000UL) /* Hz */ 985 986 /** CY_SYSCLK_PILO_TRIM_STEP is the default PILO TRIM Step value */ 987 #define CY_SYSCLK_PILO_TRIM_STEP (5UL) /* Default PILO TRIM Step size */ 988 989 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) 990 /** 991 * \note 992 * This macro is available for CAT1B devices. 993 **/ 994 /** IHO clock frequency */ 995 #if defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL) 996 /** IHO frequency should be reverted to 48MHz on silicon DRIVERS-16084 */ 997 #define CY_SYSCLK_IHO_FREQ (24000000UL) /* Hz */ 998 #else 999 #define CY_SYSCLK_IHO_FREQ (48000000UL) /* Hz */ 1000 #endif 1001 1002 #elif defined (CY_IP_MXS22SRSS) 1003 /** 1004 * \note 1005 * This macro is available for CAT1D devices. 1006 **/ 1007 /** IHO clock frequency */ 1008 #define CY_SYSCLK_IHO_FREQ (50000000UL) /* Hz for PSE84 */ 1009 #endif /* CY_IP_MXS40SSRSS,CY_IP_MXS28SRSS*/ 1010 1011 1012 #if defined (CY_IP_MXS40SRSS) 1013 /** 1014 * \note 1015 * This macro is available for CAT1A devices. 1016 **/ 1017 /** ECO clock frequency */ 1018 #define CY_SYSCLK_ECO_FREQ (4000000UL) /* Hz */ 1019 #endif /* CY_IP_MXS40SRSS */ 1020 1021 1022 #if defined (CY_IP_MXS22SRSS) 1023 /** Timer clock frequency */ 1024 #define CY_SYSCLK_TIMER_CLK_FREQ (1000000UL) /* Hz */ 1025 #endif 1026 1027 #if defined (CY_IP_MXS40SSRSS)|| defined (CY_IP_MXS22SRSS) 1028 /** FLL BYPASS configure Delay , As per SAS 1029 * "When changing BYPASS_SEL, do not turn off the reference clock 1030 * or CCO clock for ten cycles (whichever is slower)" 1031 * Slower if IMO, so delay = (10 * 1/(IMO freq in Mhz)) = 1.25 micro seconds, 1032 * approximated to 2 micro second 1033 **/ 1034 #define CY_SYSCLK_BYPASS_CONFIGURE_DELAY (2UL) /* micro seconds */ 1035 1036 /** FLL Disable Timeout value 1037 **/ 1038 #define CY_SYSCLK_FLL_DISABLE_TIMEOUT (100UL) /* micro seconds */ 1039 1040 #else 1041 1042 /** FLL BYPASS configure Delay , As per SAS 1043 * "When changing BYPASS_SEL, do not turn off the reference clock 1044 * or CCO clock for seven cycles (whichever is slower)" 1045 * Slower if IMO, so delay = (7 * 1/(IMO freq in Mhz)) = 0.875 micro seconds, 1046 * approximated to 1 micro second 1047 **/ 1048 #define CY_SYSCLK_BYPASS_CONFIGURE_DELAY (1UL) /* micro seconds */ 1049 1050 /** FLL Disable Timeout value 1051 **/ 1052 #define CY_SYSCLK_FLL_DISABLE_TIMEOUT (100UL) /* micro seconds */ 1053 1054 #endif /* defined (CY_IP_MXS40SSRSS)|| defined (CY_IP_MXS22SRSS) */ 1055 1056 1057 /******************************************************************************* 1058 * Internal Defines 1059 *******************************************************************************/ 1060 #if defined (CY_IP_MXS22SRSS) 1061 /** 1062 * \note 1063 * This macro is valid for CAT1D devices. 1064 **/ 1065 /* Macro to validate parameters in Cy_SysClk_ClkPathSetSource() function */ 1066 #define CY_SYSCLK_IS_CLKPATH_SOURCE_VALID(clkSrc) (((clkSrc) == CY_SYSCLK_CLKPATH_IN_IHO) || \ 1067 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_EXT) || \ 1068 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ECO) || \ 1069 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_IMO) || \ 1070 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_WCO) || \ 1071 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_PILO)) 1072 #elif defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2) 1073 /** 1074 * \note 1075 * This macro is valid for CAT1A (TVIIBE only) and CAT1C devices. 1076 **/ 1077 /* Macro to validate parameters in Cy_SysClk_ClkPathSetSource() function */ 1078 #define CY_SYSCLK_IS_CLKPATH_SOURCE_VALID(clkSrc) (((clkSrc) == CY_SYSCLK_CLKPATH_IN_IMO) || \ 1079 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_EXT) || \ 1080 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ECO) || \ 1081 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ILO0) || \ 1082 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_WCO) || \ 1083 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ILO1)) 1084 #elif defined (CY_IP_MXS40SSRSS) 1085 /** 1086 * \note 1087 * This macro is valid for CAT1B devices. 1088 **/ 1089 /* Macro to validate parameters in Cy_SysClk_ClkPathSetSource() function */ 1090 #define CY_SYSCLK_IS_CLKPATH_SOURCE_VALID(clkSrc) (((clkSrc) == CY_SYSCLK_CLKPATH_IN_IMO) || \ 1091 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_EXT) || \ 1092 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ALTHF) || \ 1093 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_IHO) || \ 1094 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ILO) || \ 1095 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_WCO) || \ 1096 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_PILO)) 1097 #else 1098 /** 1099 * \note 1100 * This macro is valid for CAT1A devices (excluding TVIIBE). 1101 **/ 1102 /* Macro to validate parameters in Cy_SysClk_ClkPathSetSource() function */ 1103 #define CY_SYSCLK_IS_CLKPATH_SOURCE_VALID(clkSrc) (((clkSrc) == CY_SYSCLK_CLKPATH_IN_IMO) || \ 1104 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_EXT) || \ 1105 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ALTHF) || \ 1106 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ECO) || \ 1107 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ILO) || \ 1108 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_WCO) || \ 1109 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_PILO) 1110 #endif 1111 1112 /** \} group_sysclk_macros */ 1113 1114 1115 /** 1116 * \addtogroup group_sysclk_returns 1117 * \{ 1118 */ 1119 /** Defines general-purpose function return values */ 1120 typedef enum 1121 { 1122 CY_SYSCLK_SUCCESS = 0x00UL, /**< Command completed with no errors */ 1123 CY_SYSCLK_BAD_PARAM = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x01UL), /**< Invalid function input parameter */ 1124 CY_SYSCLK_TIMEOUT = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x02UL), /**< Timeout occurred */ 1125 CY_SYSCLK_INVALID_STATE = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x03UL), /**< Clock is in an invalid state */ 1126 CY_SYSCLK_UNSUPPORTED_STATE = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x04UL) /**< Feature Unsupported */ 1127 } cy_en_sysclk_status_t; 1128 /** \} group_sysclk_returns */ 1129 1130 1131 /* ========================================================================== */ 1132 /* =========================== EXT SECTION ============================ */ 1133 /* ========================================================================== */ 1134 1135 /** \cond INTERNAL */ 1136 #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) 1137 /* Internal storage for external clock frequency user setting */ 1138 extern uint32_t cySysClkExtFreq; 1139 #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ 1140 /** \endcond */ 1141 1142 /** 1143 * \addtogroup group_sysclk_ext_funcs 1144 * \{ 1145 */ 1146 /******************************************************************************* 1147 * Function Name: Cy_SysClk_ExtClkSetFrequency 1148 ****************************************************************************//** 1149 * 1150 * Sets the signal frequency of the External Clock Source (EXTCLK) into the 1151 * internal storage to be used in \ref Cy_SysClk_ClkHfGetFrequency. 1152 * 1153 * \param freq The frequency of the External Clock Source. 1154 * 1155 * \funcusage 1156 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency 1157 * 1158 *******************************************************************************/ 1159 void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); 1160 1161 1162 /******************************************************************************* 1163 * Function Name: Cy_SysClk_ExtClkGetFrequency 1164 ****************************************************************************//** 1165 * 1166 * Returns the frequency of the External Clock Source (EXTCLK) from the 1167 * internal storage. 1168 * 1169 * \return The frequency of the External Clock Source. 1170 * 1171 * \funcusage 1172 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency 1173 * 1174 *******************************************************************************/ 1175 uint32_t Cy_SysClk_ExtClkGetFrequency(void); 1176 /** \} group_sysclk_ext_funcs */ 1177 1178 /* ========================================================================== */ 1179 /* =========================== ECO SECTION ============================ */ 1180 /* ========================================================================== */ 1181 1182 /** 1183 * \addtogroup group_sysclk_macros 1184 * \{ 1185 */ 1186 1187 /** 1188 * \defgroup group_sysclk_ecostatus ECO status 1189 * \{ 1190 * Constants used for expressing ECO status. 1191 */ 1192 #define CY_SYSCLK_ECOSTAT_AMPLITUDE 0UL /**< \brief ECO does not have sufficient amplitude */ 1193 #define CY_SYSCLK_ECOSTAT_INACCURATE 1UL /**< \brief ECO may not be meeting accuracy and duty cycle specs */ 1194 #define CY_SYSCLK_ECOSTAT_STABLE 2UL /**< \brief ECO has fully stabilized */ 1195 1196 #if defined (CY_IP_MXS28SRSS) 1197 /** 1198 * \note 1199 * This macro is available for CAT1B devices. 1200 **/ 1201 #define CY_SYSCLK_ECOSTAT_BLE_DISABLED 0UL /**< \brief ECO for BLE is disabled */ 1202 /** 1203 * \note 1204 * This macro is available for CAT1B devices. 1205 **/ 1206 #define CY_SYSCLK_ECOSTAT_BLE_ENABLED 1UL /**< \brief ECO for BLE is enabled */ 1207 #endif /* CY_IP_MXS28SRSS */ 1208 1209 /** \} group_sysclk_ecostatus */ 1210 1211 #if defined (CY_IP_MXS22SRSS) 1212 1213 /** \cond internal */ 1214 #define CY_SYSCLK_CLK_ECO_CTRIM_MIN 0x0U 1215 #define CY_SYSCLK_CLK_ECO_CTRIM_MAX 0x1FU 1216 1217 #define CY_SYSCLK_CLK_ECO_GTRIM_MIN 0x0U 1218 #define CY_SYSCLK_CLK_ECO_GTRIM_MAX 0xFU 1219 1220 1221 #define CY_SYSCLK_IS_CLK_ECO_CTRIM_VALID(clkCtrim) ((clkCtrim) <= CY_SYSCLK_CLK_ECO_CTRIM_MAX) 1222 1223 #define CY_SYSCLK_IS_CLK_ECO_GTRIM_VALID(clkGtrim) ((clkGtrim) <= CY_SYSCLK_CLK_ECO_GTRIM_MAX) 1224 /** \endcond */ 1225 1226 #endif 1227 1228 # if (defined (CY_DEVICE_SECURE)) 1229 /** 1230 * \note 1231 * This structure is available for CAT1A devices. 1232 **/ 1233 /** PRA structure for Cy_SysClk_EcoConfigure function parameters */ 1234 typedef struct 1235 { 1236 uint32_t praClkEcofreq; /**< freq */ 1237 uint32_t praCsum; /**< cSum */ 1238 uint32_t praEsr; /**< esr */ 1239 uint32_t praDriveLevel; /**< drivelevel */ 1240 } cy_stc_pra_clk_eco_configure_t; 1241 #endif /* (defined (CY_DEVICE_SECURE)) */ 1242 1243 1244 1245 #if defined (CY_IP_MXS22SRSS) 1246 /** 1247 * \note 1248 * This structure is available for CAT1D devices. 1249 **/ 1250 /** structure for Cy_SysClk_EcoManualConfigure function parameters */ 1251 typedef struct 1252 { 1253 uint32_t ecoClkfreq; /**< freq in Hz */ 1254 uint32_t ecoCtrim; /**< ctrim */ 1255 uint32_t ecoGtrim; /**< gtrim */ 1256 bool ecoIboost; /**< iboost */ 1257 } cy_stc_clk_eco_config_t; 1258 #endif 1259 1260 1261 /** \} group_sysclk_macros */ 1262 1263 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL)) 1264 /** \cond */ 1265 /** 1266 * \note 1267 * This macro is available for CAT1A, CAT1B, CAT1C, and CAT1D devices. 1268 **/ 1269 #define SRSS_CLK_ECO_STATUS_Msk (SRSS_CLK_ECO_STATUS_ECO_OK_Msk | SRSS_CLK_ECO_STATUS_ECO_READY_Msk) 1270 /** \endcond */ 1271 #endif /* defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS) */ 1272 1273 #if defined (CY_IP_MXS28SRSS) 1274 /** \cond */ 1275 /** 1276 * \note 1277 * It is available for CAT1B devices. 1278 **/ 1279 #define SRSS_CLK_ECO_STATUS_Msk (SRSS_CLK_ECO_STATUS_ECO_CORE_READY_Msk | SRSS_CLK_ECO_STATUS_ECO_CORE_AMP_OK_Msk) 1280 1281 /** \endcond */ 1282 #endif /* CY_IP_MXS28SRSS */ 1283 1284 1285 1286 #if defined (CY_IP_MXS28SRSS) 1287 /** 1288 * \addtogroup group_sysclk_eco_enums 1289 * \{ 1290 */ 1291 /** 1292 * ECO enable options for BLE 1293 */ 1294 /** 1295 * \note 1296 * This enum is available for CAT1B devices. 1297 **/ 1298 typedef enum 1299 { 1300 CY_SYSCLK_ECO_BLESS_CONTROL0 = 0U, /**< 0, 1: hardware controlled by BLESS. */ 1301 CY_SYSCLK_ECO_BLESS_CONTROL1 = 1U, /**< 0, 1: hardware controlled by BLESS. */ 1302 CY_SYSCLK_ECO_FORCE_ENABLE = 2U, /**< Force ECO enabled for use by BLE */ 1303 CY_SYSCLK_ECO_FORCE_DISABLE = 3U, /**< Force ECO disabled for use by BLE */ 1304 } cy_en_eco_for_ble_t; 1305 /** \} group_sysclk_eco_enums */ 1306 #endif /* CY_IP_MXS28SRSS */ 1307 1308 /** 1309 * \addtogroup group_sysclk_eco_funcs 1310 * \{ 1311 */ 1312 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) || \ 1313 (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL)) || defined (CY_DOXYGEN) 1314 /******************************************************************************* 1315 * Function Name: Cy_SysClk_EcoSetFrequency 1316 ****************************************************************************//** 1317 * 1318 * Stores the external crystal oscillator (ECO) frequency in a global variable 1319 * within Sysclk driver. 1320 * 1321 * \param freq Operating frequency of the crystal in Hz. 1322 * Valid range: 16000000...35000000 (16..35 MHz). 1323 * 1324 * \note 1325 * This API is available for CAT1A (excluding TVIIBE), CAT1B, CAT1C and CAT1D devices. 1326 * 1327 *******************************************************************************/ 1328 void Cy_SysClk_EcoSetFrequency(uint32_t freq); 1329 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) */ 1330 1331 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL)) 1332 1333 1334 #if defined (CY_IP_MXS22SRSS) 1335 /******************************************************************************* 1336 * Function Name: Cy_SysClk_EcoManualConfigure 1337 ****************************************************************************//** 1338 * 1339 * Configures the external crystal oscillator (ECO) trim bits based on crystal 1340 * characteristics. This function should be called only when the ECO is disabled. 1341 * 1342 * \param ecoConfig \ref cy_stc_clk_eco_config_t 1343 * 1344 * \note 1345 * This API expects the trims to be calculated outside this API scope, so refer 1346 * and use the ECO calculators excel sheet for the platform to obtain the 1347 * trims. 1348 * 1349 * \return Error / status code: \n 1350 * CY_SYSCLK_SUCCESS - ECO configuration completed successfully \n 1351 * CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n 1352 * CY_SYSCLK_INVALID_STATE - ECO already enabled 1353 * 1354 * \note 1355 * This API is available for CAT1D devices. 1356 * 1357 * \funcusage 1358 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoManualConfigure 1359 * 1360 *******************************************************************************/ 1361 cy_en_sysclk_status_t Cy_SysClk_EcoManualConfigure(const cy_stc_clk_eco_config_t *ecoConfig); 1362 1363 1364 #else 1365 /******************************************************************************* 1366 * Function Name: Cy_SysClk_EcoConfigure 1367 ****************************************************************************//** 1368 * 1369 * Configures the external crystal oscillator (ECO) trim bits based on crystal 1370 * characteristics. This function should be called only when the ECO is disabled. 1371 * 1372 * \param freq Operating frequency of the crystal in Hz. 1373 * Valid range: 16000000...35000000 (16..35 MHz). 1374 * 1375 * \param cSum The summary capacitance of 1376 * C0 (the crystal itself shunt capacitance) and 1377 * Cload (the parallel load capacitance), in pF. 1378 * So cSum = C0 + Cload. 1379 * Valid range: 1...100. 1380 * \note 1381 * For CAT1B Devices: 1382 * cSum stands for crystal load capacitance in pF. 1383 * 1384 * \param esr Effective series resistance of the crystal in Ohms. 1385 * Valid range: 1...1000. 1386 * 1387 * \param driveLevel Crystal drive level in uW. 1388 * Valid range: 1...2000. 1389 * 1390 * \return Error / status code: \n 1391 * CY_SYSCLK_SUCCESS - ECO configuration completed successfully \n 1392 * CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n 1393 * CY_SYSCLK_INVALID_STATE - ECO already enabled 1394 * \note Behavior of this API is IP dependent. \n 1395 * On CAT1A device: \n 1396 * 1397 * For the PSoC 64 devices there are possible situations when function returns 1398 * the PRA error status code. This is because for PSoC 64 devices the function 1399 * uses the PRA driver to change the protected registers. Refer to 1400 * \ref cy_en_pra_status_t for more details. 1401 * The following calculations are implemented in the 32-bit integer math: 1402 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1403 * after \ref Cy_SysClk_EcoEnable call. 1404 * 1405 * \verbatim 1406 * freqKhz = freq / 1000 1407 * maxAmpl = sqrt(drivelevel / 2 / esr) / 3.14 / freqKhz / cSum 1408 * ampSect = INT(5 * 4 * 3.14^2 * freqKhz^2 * cSum^2 * 4 * esr / 1000000000 / 1000000 / 9) 1409 * As a result of the above calculations, max amplitude must be >= 0.65V, and the 1410 * number of amplifier sections must be <= 3, otherwise this function returns with 1411 * a parameter error. 1412 * 1413 * atrim = 15 1414 * agc_en = 1 1415 * wdtrim = 7 1416 * gtrim = ampSect > 1 ? ampSect : ampSect == 1 ? 0 : 1 1417 * rtrim = 0 1418 * ftrim = 3 1419 * \endverbatim 1420 * 1421 * \note 1422 * On CAT1C Device: \n 1423 * 1424 * \verbatim 1425 1426 * No TRIM registers configuration required for CAT1B devices, For legacy API is emptied 1427 * The following calculations are implemented, generally in floating point: 1428 * freqMHz = freq / 1000000 1429 * max amplitude Vpp = 1000 * sqrt(drivelevel / 2 / esr) / 3.14 / freqMHz / cLoad 1430 * gm_min mA/V = 5 * 4 * 3.14 * 3.14 * freqMhz^2 * cLoad^2 * 4 * esr / 1000000000 1431 * Number of amplifier sections = INT(gm_min / 4.5) 1432 * 1433 * As a result of the above calculations, max amplitude must be >= 0.5, and the 1434 * number of amplifier sections must be <= 3, otherwise this function returns with 1435 * a parameter error. 1436 * 1437 * atrim = if (max amplitude < 0.5) then error 1438 * else 2 * the following: 1439 * max amplitude < 0.6: 0 1440 * max amplitude < 0.7: 1 1441 * max amplitude < 0.8: 2 1442 * max amplitude < 0.9: 3 1443 * max amplitude < 1.15: 5 1444 * max amplitude < 1.275: 6 1445 * max amplitude >= 1.275: 7 1446 * wdtrim = if (max amplitude < 0.5) then error 1447 * else 2 * the following: 1448 * max amplitude < 1.2: INT(5 * max amplitude) - 2 1449 * max amplitude >= 1.2: 3 1450 * gtrim = if (number of amplifier sections > 3) then error 1451 * else the following: 1452 * number of amplifier sections > 1: number of amplifier sections 1453 * number of amplifier sections = 1: 0 1454 * number of amplifier sections < 1: 1 1455 * rtrim = if (gtrim = error) then error 1456 * else the following: 1457 * freqMHz > 26.8: 0 1458 * freqMHz > 23.33: 1 1459 * freqMHz > 16.5: 2 1460 * freqMHz <= 16.5: 3 1461 * ftrim = if (atrim = error) then error 1462 * else INT(atrim / 2) 1463 * \endverbatim 1464 * 1465 * \note 1466 * This API is available for CAT1A, CAT1C and CAT1D devices. 1467 * 1468 * \funcusage 1469 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoConfigure 1470 * 1471 *******************************************************************************/ 1472 cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint32_t esr, uint32_t driveLevel); 1473 1474 #endif /* defined (CY_IP_MXS22SRSS) */ 1475 1476 1477 /******************************************************************************* 1478 * Function Name: Cy_SysClk_EcoEnable 1479 ****************************************************************************//** 1480 * 1481 * Enables the external crystal oscillator (ECO). This function should be called 1482 * after \ref Cy_SysClk_EcoConfigure. 1483 * 1484 * \param timeoutus Amount of time in microseconds to wait for the ECO to stabilize. 1485 * To avoid waiting for stabilization, set this parameter to 0. 1486 * 1487 * \return Error / status code: \n 1488 * CY_SYSCLK_SUCCESS - ECO locked \n 1489 * CY_SYSCLK_TIMEOUT - ECO timed out and did not lock \n 1490 * CY_SYSCLK_INVALID_STATE - ECO already enabled \n 1491 * CY_SYSCLK_UNSUPPORTED_STATE - ECO is not present 1492 * For the PSoC 64 devices there are possible situations when function returns 1493 * the PRA error status code. This is because for PSoC 64 devices the function 1494 * uses the PRA driver to change the protected registers. Refer to 1495 * \ref cy_en_pra_status_t for more details. 1496 * 1497 * \note 1498 * Call \ref SystemCoreClockUpdate after this function calling 1499 * if it affects the CLK_HF0 frequency. 1500 * 1501 * \note 1502 * This API is available for CAT1A & CAT1C devices. 1503 * 1504 * \note 1505 * Take into account the possible platform specific clkHf (and further 1506 * clocking chain links) frequency limitations while using this API. 1507 * 1508 * \funcusage 1509 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable 1510 * 1511 *******************************************************************************/ 1512 cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus); 1513 1514 /******************************************************************************* 1515 * Function Name: Cy_SysClk_EcoGetFrequency 1516 ****************************************************************************//** 1517 * 1518 * Returns the frequency of the external crystal oscillator (ECO). 1519 * 1520 * \return The frequency of the ECO. 1521 * 1522 * \note If the ECO is not enabled or stable - a zero is returned. 1523 * 1524 * \funcusage 1525 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable 1526 * 1527 * \note 1528 * This API is available for CAT1A, CAT1B(PSoC C3), CAT1C & CAT1D devices. 1529 * 1530 *******************************************************************************/ 1531 uint32_t Cy_SysClk_EcoGetFrequency(void); 1532 1533 /******************************************************************************* 1534 * Function Name: Cy_SysClk_EcoDisable 1535 ****************************************************************************//** 1536 * 1537 * Disables the external crystal oscillator (ECO). This function should not be 1538 * called if the ECO is sourcing clkHf[0]. 1539 * 1540 * \funcusage 1541 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoDisable 1542 * 1543 * \note 1544 * This API is available for CAT1A, CAT1C devices. 1545 * 1546 *******************************************************************************/ 1547 void Cy_SysClk_EcoDisable(void); 1548 1549 1550 /******************************************************************************* 1551 * Function Name: Cy_SysClk_EcoGetStatus 1552 ****************************************************************************//** 1553 * 1554 * Reports the current status of the external crystal oscillator (ECO). 1555 * 1556 * \return 1557 * CY_SYSCLK_ECOSTAT_AMPLITUDE = ECO does not have sufficient amplitude \n 1558 * CY_SYSCLK_ECOSTAT_INACCURATE = ECO has sufficient amplitude but may not be meeting accuracy and duty cycle specifications \n 1559 * CY_SYSCLK_ECOSTAT_STABLE = ECO has fully stabilized 1560 * 1561 * \note 1562 * This API is available for CAT1A, CAT1C devices. 1563 * 1564 * \funcusage 1565 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoGetStatus 1566 * 1567 *******************************************************************************/ 1568 uint32_t Cy_SysClk_EcoGetStatus(void); 1569 #endif /* defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL)) */ 1570 1571 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL)) 1572 1573 /******************************************************************************* 1574 * Function Name: Cy_SysClk_EcoPrescaleConfigure 1575 ****************************************************************************//** 1576 * 1577 * Configures the external crystal oscillator (ECO) using ECO Prescaler 1578 * Configuration Register and derives clk_eco_prescaler 1579 * 1580 * \param enable ECO Prescaler enable/disable. 1581 * 1582 * \param int_div 10-bit integer value. 1583 * 1584 * \param frac_div 8-bit fraction value. 1585 * 1586 * \return Error / status code: \n 1587 * CY_SYSCLK_SUCCESS - ECO configuration completed successfully \n 1588 * CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n 1589 * CY_SYSCLK_INVALID_STATE - ECO already enabled \n 1590 * CY_SYSCLK_UNSUPPORTED_STATE - ECO is not present 1591 * 1592 * \note 1593 * This API is available for CAT1A (TVIIBE only) and CAT1C devices. 1594 * 1595 *******************************************************************************/ 1596 cy_en_sysclk_status_t Cy_SysClk_EcoPrescaleConfigure(uint32_t enable, uint32_t int_div, uint32_t frac_div); 1597 1598 /******************************************************************************* 1599 * Function Name: Cy_SysClk_EcoPrescaleIsEnabled 1600 ****************************************************************************//** 1601 * 1602 * Reports whether or not ECO Prescale is enabled. 1603 * 1604 * \return 1605 * false = disabled \n 1606 * true = enabled 1607 * 1608 * \note 1609 * This API is available for CAT1A (TVIIBE only) and CAT1C devices. 1610 * 1611 *******************************************************************************/ 1612 bool Cy_SysClk_EcoPrescaleIsEnabled(void); 1613 1614 1615 /******************************************************************************* 1616 * Function Name: Cy_SysClk_EcoPrescaleGetFrequency 1617 ****************************************************************************//** 1618 * 1619 * Returns the frequency of the external crystal oscillator (ECO) prescaler. 1620 * 1621 * \return The frequency of the ECO Prescaler. 1622 * 1623 * \note If the ECO is not enabled or stable - a zero is returned. 1624 * 1625 * \note 1626 * This API is available for CAT1B(PSoC C3), CAT1C & CAT1D devices. 1627 * 1628 *******************************************************************************/ 1629 uint32_t Cy_SysClk_EcoPrescaleGetFrequency(void); 1630 1631 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL))*/ 1632 1633 #if defined (CY_IP_MXS28SRSS) 1634 /******************************************************************************* 1635 * Function Name: Cy_SysClk_EcoBleEnable 1636 ****************************************************************************//** 1637 * 1638 * Enables the external crystal oscillator (ECO) for BlueTooth Usage. This function should be called 1639 * after \ref Cy_SysClk_EcoConfigure. 1640 * 1641 * \param control To be selected from \ref cy_en_eco_for_ble_t 1642 * 1643 * \param timeoutus timeoutus 1644 * 1645 * \return Error / status code: \n 1646 * CY_SYSCLK_SUCCESS - ECO locked \n 1647 * CY_SYSCLK_TIMEOUT - ECO timed out and did not lock \n 1648 * CY_SYSCLK_INVALID_STATE - ECO already enabled \n 1649 * CY_SYSCLK_UNSUPPORTED_STATE - ECO is not present 1650 * 1651 * \note 1652 * This API is available for CAT1B devices. 1653 * 1654 *******************************************************************************/ 1655 cy_en_sysclk_status_t Cy_SysClk_EcoBleControl(cy_en_eco_for_ble_t control, uint32_t timeoutus); 1656 1657 /******************************************************************************* 1658 * Function Name: Cy_SysClk_EcoBleGetStatus 1659 ****************************************************************************//** 1660 * 1661 * Reports the current status w.r.to BLE of the external crystal oscillator (ECO). 1662 * 1663 * \return 1664 * CY_SYSCLK_ECOSTAT_BLE_ENABLED = ECO for BLE is enabled \n 1665 * CY_SYSCLK_ECOSTAT_BLE_DISABLED = ECO for BLE is not enabled 1666 * 1667 * \note 1668 * This API is available for CAT1B devices. 1669 * 1670 *******************************************************************************/ 1671 uint32_t Cy_SysClk_EcoBleGetStatus(void); 1672 #endif /* defined (CY_IP_MXS28SRSS) */ 1673 1674 /** \} group_sysclk_eco_funcs */ 1675 1676 1677 /* ========================================================================== */ 1678 /* ========================== LPECO SECTION =========================== */ 1679 /* ========================================================================== */ 1680 1681 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) && (defined (SRSS_BACKUP_S40E_LPECO_PRESENT) && (SRSS_BACKUP_S40E_LPECO_PRESENT == 1u)) 1682 1683 /** 1684 * \addtogroup group_sysclk_lpeco_enums 1685 * \{ 1686 */ 1687 /** 1688 * Backup domain LPECO load capacitance range. 1689 */ 1690 /** 1691 * \note 1692 * This enum is available for TVIIC devices. 1693 **/ 1694 typedef enum 1695 { 1696 CY_SYSCLK_BAK_LPECO_LCAP_5TO10PF = 0u, /**< Backup domain LPECO load is in range [5pF, 10pF] */ 1697 CY_SYSCLK_BAK_LPECO_LCAP_10TO15PF = 1u, /**< Backup domain LPECO load is in range (10pF, 15pF] */ 1698 CY_SYSCLK_BAK_LPECO_LCAP_15TO20PF = 2u, /**< Backup domain LPECO load is in range (15pF, 20pF] */ 1699 CY_SYSCLK_BAK_LPECO_LCAP_20TO25PF = 3u, /**< Backup domain LPECO load is in range (20pF, 25pF] */ 1700 1701 } cy_en_clkbak_lpeco_loadcap_range_t; 1702 1703 /** 1704 * Backup domain LPECO crystal frequency range. 1705 */ 1706 /** 1707 * \note 1708 * This enum is available for TVIIC devices. 1709 **/ 1710 typedef enum 1711 { 1712 CY_SYSCLK_BAK_LPECO_FREQ_4TO6MHZ = 0u, /**< Backup domain LPECO frequency is in range [4MHz, 6MHz) */ 1713 CY_SYSCLK_BAK_LPECO_FREQ_6TO8MHZ = 1u, /**< Backup domain LPECO frequency is in range [6MHz, 8MHz] */ 1714 1715 } cy_en_clkbak_lpeco_frequency_range_t; 1716 1717 /** 1718 * Backup domain LPECO crystal oscillation amplitude. 1719 */ 1720 /** 1721 * \note 1722 * This enum is available for TVIIC devices. 1723 **/ 1724 typedef enum 1725 { 1726 CY_SYSCLK_BAK_LPECO_AMP_MAX_1P35V = 0u, /**< Backup domain LPECO maximum amplitude is 1.35V. This is the lowest power setting. */ 1727 CY_SYSCLK_BAK_LPECO_AMP_MAX_1P8V = 1u, /**< Backup domain LPECO maximum amplitude is 1.8V. This is the lowest jitter setting. */ 1728 1729 } cy_en_clkbak_lpeco_max_amplitude_t; 1730 1731 /** 1732 * Backup domain LPECO minimum amplitude detection. 1733 */ 1734 /** 1735 * \note 1736 * This enum is available for TVIIC devices. 1737 **/ 1738 typedef enum 1739 { 1740 CY_SYSCLK_BAK_LPECO_AMPDET_INIT_EN = 0u, /**< Initially enabled, and then automatically disabled when amplitude detector detects sufficient amplitude. */ 1741 CY_SYSCLK_BAK_LPECO_AMPDET_ALWAYS_EN = 1u, /**< Keep minimum amplitude detector enabled as long as LPECO is enabled */ 1742 1743 } cy_en_clkbak_lpeco_amplitude_detect_t; 1744 /** \} group_sysclk_lpeco_enums */ 1745 1746 1747 /** 1748 * \addtogroup group_sysclk_lpeco_funcs 1749 * \{ 1750 */ 1751 1752 /******************************************************************************* 1753 * Function Name: Cy_SysClk_LpEcoConfigure 1754 ****************************************************************************//** 1755 * 1756 * Configures the low-power external crystal oscillator based on crystal characteristics 1757 * 1758 * \param capValue \ref cy_en_clkbak_lpeco_loadcap_range_t 1759 * 1760 * \param freqValue \ref cy_en_clkbak_lpeco_frequency_range_t 1761 * 1762 * \param ampValue \ref cy_en_clkbak_lpeco_max_amplitude_t 1763 * 1764 * \param ampDetEn Enable amplitude detection always (true) or only on init (false) 1765 * 1766 * \note 1767 * This API is available for TVIIC devices. 1768 * 1769 * \funcusage 1770 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_LpEcoConfigure 1771 * 1772 *******************************************************************************/ 1773 void Cy_SysClk_LpEcoConfigure(cy_en_clkbak_lpeco_loadcap_range_t capValue, 1774 cy_en_clkbak_lpeco_frequency_range_t freqValue, 1775 cy_en_clkbak_lpeco_max_amplitude_t ampValue, 1776 bool ampDetEn); 1777 1778 /******************************************************************************* 1779 * Function Name: Cy_SysClk_LpEcoEnable 1780 ****************************************************************************//** 1781 * 1782 * Enables the low-power external crystal oscillator (LPECO). This function should 1783 * be called after \ref Cy_SysClk_LpEcoConfigure. 1784 * 1785 * \param timeoutus Amount of time in microseconds to wait for the LPECO to stabilize. 1786 * To avoid waiting for stabilization, set this parameter to 0. 1787 * 1788 * \return Error / status code: \n 1789 * CY_SYSCLK_SUCCESS - ECO locked \n 1790 * CY_SYSCLK_TIMEOUT - ECO timed out and did not lock \n 1791 * CY_SYSCLK_INVALID_STATE - ECO already enabled 1792 * 1793 * \note 1794 * Call \ref SystemCoreClockUpdate after this function calling 1795 * if it affects the CLK_HF0 or CLK_HF1 frequency. 1796 * 1797 * \note 1798 * This API is available for TVIIC devices. 1799 * 1800 * \funcusage 1801 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_LpEcoEnable 1802 * 1803 *******************************************************************************/ 1804 cy_en_sysclk_status_t Cy_SysClk_LpEcoEnable(uint32_t timeoutus); 1805 1806 /******************************************************************************* 1807 * Function Name: Cy_SysClk_LpEcoDisable 1808 ****************************************************************************//** 1809 * 1810 * Disables the low-power external crystal oscillator (LPECO). This function 1811 * should not be called if the LPECO is sourcing clkHf[0] or clkHf[1]. 1812 * 1813 * \note 1814 * This API is available for TVIIC devices. 1815 * 1816 * \funcusage 1817 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_LpEcoDisable 1818 * 1819 *******************************************************************************/ 1820 void Cy_SysClk_LpEcoDisable(void); 1821 1822 /******************************************************************************* 1823 * Function Name: Cy_SysClk_LpEcoSetFrequency 1824 ****************************************************************************//** 1825 * 1826 * Stores the low-power external crystal oscillator (LPECO) frequency in a global 1827 * variable within Sysclk driver. 1828 * 1829 * \param freq Operating frequency of the crystal in Hz. 1830 * Valid range: 3990000...8010000 (3.99..8.01 MHz). 1831 * 1832 * \note 1833 * This API is available for TVIIC devices. 1834 * 1835 *******************************************************************************/ 1836 void Cy_SysClk_LpEcoSetFrequency(uint32_t freq); 1837 1838 /******************************************************************************* 1839 * Function Name: Cy_SysClk_LpEcoGetFrequency 1840 ****************************************************************************//** 1841 * 1842 * Returns the frequency of the low-power external crystal oscillator (LPECO). 1843 * 1844 * \return The frequency of the LPECO in Hz. 1845 * 1846 * \note If the LPECO is not enabled or stable - a zero is returned. 1847 * 1848 * \note 1849 * This API is available for TVIIC devices. 1850 * 1851 *******************************************************************************/ 1852 uint32_t Cy_SysClk_LpEcoGetFrequency(void); 1853 1854 /******************************************************************************* 1855 * Function Name: Cy_SysClk_LpEcoPrescaleConfigure 1856 ****************************************************************************//** 1857 * 1858 * Configures the low-power external crystal oscillator (LPECO) Prescaler 1859 * and derives clk_lpeco_prescaler 1860 * 1861 * \param enable LPECO Prescaler enable/disable. 1862 * 1863 * \param int_div 10-bit integer value. Subtract one from the desired divide value 1864 * when using this parameter. For example , to divide by 1, int_div should be set 1865 * to 0. 1866 * 1867 * \param frac_div 8-bit fraction value. 1868 * 1869 * \return Error / status code: \n 1870 * CY_SYSCLK_SUCCESS - LPECO prescaler configuration completed successfully \n 1871 * CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n 1872 * CY_SYSCLK_INVALID_STATE - LPECO already enabled 1873 * 1874 * \note 1875 * This API is available for TVIIC devices. 1876 * 1877 * \funcusage 1878 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_LpEcoPrescaleConfigure 1879 * 1880 *******************************************************************************/ 1881 cy_en_sysclk_status_t Cy_SysClk_LpEcoPrescaleConfigure(bool enable, uint32_t int_div, uint32_t frac_div); 1882 1883 /******************************************************************************* 1884 * Function Name: Cy_SysClk_LpEcoPrescaleIsEnabled 1885 ****************************************************************************//** 1886 * 1887 * Reports whether or not LPECO Prescale is enabled. 1888 * 1889 * \return 1890 * false = disabled \n 1891 * true = enabled 1892 * 1893 * \note 1894 * This API is available for TVIIC devices. 1895 * 1896 *******************************************************************************/ 1897 bool Cy_SysClk_LpEcoPrescaleIsEnabled(void); 1898 1899 /******************************************************************************* 1900 * Function Name: Cy_SysClk_LpEcoAmplitudeOkay 1901 ****************************************************************************//** 1902 * 1903 * Reports the current status of the low-power external crystal oscillator (LPECO) 1904 * amplitude detection. 1905 * 1906 * \return 1907 * false = Insufficient oscillation amplitude OR the amplitude detector is off \n 1908 * true = Sufficient oscillation amplitude is detected 1909 * 1910 * \note 1911 * This API is available for TVIIC devices. 1912 * 1913 * \funcusage 1914 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_LpEcoAmplitudeOkay 1915 * 1916 *******************************************************************************/ 1917 bool Cy_SysClk_LpEcoAmplitudeOkay(void); 1918 1919 /******************************************************************************* 1920 * Function Name: Cy_SysClk_LpEcoIsReady 1921 ****************************************************************************//** 1922 * 1923 * Indicates whether or not the low-power external crystal oscillator (LPECO) 1924 * has had enough time to start. 1925 * 1926 * \return 1927 * false = LPECO not stable \n 1928 * true = LPECO stable 1929 * 1930 * \note 1931 * This API is available for TVIIC devices. 1932 * 1933 * \funcusage 1934 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_LpEcoIsReady 1935 * 1936 *******************************************************************************/ 1937 bool Cy_SysClk_LpEcoIsReady(void); 1938 1939 /** \} group_sysclk_lpeco_funcs */ 1940 1941 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) && (defined (SRSS_BACKUP_S40E_LPECO_PRESENT) && (SRSS_BACKUP_S40E_LPECO_PRESENT == 1u)) */ 1942 1943 /* ========================================================================== */ 1944 /* ==================== INPUT MULTIPLEXER SECTION ===================== */ 1945 /* ========================================================================== */ 1946 /** 1947 * \addtogroup group_sysclk_path_src_enums 1948 * \{ 1949 */ 1950 /** 1951 * Input multiplexer clock sources 1952 */ 1953 1954 1955 typedef enum 1956 { 1957 #if defined (CY_IP_MXS22SRSS) 1958 CY_SYSCLK_CLKPATH_IN_IHO = 0U, /**< Select the IHO as the output of the path mux */ 1959 CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */ 1960 CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */ 1961 CY_SYSCLK_CLKPATH_IN_IMO = 3U, /**< Select the IMO as the output of the path mux */ 1962 CY_SYSCLK_CLKPATH_IN_ALTHF0 = 4U, /**< Select the ALTHF0 as the output of the path mux */ 1963 CY_SYSCLK_CLKPATH_IN_ALTHF1 = 5U, /**< Select the ALTHF1 as the output of the path mux */ 1964 CY_SYSCLK_CLKPATH_IN_DSIMUX = 7U, /**< Select the DSI MUX output as the output of the path mux */ 1965 CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. 1966 * Make sure the DSI clock sources are available on used device. 1967 */ 1968 CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, /**< Select the ILO (16) as the output of the DSI mux and path mux */ 1969 CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */ 1970 CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux. 1971 * Make sure the ALTLF clock sources in available on used device. 1972 */ 1973 CY_SYSCLK_CLKPATH_IN_PILO = 0x113U, /**< Select the PILO (19) as the output of the DSI mux and path mux. 1974 * Make sure the PILO clock sources in available on used device. 1975 */ 1976 #elif defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2) 1977 CY_SYSCLK_CLKPATH_IN_IMO = 0U, /**< Select the IMO as the output of the path mux */ 1978 CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */ 1979 CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */ 1980 CY_SYSCLK_CLKPATH_IN_ALTHF = 3U, /**< Select the ALTHF as the output of the path mux */ 1981 CY_SYSCLK_CLKPATH_IN_DSIMUX = 4U, /**< Select the DSI MUX output as the output of the path mux */ 1982 CY_SYSCLK_CLKPATH_IN_LPECO = 5U, /**< Select the LPECO as the output of the path mux */ 1983 CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. 1984 * Make sure the DSI clock sources are available on used device. 1985 */ 1986 CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, 1987 CY_SYSCLK_CLKPATH_IN_ILO0 = CY_SYSCLK_CLKPATH_IN_ILO,/**< Select the ILO0 (16) as the output of the DSI mux and path mux */ 1988 CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */ 1989 CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux. 1990 * Make sure the ALTLF clock sources in available on used device. 1991 */ 1992 CY_SYSCLK_CLKPATH_IN_PILO = 0x113U, /**< Select the PILO (19) as the output of the DSI mux and path mux. 1993 * Make sure the PILO clock sources in available on used device. 1994 */ 1995 CY_SYSCLK_CLKPATH_IN_ILO1 = 0x114U, /**< Select the ILO1 (20) as the output of the DSI mux and path mux */ 1996 #elif defined (CY_IP_MXS40SSRSS) 1997 CY_SYSCLK_CLKPATH_IN_IMO = 0U, /**< Select the IMO as the output of the path mux */ 1998 CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */ 1999 CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */ 2000 CY_SYSCLK_CLKPATH_IN_ALTHF = 3U, /**< Select the ALTHF as the output of the path mux */ 2001 CY_SYSCLK_CLKPATH_IN_DSIMUX = 4U, /**< Select the DSI MUX output as the output of the path mux */ 2002 CY_SYSCLK_CLKPATH_IN_LPECO = 5U, /**< Select the LPECO as the output of the path mux */ 2003 CY_SYSCLK_CLKPATH_IN_IHO = 6U, /**< Select the IHO as the output of the path mux */ 2004 CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. 2005 * Make sure the DSI clock sources are available on used device. 2006 */ 2007 CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, /**< Select the ILO (16) as the output of the DSI mux and path mux */ 2008 CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */ 2009 CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux. 2010 * Make sure the ALTLF clock sources in available on used device. 2011 */ 2012 CY_SYSCLK_CLKPATH_IN_PILO = 0x113U, /**< Select the PILO (19) as the output of the DSI mux and path mux. 2013 * Make sure the PILO clock sources in available on used device. 2014 */ 2015 CY_SYSCLK_CLKPATH_IN_ILO1 = 0x114U, /**< Select the ILO1 (20) as the output of the DSI mux and path mux */ 2016 #else 2017 CY_SYSCLK_CLKPATH_IN_IMO = 0U, /**< Select the IMO as the output of the path mux */ 2018 CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */ 2019 CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */ 2020 CY_SYSCLK_CLKPATH_IN_ALTHF = 3U, /**< Select the ALTHF as the output of the path mux */ 2021 CY_SYSCLK_CLKPATH_IN_DSIMUX = 4U, /**< Select the DSI MUX output as the output of the path mux */ 2022 CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. 2023 * Make sure the DSI clock sources are available on used device. 2024 */ 2025 CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, /**< Select the ILO (16) as the output of the DSI mux and path mux */ 2026 CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */ 2027 CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux. 2028 * Make sure the ALTLF clock sources in available on used device. 2029 */ 2030 CY_SYSCLK_CLKPATH_IN_PILO = 0x113U, /**< Select the PILO (19) as the output of the DSI mux and path mux. 2031 * Make sure the PILO clock sources in available on used device. 2032 */ 2033 #endif 2034 } cy_en_clkpath_in_sources_t; 2035 2036 2037 #if (defined(CY_DEVICE_SECURE)) 2038 /** 2039 * \note 2040 * This structure is available for CAT1A devices. 2041 **/ 2042 /** PRA structure for Cy_SysClk_ClkPathSetSource function parameters */ 2043 typedef struct 2044 { 2045 uint32_t clk_path; /**< clkpath */ 2046 cy_en_clkpath_in_sources_t source; /**< Source */ 2047 } cy_stc_pra_clkpathsetsource_t; 2048 #endif /* (defined(CY_DEVICE_SECURE)) */ 2049 2050 /** \} group_sysclk_path_src_enums */ 2051 2052 /** 2053 * \addtogroup group_sysclk_path_src_funcs 2054 * \{ 2055 */ 2056 /******************************************************************************* 2057 * Function Name: Cy_SysClk_ClkPathSetSource 2058 ****************************************************************************//** 2059 * 2060 * Configures the source for the specified clock path. 2061 * 2062 * \param clkPath Selects which clock path to configure; 0 is the first clock 2063 * path, which is the FLL. 2064 * 2065 * \param source \ref cy_en_clkpath_in_sources_t 2066 * 2067 * \return \ref cy_en_sysclk_status_t 2068 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2069 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2070 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2071 * uses the PRA driver to change the protected registers. Refer to 2072 * \ref cy_en_pra_status_t for more details. 2073 * 2074 * \note 2075 * If calling this function changes an FLL or PLL input frequency, disable the FLL 2076 * or PLL before calling this function. After calling this function, call the FLL 2077 * or PLL configure function, for example \ref Cy_SysClk_FllConfigure(). 2078 * 2079 * \note 2080 * Call \ref SystemCoreClockUpdate after this function calling 2081 * if it affects the CLK_HF0 frequency. 2082 * 2083 * \note 2084 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2085 * it affects the CLK_HF0 frequency and the frequency is increasing. 2086 * 2087 * \note 2088 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2089 * it affects the CLK_HF0 frequency and the frequency is decreasing. 2090 * 2091 * \funcusage 2092 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource 2093 * 2094 * \note 2095 * Take into account the possible platform specific clkHf (and further 2096 * clocking chain links) frequency limitations while using this API. 2097 * 2098 * \note It takes four cycles of the originally selected clock to switch away 2099 * from it. Do not disable the original clock during this time. 2100 * 2101 *******************************************************************************/ 2102 cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source); 2103 2104 2105 /******************************************************************************* 2106 * Function Name: Cy_SysClk_ClkPathGetSource 2107 ****************************************************************************//** 2108 * 2109 * Reports which source is selected for the path mux. 2110 * 2111 * \param clkPath Selects which clock path to report; 0 is the first clock path, 2112 * which is the FLL. 2113 * 2114 * \return \ref cy_en_clkpath_in_sources_t 2115 * 2116 * \funcusage 2117 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathGetSource 2118 * 2119 *******************************************************************************/ 2120 cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath); 2121 2122 2123 /******************************************************************************* 2124 * Function Name: Cy_SysClk_ClkPathMuxGetFrequency 2125 ****************************************************************************//** 2126 * 2127 * Returns the output frequency of the clock path mux. 2128 * 2129 * \return The output frequency of the path mux. 2130 * 2131 * \note If the return value equals zero, that means either: 2132 * - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or 2133 * - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). 2134 * 2135 * \funcusage 2136 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource 2137 * 2138 *******************************************************************************/ 2139 uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath); 2140 2141 2142 /******************************************************************************* 2143 * Function Name: Cy_SysClk_ClkPathGetFrequency 2144 ****************************************************************************//** 2145 * 2146 * Returns the output frequency of the clock path mux. 2147 * 2148 * \return The output frequency of the path mux. 2149 * 2150 * \note If the return value equals zero, that means either: 2151 * - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or 2152 * - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). 2153 * 2154 * \funcusage 2155 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable 2156 * 2157 *******************************************************************************/ 2158 uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath); 2159 /** \} group_sysclk_path_src_funcs */ 2160 2161 2162 /* ========================================================================== */ 2163 /* =========================== FLL SECTION ============================ */ 2164 /* ========================================================================== */ 2165 /** 2166 * \addtogroup group_sysclk_fll_enums 2167 * \{ 2168 */ 2169 /** FLL and PLL output mode. 2170 * See registers CLK_FLL_CONFIG3 and CLK_PLL_CONFIG0, bits BYPASS_SEL. 2171 */ 2172 typedef enum 2173 { 2174 CY_SYSCLK_FLLPLL_OUTPUT_AUTO = 0U, /**< Output FLL/PLL input source when not locked, and FLL/PLL output when locked */ 2175 CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 = 1U, /**< Same as AUTO */ 2176 CY_SYSCLK_FLLPLL_OUTPUT_INPUT = 2U, /**< Output FLL/PLL input source regardless of lock status */ 2177 CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT = 3U /**< Output FLL/PLL output regardless of lock status. This can be dangerous if used to clock clkHf, because FLL/PLL output may be unstable */ 2178 } cy_en_fll_pll_output_mode_t; 2179 2180 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 2181 /** FLL current-controlled oscillator (CCO) frequency ranges. 2182 * See register CLK_FLL_CONFIG4, bits CCO_RANGE. 2183 */ 2184 typedef enum 2185 { 2186 CY_SYSCLK_FLL_CCO_RANGE0, /**< Target frequency is in range 48 - 64 MHz */ 2187 CY_SYSCLK_FLL_CCO_RANGE1, /**< Target frequency is in range 64 - 85 MHz */ 2188 CY_SYSCLK_FLL_CCO_RANGE2, /**< Target frequency is in range 85 - 113 MHz */ 2189 CY_SYSCLK_FLL_CCO_RANGE3, /**< Target frequency is in range 113 - 150 MHz */ 2190 CY_SYSCLK_FLL_CCO_RANGE4 /**< Target frequency is in range 150 - 200 MHz */ 2191 } cy_en_fll_cco_ranges_t; 2192 #endif /* defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) */ 2193 /** \} group_sysclk_fll_enums */ 2194 2195 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 2196 2197 /** 2198 * \addtogroup group_sysclk_fll_structs 2199 * \{ 2200 */ 2201 /** Structure containing information for manual configuration of FLL. 2202 */ 2203 typedef struct 2204 { 2205 uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */ 2206 uint16_t refDiv; /**< CLK_FLL_CONFIG2 register, FLL_REF_DIV bits */ 2207 cy_en_fll_cco_ranges_t ccoRange; /**< CLK_FLL_CONFIG4 register, CCO_RANGE bits */ 2208 bool enableOutputDiv; /**< CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit */ 2209 uint16_t lockTolerance; /**< CLK_FLL_CONFIG2 register, LOCK_TOL bits */ 2210 uint8_t igain; /**< CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits */ 2211 uint8_t pgain; /**< CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits */ 2212 uint16_t settlingCount; /**< CLK_FLL_CONFIG3 register, SETTLING_COUNT bits */ 2213 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_FLL_CONFIG3 register, BYPASS_SEL bits */ 2214 uint16_t cco_Freq; /**< CLK_FLL_CONFIG4 register, CCO_FREQ bits */ 2215 } cy_stc_fll_manual_config_t; 2216 2217 /** \} group_sysclk_fll_structs */ 2218 2219 /** 2220 * \addtogroup group_sysclk_fll_funcs 2221 * \{ 2222 *//******************************************************************************* 2223 * Function Name: Cy_SysClk_FllConfigure 2224 ****************************************************************************//** 2225 * 2226 * Configures the FLL, for best accuracy optimization. 2227 * 2228 * \param inputFreq frequency of input source, in Hz 2229 * 2230 * \param outputFreq Desired FLL output frequency, in Hz. Allowable range is 2231 * 24 MHz to 100 MHz. In all cases, FLL_OUTPUT_DIV must be set; the output divide 2232 * by 2 option is required. 2233 * 2234 * \param outputMode \ref cy_en_fll_pll_output_mode_t 2235 * If output mode is bypass, then the output frequency equals the input source 2236 * frequency regardless of the frequency parameter values. 2237 * 2238 * \return Error / status code: \n 2239 * CY_SYSCLK_SUCCESS - FLL successfully configured \n 2240 * CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled \n 2241 * CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range \n 2242 * CY_SYSCLK_UNSUPPORTED_STATE - FLL is not present 2243 * 2244 * \note 2245 * Call this function after changing the FLL input frequency, for example if 2246 * \ref Cy_SysClk_ClkPathSetSource() is called. 2247 * 2248 * \note 2249 * Do not call this function when the FLL is enabled. If it is called, then this function 2250 * returns with an CY_SYSCLK_INVALID_STATE return value and no register updates. 2251 * 2252 * \note 2253 * Call \ref SystemCoreClockUpdate after this function calling 2254 * if it affects the CLK_HF0 frequency. 2255 * 2256 * \note 2257 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2258 * the FLL is the source of CLK_HF0 and the FLL frequency is increasing. 2259 * 2260 * \note 2261 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2262 * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. 2263 * 2264 * \note 2265 * On PSoC 64 devices the configuration on the PRA driver will be reflected 2266 * after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration 2267 * before calling \ref Cy_SysClk_FllEnable returns old configuration values. 2268 * 2269 * \funcusage 2270 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllConfigure 2271 * 2272 *******************************************************************************/ 2273 cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode); 2274 2275 2276 /******************************************************************************* 2277 * Function Name: Cy_SysClk_FllManualConfigure 2278 ****************************************************************************//** 2279 * 2280 * Manually configures the FLL based on user inputs. 2281 * 2282 * \param config \ref cy_stc_fll_manual_config_t 2283 * 2284 * \return Error / status code: \n 2285 * CY_SYSCLK_SUCCESS - FLL successfully configured \n 2286 * CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled 2287 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2288 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2289 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2290 * uses the PRA driver to change the protected registers. Refer to 2291 * \ref cy_en_pra_status_t for more details. 2292 * 2293 * \note 2294 * Call this function after changing the FLL input frequency, for example if 2295 * \ref Cy_SysClk_ClkPathSetSource() is called. 2296 * 2297 * \note 2298 * Do not call this function when the FLL is enabled. If it is called, then this function 2299 * returns immediately with an CY_SYSCLK_INVALID_STATE return value and no register updates. 2300 * 2301 * \note 2302 * Call \ref SystemCoreClockUpdate after this function calling 2303 * if it affects the CLK_HF0 frequency. 2304 * 2305 * \note 2306 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2307 * the FLL is the source of CLK_HF0 and the FLL frequency is increasing. 2308 * 2309 * \note 2310 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2311 * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. 2312 * 2313 * \note 2314 * On PSoC 64 devices the configuration on the PRA driver will be reflected 2315 * after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration 2316 * before calling \ref Cy_SysClk_FllEnable returns old configuration values. 2317 * 2318 * \funcusage 2319 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllManualConfigure 2320 * 2321 *******************************************************************************/ 2322 cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config); 2323 2324 2325 /******************************************************************************* 2326 * Function Name: Cy_SysClk_FllGetConfiguration 2327 ****************************************************************************//** 2328 * 2329 * Reports the FLL configuration settings. 2330 * 2331 * \param config \ref cy_stc_fll_manual_config_t 2332 * 2333 * \note 2334 * On PSoC 64 devices the configuration on the PRA driver will be reflected 2335 * after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration 2336 * before calling \ref Cy_SysClk_FllEnable returns old configuration values. 2337 * 2338 * \funcusage 2339 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllGetConfiguration 2340 * 2341 *******************************************************************************/ 2342 void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config); 2343 2344 2345 /******************************************************************************* 2346 * Function Name: Cy_SysClk_FllEnable 2347 ****************************************************************************//** 2348 * 2349 * Enables the FLL. The FLL should be configured before calling this function. 2350 * 2351 * \param timeoutus Amount of time in micro seconds to wait for FLL to lock. 2352 * If lock doesn't occur, the FLL is stopped. To avoid waiting for lock, set this to 0 2353 * and manually check for lock using \ref Cy_SysClk_FllLocked. 2354 * 2355 * \return Error / status code: \n 2356 * CY_SYSCLK_SUCCESS - FLL successfully enabled \n 2357 * CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock 2358 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2359 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2360 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2361 * uses the PRA driver to change the protected registers. Refer to 2362 * \ref cy_en_pra_status_t for more details. 2363 * 2364 * \note 2365 * While waiting for the FLL to lock, the FLL bypass mode is set to \ref CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 2366 * After the FLL is locked, the FLL bypass mdoe is then set to \ref CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT. 2367 * 2368 * \note 2369 * Call \ref SystemCoreClockUpdate after calling this function 2370 * if it affects the CLK_HF0 frequency. 2371 * 2372 * \note 2373 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2374 * the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 2375 * 2376 * \note 2377 * Take into account the possible platform specific clkHf (and further 2378 * clocking chain links) frequency limitations while using this API. 2379 * 2380 * \funcusage 2381 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable 2382 * 2383 *******************************************************************************/ 2384 cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus); 2385 2386 2387 /******************************************************************************* 2388 * Function Name: Cy_SysClk_FllIsEnabled 2389 ****************************************************************************//** 2390 * 2391 * Reports whether or not the FLL is enabled. 2392 * 2393 * \return 2394 * false = disabled \n 2395 * true = enabled 2396 * 2397 * \funcusage 2398 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable 2399 * 2400 *******************************************************************************/ 2401 bool Cy_SysClk_FllIsEnabled(void); 2402 2403 2404 /******************************************************************************* 2405 * Function Name: Cy_SysClk_FllLocked 2406 ****************************************************************************//** 2407 * 2408 * Reports whether the FLL is locked first time during FLL starting. 2409 * Intended to be used with \ref Cy_SysClk_FllEnable with zero timeout. 2410 * 2411 * \return 2412 * false = not locked \n 2413 * true = locked 2414 * 2415 * \note 2416 * The unlock occurrence may appear during FLL normal operation, so this function 2417 * is not recommended to check the FLL normal operation stability. 2418 * 2419 * \funcusage 2420 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllLocked 2421 * 2422 *******************************************************************************/ 2423 bool Cy_SysClk_FllLocked(void); 2424 2425 2426 /******************************************************************************* 2427 * Function Name: Cy_SysClk_FllDisable 2428 ****************************************************************************//** 2429 * 2430 * Disables the FLL and the CCO. 2431 * 2432 * \return \ref cy_en_sysclk_status_t 2433 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2434 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2435 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2436 * uses the PRA driver to change the protected registers. Refer to 2437 * \ref cy_en_pra_status_t for more details. 2438 * 2439 * \note 2440 * Call \ref SystemCoreClockUpdate after this function calling 2441 * if it affects the CLK_HF0 frequency. 2442 * 2443 * \note 2444 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2445 * the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 2446 * 2447 * \funcusage 2448 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable 2449 * 2450 *******************************************************************************/ 2451 cy_en_sysclk_status_t Cy_SysClk_FllDisable(void); 2452 2453 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) 2454 2455 /******************************************************************************* 2456 * Function Name: Cy_SysClk_FllOutputDividerEnable 2457 ****************************************************************************//** 2458 * 2459 * Enables/Disables the FLL output divider 2460 * 2461 * \param enable 2462 * 2463 *******************************************************************************/ 2464 void Cy_SysClk_FllOutputDividerEnable(bool enable); 2465 2466 #endif 2467 2468 /******************************************************************************* 2469 * Function Name: Cy_SysClk_FllGetFrequency 2470 ****************************************************************************//** 2471 * 2472 * Returns the output frequency of the FLL. 2473 * 2474 * \return The output frequency of FLL. 2475 * 2476 * \note If the return value equals zero, that means FLL is disabled. 2477 * 2478 * \funcusage 2479 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllGetFrequency 2480 * 2481 *******************************************************************************/ 2482 uint32_t Cy_SysClk_FllGetFrequency(void); 2483 2484 /** \} group_sysclk_fll_funcs */ 2485 #endif /* defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) */ 2486 2487 /* ========================================================================== */ 2488 /* =========================== PLL SECTION ============================ */ 2489 /* ========================================================================== */ 2490 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_NUM_TOTAL_PLL > 0UL)) 2491 /** 2492 * \addtogroup group_sysclk_pll_structs 2493 * \{ 2494 */ 2495 /** Structure containing information for configuration of a PLL. 2496 */ 2497 typedef struct 2498 { 2499 uint32_t inputFreq; /**< frequency of PLL source, in Hz */ 2500 uint32_t outputFreq; /**< frequency of PLL output, in Hz */ 2501 bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */ 2502 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */ 2503 } cy_stc_pll_config_t; 2504 2505 #if defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_NUM_TOTAL_PLL > 0UL)) || defined(CY_DOXYGEN) 2506 /** Structure containing information for configuration of a DPLL-LP. 2507 */ 2508 /** 2509 * \note 2510 * This structure is available only for CAT1D devices. 2511 **/ 2512 typedef struct 2513 { 2514 uint8_t feedbackDiv; /**< CONFIG register, FEEDBACK_DIV (P) bits */ 2515 uint8_t referenceDiv; /**< CONFIG register, REFERENCE_DIV (Q) bits */ 2516 uint8_t outputDiv; /**< CONFIG register, OUTPUT_DIV bits */ 2517 bool pllDcoMode; /**< CONFIG register, PLL_DCO_MODE bit */ 2518 cy_en_fll_pll_output_mode_t outputMode; /**< CONFIG register, BYPASS_SEL bits */ 2519 uint32_t fracDiv; /**< CONFIG2 register, FRAC_DIV bits, only for CAT1B(B2),CAT1D devices */ 2520 bool fracDitherEn; /**< CONFIG2 register, FRAC_DITHER_EN bit, only for CAT1B(B2),CAT1D devices */ 2521 bool fracEn; /**< CONFIG2 register, FRAC_EN bit, only for CAT1B(B2),CAT1D devices */ 2522 uint32_t sscgDepth; /**< CONFIG3 register, SSCG_DEPTH bits, only for CAT1B(B2),CAT1D devices */ 2523 uint8_t sscgRate; /**< CONFIG3 register, SSCG_RATE bits, only for CAT1B(B2),CAT1D devices */ 2524 bool sscgDitherEn; /**< CONFIG3 register, SSCG_DITHER_EN bit, only for CAT1B(B2),CAT1D devices */ 2525 bool sscgMode; /**< CONFIG3 register, SSCG_MODE bit, only for CAT1B(B2),CAT1D devices */ 2526 bool sscgEn; /**< CONFIG3 register, SSCG_EN bit, only for CAT1B(B2),CAT1D devices */ 2527 #if defined (CY_IP_MXS22SRSS) 2528 uint32_t dcoCode; /**< CONFIG4 register, DCO_CODE bits, only for CAT1D devices */ 2529 bool disableBias; /**< CONFIG4 register, PLL_CS_PB2_DIS bit, only for CAT1D devices */ 2530 bool enableDcoSd; /**< CONFIG4 register, DCO_SD_EN bit, only for CAT1D devices */ 2531 uint32_t kiInt; /**< CONFIG5 register, Gain of P/I loop filter integrator path for INT operation only for CAT1D devices */ 2532 uint32_t kiFrac; /**< CONFIG5 register, Gain of P/I loop filter proportional path for FRACT operation only for CAT1D devices */ 2533 uint32_t kiSscg; /**< CONFIG5 register, Gain of P/I loop filter proportional path for SSCG operation only for CAT1D devices */ 2534 uint32_t kpInt; /**< CONFIG5 register, Gain of P/I loop filter integrator path for INT operation. only for CAT1D devices */ 2535 uint32_t kpFrac; /**< CONFIG5 register, Gain of P/I loop filter integrator path for FRACT operation. only for CAT1D devices */ 2536 uint32_t kpSscg; /**< CONFIG5 register, Gain of P/I loop filter integrator path for SSCG operation. only for CAT1D devices */ 2537 #else 2538 uint32_t dcoCode; /**< CONFIG4 register, DCO_CODE bits, only for CAT1B(B2), devices */ 2539 uint32_t accMode; /**< CONFIG4 register, ACC_MODE bits, only for CAT1B(B2), devices */ 2540 uint32_t tdcMode; /**< CONFIG4 register, TDC_MODE bits, only for CAT1B(B2), devices */ 2541 uint32_t pllTg; /**< CONFIG4 register, PLL_TG bits, only for CAT1B(B2), devices */ 2542 bool accCntLock; /**< CONFIG4 register, ACC_CNT_LOCK bits, only for CAT1B(B2), devices */ 2543 uint32_t kiInt; /**< CONFIG5 register, KI_INT bits, only for CAT1B(B2), devices */ 2544 uint32_t kpInt; /**< CONFIG5 register, KP_INT bits, only for CAT1B(B2), devices */ 2545 uint32_t kiAccInt; /**< CONFIG5 register, KI_ACC_INT bits, only for CAT1B(B2), devices */ 2546 uint32_t kpAccInt; /**< CONFIG5 register, KP_ACC_INT bits, only for CAT1B(B2), devices */ 2547 uint32_t kiFrac; /**< CONFIG6 register, KI_FRACT bits, only for CAT1B(B2), devices */ 2548 uint32_t kpFrac; /**< CONFIG6 register, KP_FRACT bits, only for CAT1B(B2), devices */ 2549 uint32_t kiAccFrac; /**< CONFIG6 register, KI_ACC_FRACT bits, only for CAT1B(B2), devices */ 2550 uint32_t kpAccFrac; /**< CONFIG7 register, KP_ACC_FRACT bits, only for CAT1B(B2), devices */ 2551 uint32_t kiSscg; /**< CONFIG7 register, KI_SSCG bits, only for CAT1B(B2), devices */ 2552 uint32_t kpSscg; /**< CONFIG7 register, KP_SSCG bits, only for CAT1B(B2), devices */ 2553 uint32_t kiAccSscg; /**< CONFIG7 register, KI_ACC_SSCG bits, only for CAT1B(B2), devices */ 2554 uint32_t kpAccSscg; /**< CONFIG7 register, KP_ACC_SSCG bits, only for CAT1B(B2), devices */ 2555 #endif 2556 } cy_stc_dpll_lp_config_t; 2557 2558 #if defined (CY_IP_MXS22SRSS) || defined(CY_DOXYGEN) 2559 /** DPLL-HP wait mode selection enum. 2560 * See CONFIG2 register, bits MODE_SEL. 2561 */ 2562 typedef enum 2563 { 2564 CY_SYSCLK_DPLL_HP_CLK4MHZ_1US_CNT_VAL = 0U, /**< clk_dig frequency = 4MHz*/ 2565 CY_SYSCLK_DPLL_HP_CLK10MHZ_1US_CNT_VAL = 1U, /**< clk_dig frequency = 10MHz*/ 2566 CY_SYSCLK_DPLL_HP_CLK15MHZ_1US_CNT_VAL = 2U, /**< clk_dig frequency = 15MHz*/ 2567 CY_SYSCLK_DPLL_HP_CLK20MHZ_1US_CNT_VAL = 3U, /**< clk_dig frequency = 20MHz*/ 2568 CY_SYSCLK_DPLL_HP_CLK30MHZ_1US_CNT_VAL = 4U, /**< clk_dig frequency = 30MHz*/ 2569 CY_SYSCLK_DPLL_HP_CLK40MHZ_1US_CNT_VAL = 5U, /**< clk_dig frequency = 40MHz*/ 2570 CY_SYSCLK_DPLL_HP_CLK45MHZ_1US_CNT_VAL = 6U, /**< clk_dig frequency = 45MHz*/ 2571 CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL = 7U /**< clk_dig frequency = 50MHz*/ 2572 } cy_en_wait_mode_select_t; 2573 2574 2575 /** Structure containing information for configuration of a DPLL-HP. 2576 */ 2577 /** 2578 * \note 2579 * This structure is available only for CAT1D devices. 2580 **/ 2581 typedef struct 2582 { 2583 uint8_t nDiv; /**< CONFIG register, NDIV bits, Ratio between DCO frequency and reference frequency */ 2584 uint8_t pDiv; /**< CONFIG register, PDIV bits, Pre-Divider for scaling the reference frequency */ 2585 uint8_t kDiv; /**< CONFIG register, KDIV bits, Post-Divider */ 2586 cy_en_fll_pll_output_mode_t outputMode; /**< CONFIG register, BYPASS_SEL bits */ 2587 bool pllEn; /**< CONFIG register, ENABLE bits, Master Enable for PLL */ 2588 2589 uint32_t nDivFract; /**< CONFIG2 register, NDIV_FRACT bits, N-divider division factor */ 2590 cy_en_wait_mode_select_t freqModeSel; /**< CONFIG2 register, MODE_SEL bits, Selects the waiting time for Power Initialization sequence */ 2591 uint8_t ivrTrim ; /**< CONFIG2 register, IVR_TRIM bits, Trim value for the Regulated Voltage */ 2592 2593 bool clkrSel; /**< CONFIG3 register, CLKR_SEL bit, Select re-timed reference clock */ 2594 bool fdsmSel; /**< CONFIG3 register, FDSM_SEL bit, DSM clock division select, true - div_by_2, false - div_by_4 */ 2595 2596 uint8_t alphaCoarse; /**< CONFIG4 register, LF_LC_ALPHA bits, Alpha value of the coarse filter */ 2597 uint8_t betaCoarse; /**< CONFIG4 register, LF_LC_BETA bits, Beta value of the coarse filter */ 2598 uint8_t flockThresh; /**< CONFIG4 register, FLOCK_EN_THRESH bits, PQDIFF threshold under which FINE Filtering gets enabled */ 2599 uint8_t flockWait; /**< CONFIG4 register, FLOCK_WAITPER bits, Period over which flock_en_thresh must be met in order for FINE Filtering enabling */ 2600 uint8_t flockLkThres; /**< CONFIG4 register, FLOCK_LK_THRESH bits, PQDIFF threshold under which DLL asserts Freq LOCK */ 2601 uint8_t flockLkWait; /**< CONFIG4 register, FLOCK_LK_WAITPER bits, Period over which flock_en_thresh must be met in order for Freq Locking */ 2602 uint8_t flockObs; /**< CONFIG4 register, FLOCK_OBSWIN bits, Period over which PQDIFF is computed/observed */ 2603 2604 uint8_t alphaExt; /**< CONFIG5 register, LF_ALPHA bits, External Alpha value */ 2605 uint8_t betaExt; /**< CONFIG5 register, LF_BETA bits, External Beta value */ 2606 bool lfEn; /**< CONFIG5 register, LF_SET_PARAMS bit, enable for external loop filter control (alpha and beta values) */ 2607 uint16_t dtCal; /**< CONFIG5 register, DUTY CAL circuit status */ 2608 2609 uint16_t tmodFreq; /**< TRIGMOD register, TRIMOD_FREQ bits, Triangular-Frequency Modulation: modulation frequency */ 2610 uint16_t tmodGrad; /**< TRIGMOD register, TRIMOD_GRD bits, Triangular-Frequency Modulation: modulation gradient */ 2611 2612 uint32_t tmodRate; /**< TRIGMOD2 register, TRIMOD_RATE bits, Triangular-Frequency Modulation Rate */ 2613 bool tmodEn; /**< TRIGMOD2 register, TRIMOD_EN bit, Triangular-Frequency Modulation enable */ 2614 bool tmodStop; /**< TRIGMOD2 register, TRIMOD_STP bit, Triangular-Frequency Modulation stop */ 2615 2616 bool pllLocked; /**< STATUS register, LOCKED bits, PLL Lock Indicator */ 2617 bool pllUnlock; /**< STATUS register, UNLOCK_OCCURRED bit, Sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware*/ 2618 bool lockDetReset; /**< STATUS register, LOCKDET_RES bit, Restart lock detector */ 2619 bool lockDetRstAck; /**< STATUS register, LOCKDET_RES_ACK bit, Acknowledgement for lock detection restart */ 2620 2621 uint8_t dcCalDelta; /**< DUTYCAL_CTRL register, DELTA bits, Margins for the duty cycle calibration error */ 2622 bool dcRatioStatus; /**< DUTYCAL_CTRL register, RATIO_OK bit, Status of the duty calibration ratio*/ 2623 bool dcStatus; /**< DUTYCAL_CTRL register, OK bit, Status of the duty calibration*/ 2624 uint16_t dcTarget; /**< DUTYCAL_CTRL register, TARGET bits, Duty cycle target */ 2625 bool dcEnRingOsc; /**< DUTYCAL_CTRL register, CTRL_RG_EN bit, Enables ring oscillator for duty cycle digitization */ 2626 bool dcEn; /**< DUTYCAL_CTRL register, EN bit, Enables duty cycle calibration */ 2627 }cy_stc_dpll_hp_config_t; 2628 #endif 2629 #endif 2630 2631 /** Structure containing information for manual configuration of a PLL. 2632 */ 2633 typedef struct 2634 { 2635 #if defined (CY_IP_MXS40SRSS) ||defined(CY_DOXYGEN) 2636 uint8_t feedbackDiv; /**< CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits */ 2637 uint8_t referenceDiv; /**< CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits */ 2638 uint8_t outputDiv; /**< CLK_PLL_CONFIG register, OUTPUT_DIV bits */ 2639 bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */ 2640 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */ 2641 #endif 2642 2643 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) || defined(CY_DOXYGEN) 2644 uint32_t fracDiv; /**< CLK_PLL_CONFIG2 register, FRAC_DIV bits, only for CAT1C devices */ 2645 bool fracDitherEn; /**< CLK_PLL_CONFIG2 register, FRAC_DITHER_EN bit, only for CAT1C devices */ 2646 bool fracEn; /**< CLK_PLL_CONFIG2 register, FRAC_EN bit, only for CAT1C devices */ 2647 uint32_t sscgDepth; /**< CLK_PLL_CONFIG3 register, SSCG_DEPTH bits, only for CAT1C devices */ 2648 uint8_t sscgRate; /**< CLK_PLL_CONFIG3 register, SSCG_RATE bits, only for CAT1C devices */ 2649 bool sscgEn; /**< CLK_PLL_CONFIG3 register, SSCG_EN bit, only for CAT1C devices */ 2650 #endif 2651 #if defined (CY_IP_MXS22SRSS) || defined(CY_DOXYGEN) 2652 cy_stc_dpll_lp_config_t *lpPllCfg; /**< DPLL-LP configuration */ 2653 cy_stc_dpll_hp_config_t *hpPllCfg; /**< DPLL-HP configuration */ 2654 #endif 2655 #if (defined (CY_IP_MXS40SSRSS) && (SRSS_NUM_TOTAL_PLL > 0UL)) || defined(CY_DOXYGEN) 2656 cy_stc_dpll_lp_config_t *lpPllCfg; /**< DPLL-LP configuration */ 2657 #endif 2658 } cy_stc_pll_manual_config_t; 2659 /** \} group_sysclk_pll_structs */ 2660 2661 #if (defined(CY_DEVICE_SECURE)) 2662 2663 /** PRA structure for Cy_SysClk_PllManualConfigure function parameters */ 2664 typedef struct 2665 { 2666 uint32_t clkPath; /**< clkPath */ 2667 cy_stc_pll_manual_config_t *praConfig; /**< config */ 2668 } cy_stc_pra_clk_pll_manconfigure_t; 2669 #endif /* (defined(CY_DEVICE_SECURE)) */ 2670 2671 /** 2672 * \addtogroup group_sysclk_pll_funcs 2673 * \{ 2674 *//******************************************************************************* 2675 * Function Name: Cy_SysClk_PllConfigure 2676 ****************************************************************************//** 2677 * 2678 * Configures a given PLL. 2679 * The configuration formula used is: 2680 * Fout = pll_clk * (P / Q / div_out), where: 2681 * Fout is the desired output frequency 2682 * pll_clk is the frequency of the input source 2683 * P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. 2684 * Q is the reference divider. Its value is in bitfield REFERENCE_DIV. 2685 * div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. 2686 * 2687 * \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. 2688 * 2689 * \param config \ref cy_stc_pll_config_t 2690 * 2691 * \return Error / status code: \n 2692 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 2693 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2694 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 2695 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2696 * 2697 * \note 2698 * Call this function after changing the PLL input frequency, for example if 2699 * \ref Cy_SysClk_ClkPathSetSource() is called. 2700 * 2701 * \note 2702 * Do not call this function when the PLL is enabled. If it is called, then this function 2703 * returns immediately with an error return value and no register updates. 2704 * 2705 * \note 2706 * Call \ref SystemCoreClockUpdate after this function calling 2707 * if it affects the CLK_HF0 frequency. 2708 * 2709 * \note 2710 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2711 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 2712 * 2713 * \note 2714 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2715 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 2716 * 2717 * \note 2718 * On PSoC 64 devices the configuration on the PRA driver will be reflected 2719 * after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration 2720 * before calling \ref Cy_SysClk_PllEnable returns old configuration values. 2721 * 2722 * \note 2723 * This API is available for CAT1A, CAT1C and CAT1D devices. 2724 * 2725 * \funcusage 2726 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllConfigure 2727 * 2728 *******************************************************************************/ 2729 cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config); 2730 2731 2732 /******************************************************************************* 2733 * Function Name: Cy_SysClk_PllManualConfigure 2734 ****************************************************************************//** 2735 * 2736 * Manually configures a PLL based on user inputs. 2737 * 2738 * \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. 2739 * 2740 * \param config \ref cy_stc_pll_manual_config_t 2741 * 2742 * \return Error / status code: \n 2743 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 2744 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2745 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2746 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2747 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2748 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2749 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2750 * uses the PRA driver to change the protected registers. Refer to 2751 * \ref cy_en_pra_status_t for more details. 2752 * 2753 * \note 2754 * Call this function after changing the PLL input frequency; for example if 2755 * \ref Cy_SysClk_ClkPathSetSource() is called. 2756 * 2757 * \note 2758 * Do not call this function when the PLL is enabled. If it is called, then this function 2759 * returns immediately with an error return value and no register updates. 2760 * 2761 * \note 2762 * Call \ref SystemCoreClockUpdate after this function calling 2763 * if it affects the CLK_HF0 frequency. 2764 * 2765 * \note 2766 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2767 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 2768 * 2769 * \note 2770 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2771 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 2772 * 2773 * \note 2774 * On PSoC 64 devices the configuration on the PRA driver will be reflected 2775 * after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration 2776 * before calling \ref Cy_SysClk_PllEnable returns old configuration values. 2777 * 2778 * \note 2779 * This API is available for CAT1A, CAT1C and CAT1D devices. 2780 * 2781 * \funcusage 2782 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllManualConfigure 2783 * 2784 *******************************************************************************/ 2785 cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config); 2786 2787 2788 /******************************************************************************* 2789 * Function Name: Cy_SysClk_PllGetConfiguration 2790 ****************************************************************************//** 2791 * 2792 * Reports configuration settings for a PLL. 2793 * 2794 * \param clkPath Selects which PLL to report. 1 is the first PLL; 0 is invalid. 2795 * 2796 * \param config \ref cy_stc_pll_manual_config_t 2797 * 2798 * \return Error / status code: \n 2799 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 2800 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2801 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2802 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2803 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2804 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2805 * uses the PRA driver to change the protected registers. Refer to 2806 * \ref cy_en_pra_status_t for more details. 2807 * 2808 * \note 2809 * On PSoC 64 devices the configuration on the PRA driver will be reflected 2810 * after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration 2811 * before calling \ref Cy_SysClk_PllEnable returns old configuration values. 2812 * 2813 * \note 2814 * This API is available for CAT1A, CAT1C and CAT1D devices. 2815 * 2816 * \funcusage 2817 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllGetConfiguration 2818 * 2819 *******************************************************************************/ 2820 cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config); 2821 2822 2823 /******************************************************************************* 2824 * Function Name: Cy_SysClk_PllEnable 2825 ****************************************************************************//** 2826 * 2827 * Enables the PLL. The PLL should be configured before calling this function. 2828 * 2829 * \param clkPath Selects which PLL to enable. 1 is the first PLL; 0 is invalid. 2830 * 2831 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 2832 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 2833 * and manually check for lock using \ref Cy_SysClk_PllLocked. 2834 * 2835 * \return Error / status code: \n 2836 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 2837 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 2838 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2839 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2840 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2841 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2842 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2843 * uses the PRA driver to change the protected registers. Refer to 2844 * \ref cy_en_pra_status_t for more details. 2845 * 2846 * \note 2847 * Call \ref SystemCoreClockUpdate after this function calling 2848 * if it affects the CLK_HF0 frequency. 2849 * 2850 * \note 2851 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2852 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 2853 * 2854 * \note 2855 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2856 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 2857 * 2858 * \note 2859 * This API is available for CAT1A, CAT1C and CAT1D devices. 2860 * 2861 * \note 2862 * Take into account the possible platform specific clkHf (and further 2863 * clocking chain links) frequency limitations while using this API. 2864 * 2865 * \funcusage 2866 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllEnable 2867 * 2868 *******************************************************************************/ 2869 cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus); 2870 2871 2872 /******************************************************************************* 2873 * Function Name: Cy_SysClk_PllIsEnabled 2874 ****************************************************************************//** 2875 * 2876 * Reports whether or not the selected PLL is enabled. 2877 * 2878 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. 2879 * 2880 * \return 2881 * false = disabled \n 2882 * true = enabled 2883 * 2884 * \note 2885 * This API is available for CAT1A, CAT1C and CAT1D devices. 2886 * 2887 * \funcusage 2888 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable 2889 * 2890 *******************************************************************************/ 2891 bool Cy_SysClk_PllIsEnabled(uint32_t clkPath); 2892 2893 2894 /******************************************************************************* 2895 * Function Name: Cy_SysClk_PllLocked 2896 ****************************************************************************//** 2897 * 2898 * Reports whether or not the selected PLL is locked. 2899 * 2900 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. 2901 * 2902 * \return 2903 * false = not locked \n 2904 * true = locked 2905 * 2906 * \note 2907 * This API is available for CAT1A, CAT1C and CAT1D devices. 2908 * 2909 * \funcusage 2910 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLocked 2911 * 2912 *******************************************************************************/ 2913 bool Cy_SysClk_PllLocked(uint32_t clkPath); 2914 2915 2916 /******************************************************************************* 2917 * Function Name: Cy_SysClk_PllLostLock 2918 ****************************************************************************//** 2919 * 2920 * Reports whether or not the selected PLL lost its lock since the last time this 2921 * function was called. Clears the lost lock indicator. 2922 * 2923 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. 2924 * 2925 * \return 2926 * false = did not lose lock \n 2927 * true = lost lock 2928 * 2929 * \note 2930 * This API is available for CAT1A, CAT1C and CAT1D devices. 2931 * 2932 * \funcusage 2933 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLostLock 2934 * 2935 *******************************************************************************/ 2936 bool Cy_SysClk_PllLostLock(uint32_t clkPath); 2937 2938 2939 /******************************************************************************* 2940 * Function Name: Cy_SysClk_PllDisable 2941 ****************************************************************************//** 2942 * 2943 * Disables the selected PLL. 2944 * 2945 * \param clkPath Selects which PLL to disable. 1 is the first PLL; 0 is invalid. 2946 * 2947 * \return Error / status code: \n 2948 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 2949 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2950 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2951 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2952 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2953 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2954 * uses the PRA driver to change the protected registers. Refer to 2955 * \ref cy_en_pra_status_t for more details. 2956 * 2957 * \note 2958 * Call \ref SystemCoreClockUpdate after this function calling 2959 * if it affects the CLK_HF0 frequency. 2960 * 2961 * \note 2962 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2963 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 2964 * 2965 * \note 2966 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2967 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 2968 * 2969 * \sideeffect 2970 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 2971 * If AUTO mode should be used, call \ref Cy_SysClk_PllConfigure or 2972 * \ref Cy_SysClk_PllManualConfigure before calling \ref Cy_SysClk_PllEnable. 2973 * 2974 * \note 2975 * This API is available for CAT1A, CAT1C and CAT1D devices. 2976 * 2977 * \funcusage 2978 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable 2979 * 2980 *******************************************************************************/ 2981 cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath); 2982 2983 /******************************************************************************* 2984 * Function Name: Cy_SysClk_PllGetFrequency 2985 ****************************************************************************//** 2986 * 2987 * Returns the output frequency of the PLL. 2988 * 2989 * \param clkPath Selects the path on which the PLL frequency has to be obtained. 2990 * 2991 * \return The output frequency of the path PLL. 2992 * 2993 * \note If the return value equals zero, that means PLL is disabled. 2994 * 2995 * \note 2996 * This API is available for CAT1A, CAT1C and CAT1D devices. 2997 * 2998 * \funcusage 2999 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllGetFrequency 3000 * 3001 *******************************************************************************/ 3002 uint32_t Cy_SysClk_PllGetFrequency(uint32_t clkPath); 3003 3004 3005 #if defined(CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_NUM_TOTAL_PLL > 0UL)) || defined(CY_DOXYGEN) 3006 3007 /******************************************************************************* 3008 * Function Name: Cy_SysClk_DpllLpConfigure 3009 ****************************************************************************//** 3010 * 3011 * Configures DPLL-LP. 3012 * 3013 * The configuration formula used is: 3014 * Fout = pll_clk * (P / Q / div_out), where: 3015 * Fout is the desired output frequency 3016 * pll_clk is the frequency of the input source 3017 * P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. 3018 * Q is the reference divider. Its value is in bitfield REFERENCE_DIV. 3019 * div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. 3020 * 3021 * \param pllNum Selects which DPLL-LP to configure 3022 * 3023 * \param config \ref cy_stc_pll_config_t 3024 * 3025 * \return Error / status code: \n 3026 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3027 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3028 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 3029 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3030 * 3031 * \note 3032 * Call this function after changing the PLL input frequency, for example if 3033 * \ref Cy_SysClk_ClkPathSetSource() is called. 3034 * 3035 * \note 3036 * Do not call this function when the PLL is enabled. If it is called, then this function 3037 * returns immediately with an error return value and no register updates. 3038 * 3039 * \note 3040 * Call \ref SystemCoreClockUpdate after this function calling 3041 * if it affects the CLK_HF0 frequency. 3042 * 3043 * \note 3044 * This API is available only for CAT1D devices. 3045 * 3046 *******************************************************************************/ 3047 cy_en_sysclk_status_t Cy_SysClk_DpllLpConfigure(uint32_t pllNum, const cy_stc_pll_config_t *config); 3048 3049 3050 /******************************************************************************* 3051 * Function Name: Cy_SysClk_DpllLpManualConfigure 3052 ****************************************************************************//** 3053 * 3054 * Manually configures a DPLL-LP based on user inputs. 3055 * 3056 * \param pllNum Selects which DPLL-LP to configure. 3057 * 3058 * \param config \ref cy_stc_pll_manual_config_t 3059 * 3060 * \return Error / status code: \n 3061 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3062 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3063 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3064 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3065 * 3066 * \note 3067 * Call this function after changing the PLL input frequency; for example if 3068 * \ref Cy_SysClk_ClkPathSetSource() is called. 3069 * 3070 * \note 3071 * Do not call this function when the PLL is enabled. If it is called, then this function 3072 * returns immediately with an error return value and no register updates. 3073 * 3074 * \note 3075 * Call \ref SystemCoreClockUpdate after this function calling 3076 * if it affects the CLK_HF0 frequency. 3077 * 3078 * \note 3079 * This API is available only for CAT1D devices. 3080 * 3081 *******************************************************************************/ 3082 cy_en_sysclk_status_t Cy_SysClk_DpllLpManualConfigure(uint32_t pllNum, const cy_stc_pll_manual_config_t *config); 3083 3084 3085 /******************************************************************************* 3086 * Function Name: Cy_SysClk_DpllLpGetConfiguration 3087 ****************************************************************************//** 3088 * 3089 * Reports configuration settings for DPLL-LP. 3090 * 3091 * \param pllNum Selects which DPLL-LP to report. 3092 * 3093 * \param config \ref cy_stc_pll_manual_config_t 3094 * 3095 * \return Error / status code: \n 3096 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 3097 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3098 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3099 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3100 * 3101 * \note 3102 * This API is available only for CAT1D devices. 3103 * 3104 *******************************************************************************/ 3105 cy_en_sysclk_status_t Cy_SysClk_DpllLpGetConfiguration(uint32_t pllNum, cy_stc_pll_manual_config_t *config); 3106 3107 3108 /******************************************************************************* 3109 * Function Name: Cy_SysClk_DpllLpEnable 3110 ****************************************************************************//** 3111 * 3112 * Enables the DPLL-LP. The PLL should be configured before calling this function. 3113 * 3114 * \param pllNum Selects which DPLL-LP to enable. 3115 * 3116 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 3117 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 3118 * and manually check for lock using \ref Cy_SysClk_PllLocked. 3119 * 3120 * \return Error / status code: \n 3121 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 3122 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 3123 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3124 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3125 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3126 * 3127 * \note 3128 * Call \ref SystemCoreClockUpdate after this function calling 3129 * if it affects the CLK_HF0 frequency. 3130 * 3131 * \note 3132 * This API is available only for CAT1D devices. 3133 * 3134 *******************************************************************************/ 3135 cy_en_sysclk_status_t Cy_SysClk_DpllLpEnable(uint32_t pllNum, uint32_t timeoutus); 3136 3137 3138 /******************************************************************************* 3139 * Function Name: Cy_SysClk_DpllLpIsEnabled 3140 ****************************************************************************//** 3141 * 3142 * Reports whether or not the selected DPLL-LP is enabled. 3143 * 3144 * \param pllNum Selects which DPLL-LP to check. 3145 * 3146 * \return 3147 * false = disabled \n 3148 * true = enabled 3149 * 3150 * \note 3151 * This API is available only for CAT1D devices. 3152 * 3153 *******************************************************************************/ 3154 bool Cy_SysClk_DpllLpIsEnabled(uint32_t pllNum); 3155 3156 3157 /******************************************************************************* 3158 * Function Name: Cy_SysClk_DpllLpLocked 3159 ****************************************************************************//** 3160 * 3161 * Reports whether or not the selected DPLL-LP is locked. 3162 * 3163 * \param pllNum Selects which DPLL-LP to check. 3164 * 3165 * \return 3166 * false = not locked \n 3167 * true = locked 3168 * 3169 * \note 3170 * This API is available only for CAT1D devices. 3171 * 3172 *******************************************************************************/ 3173 bool Cy_SysClk_DpllLpLocked(uint32_t pllNum); 3174 3175 3176 /******************************************************************************* 3177 * Function Name: Cy_SysClk_DpllLpLostLock 3178 ****************************************************************************//** 3179 * 3180 * Reports whether or not the selected DPLL-LP lost its lock since the last time this 3181 * function was called. Clears the lost lock indicator. 3182 * 3183 * \param pllNum Selects which DPLL-LP to check. 3184 * 3185 * \return 3186 * false = did not lose lock \n 3187 * true = lost lock 3188 * 3189 * \note 3190 * This API is available only for CAT1D devices. 3191 * 3192 *******************************************************************************/ 3193 bool Cy_SysClk_DpllLpLostLock(uint32_t pllNum); 3194 3195 3196 /******************************************************************************* 3197 * Function Name: Cy_SysClk_DpllLpDisable 3198 ****************************************************************************//** 3199 * 3200 * Disables the selected DPLL-LP. 3201 * 3202 * \param pllNum Selects which DPLL-LP to disable. 3203 * 3204 * \return Error / status code: \n 3205 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 3206 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3207 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3208 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3209 * 3210 * \note 3211 * Call \ref SystemCoreClockUpdate after this function calling 3212 * if it affects the CLK_HF0 frequency. 3213 * 3214 * \sideeffect 3215 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 3216 * If AUTO mode should be used, call \ref Cy_SysClk_DpllLpConfigure or 3217 * \ref Cy_SysClk_DpllLpManualConfigure before calling \ref Cy_SysClk_DpllLpEnable. 3218 * 3219 * \note 3220 * This API is available only for CAT1D devices. 3221 * 3222 *******************************************************************************/ 3223 cy_en_sysclk_status_t Cy_SysClk_DpllLpDisable(uint32_t pllNum); 3224 3225 /******************************************************************************* 3226 * Function Name: Cy_SysClk_DpllLpGetFrequency 3227 ****************************************************************************//** 3228 * 3229 * Gets the frequency of DPLL-LP 3230 * 3231 * \param pllNum Selects which DPLL-LP to check. 3232 * 3233 * \return 3234 * DPLL-LP Frequency 3235 * 3236 * \note 3237 * This API is available only for CAT1D devices. 3238 * 3239 *******************************************************************************/ 3240 uint32_t Cy_SysClk_DpllLpGetFrequency(uint32_t pllNum); 3241 3242 #if defined(CY_IP_MXS22SRSS) || defined(CY_DOXYGEN) 3243 3244 /******************************************************************************* 3245 * Function Name: Cy_SysClk_DpllHpConfigure 3246 ****************************************************************************//** 3247 * 3248 * Configures DPLL-HP. 3249 * 3250 * The configuration formula used is: 3251 * Fout = (pll_clk * NDIV) / (PDIV * KDIV), where: 3252 * Fout is the desired output frequency 3253 * pll_clk is the frequency of the input source 3254 * NDIV is the Ratio between DCO frequency and reference frequency. 3255 * PDIV is the reference divider. 3256 * KDIV is the post divider. 3257 * 3258 * \param pllNum Selects which DPLL-HP to configure 3259 * 3260 * \param config \ref cy_stc_pll_config_t 3261 * 3262 * \return Error / status code: \n 3263 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3264 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3265 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 3266 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3267 * 3268 * \note 3269 * Call this function after changing the PLL input frequency, for example if 3270 * \ref Cy_SysClk_ClkPathSetSource() is called. 3271 * 3272 * \note 3273 * Do not call this function when the PLL is enabled. If it is called, then this function 3274 * returns immediately with an error return value and no register updates. 3275 * 3276 * \note 3277 * Call \ref SystemCoreClockUpdate after this function calling 3278 * if it affects the CLK_HF0 frequency. 3279 * 3280 * \note 3281 * This API is available only for CAT1D devices. 3282 * 3283 *******************************************************************************/ 3284 cy_en_sysclk_status_t Cy_SysClk_DpllHpConfigure(uint32_t pllNum, const cy_stc_pll_config_t *config); 3285 3286 3287 /******************************************************************************* 3288 * Function Name: Cy_SysClk_DpllHpManualConfigure 3289 ****************************************************************************//** 3290 * 3291 * Manually configures a DPLL-HP based on user inputs. 3292 * 3293 * \param pllNum Selects which DPLL-HP to configure. 3294 * 3295 * \param config \ref cy_stc_pll_manual_config_t 3296 * 3297 * \return Error / status code: \n 3298 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3299 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3300 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3301 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3302 * 3303 * \note 3304 * Call this function after changing the PLL input frequency; for example if 3305 * \ref Cy_SysClk_ClkPathSetSource() is called. 3306 * 3307 * \note 3308 * Do not call this function when the PLL is enabled. If it is called, then this function 3309 * returns immediately with an error return value and no register updates. 3310 * 3311 * \note 3312 * Call \ref SystemCoreClockUpdate after this function calling 3313 * if it affects the CLK_HF0 frequency. 3314 * 3315 * \note 3316 * This API is available only for CAT1D devices. 3317 * 3318 *******************************************************************************/ 3319 cy_en_sysclk_status_t Cy_SysClk_DpllHpManualConfigure(uint32_t pllNum, const cy_stc_pll_manual_config_t *config); 3320 3321 3322 /******************************************************************************* 3323 * Function Name: Cy_SysClk_DpllHpGetConfiguration 3324 ****************************************************************************//** 3325 * 3326 * Reports configuration settings for DPLL-HP. 3327 * 3328 * \param pllNum Selects which DPLL-HP to report. 3329 * 3330 * \param config \ref cy_stc_pll_manual_config_t 3331 * 3332 * \return Error / status code: \n 3333 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 3334 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3335 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3336 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3337 * 3338 * \note 3339 * This API is available only for CAT1D devices. 3340 * 3341 *******************************************************************************/ 3342 cy_en_sysclk_status_t Cy_SysClk_DpllHpGetConfiguration(uint32_t pllNum, cy_stc_pll_manual_config_t *config); 3343 3344 3345 /******************************************************************************* 3346 * Function Name: Cy_SysClk_DpllHpEnable 3347 ****************************************************************************//** 3348 * 3349 * Enables the DPLL-HP. The PLL should be configured before calling this function. 3350 * 3351 * \param pllNum Selects which DPLL-HP to enable. 3352 * 3353 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 3354 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 3355 * and manually check for lock using \ref Cy_SysClk_PllLocked. 3356 * 3357 * \return Error / status code: \n 3358 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 3359 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 3360 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3361 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3362 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3363 * 3364 * \note 3365 * Call \ref SystemCoreClockUpdate after this function calling 3366 * if it affects the CLK_HF0 frequency. 3367 * 3368 * \note 3369 * This API is available only for CAT1D devices. 3370 * 3371 *******************************************************************************/ 3372 cy_en_sysclk_status_t Cy_SysClk_DpllHpEnable(uint32_t pllNum, uint32_t timeoutus); 3373 3374 3375 /******************************************************************************* 3376 * Function Name: Cy_SysClk_DpllHpIsEnabled 3377 ****************************************************************************//** 3378 * 3379 * Reports whether or not the selected DPLL-HP is enabled. 3380 * 3381 * \param pllNum Selects which DPLL-HP to check. 3382 * 3383 * \return 3384 * false = disabled \n 3385 * true = enabled 3386 * 3387 * \note 3388 * This API is available only for CAT1D devices. 3389 * 3390 *******************************************************************************/ 3391 bool Cy_SysClk_DpllHpIsEnabled(uint32_t pllNum); 3392 3393 3394 /******************************************************************************* 3395 * Function Name: Cy_SysClk_DpllHpLocked 3396 ****************************************************************************//** 3397 * 3398 * Reports whether or not the selected DPLL-HP is locked. 3399 * 3400 * \param pllNum Selects which DPLL-HP to check. 3401 * 3402 * \return 3403 * false = not locked \n 3404 * true = locked 3405 * 3406 * \note 3407 * This API is available only for CAT1D devices. 3408 * 3409 *******************************************************************************/ 3410 bool Cy_SysClk_DpllHpLocked(uint32_t pllNum); 3411 3412 3413 /******************************************************************************* 3414 * Function Name: Cy_SysClk_DpllHpLostLock 3415 ****************************************************************************//** 3416 * 3417 * Reports whether or not the selected DPLL-HP lost its lock since the last time this 3418 * function was called. Clears the lost lock indicator. 3419 * 3420 * \param pllNum Selects which DPLL-HP to check. 3421 * 3422 * \return 3423 * false = did not lose lock \n 3424 * true = lost lock 3425 * 3426 * \note 3427 * This API is available only for CAT1D devices. 3428 * 3429 *******************************************************************************/ 3430 bool Cy_SysClk_DpllHpLostLock(uint32_t pllNum); 3431 3432 3433 /******************************************************************************* 3434 * Function Name: Cy_SysClk_DpllHpDisable 3435 ****************************************************************************//** 3436 * 3437 * Disables the selected DPLL-HP. 3438 * 3439 * \param pllNum Selects which DPLL-HP to disable. 3440 * 3441 * \return Error / status code: \n 3442 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 3443 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3444 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3445 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3446 * 3447 * \note 3448 * Call \ref SystemCoreClockUpdate after this function calling 3449 * if it affects the CLK_HF0 frequency. 3450 * 3451 * \sideeffect 3452 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 3453 * If AUTO mode should be used, call \ref Cy_SysClk_DpllHpConfigure or 3454 * \ref Cy_SysClk_DpllHpManualConfigure before calling \ref Cy_SysClk_DpllHpEnable. 3455 * 3456 * \note 3457 * This API is available only for CAT1D devices. 3458 * 3459 *******************************************************************************/ 3460 cy_en_sysclk_status_t Cy_SysClk_DpllHpDisable(uint32_t pllNum); 3461 3462 /******************************************************************************* 3463 * Function Name: Cy_SysClk_DpllHpGetFrequency 3464 ****************************************************************************//** 3465 * 3466 * Gets the frequency of DPLL-HP 3467 * 3468 * \param pllNum Selects which DPLL-HP to check. 3469 * 3470 * \return 3471 * DPLL-LP Frequency 3472 * 3473 * \note 3474 * This API is available only for CAT1D devices. 3475 * 3476 *******************************************************************************/ 3477 uint32_t Cy_SysClk_DpllHpGetFrequency(uint32_t pllNum); 3478 3479 #endif 3480 #endif 3481 3482 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2) 3483 3484 /******************************************************************************** 3485 * Function Name: Cy_SysClk_Pll200MConfigure 3486 ****************************************************************************//** 3487 * 3488 * Configures 200M PLL. 3489 * The configuration formula used is: 3490 * Fout = pll_clk * (P / Q / div_out), where: 3491 * Fout is the desired output frequency 3492 * pll_clk is the frequency of the input source 3493 * P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. 3494 * Q is the reference divider. Its value is in bitfield REFERENCE_DIV. 3495 * div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. 3496 * 3497 * \param pllNum Selects which PLL to configure 3498 * 3499 * \param config \ref cy_stc_pll_config_t 3500 * 3501 * \return Error / status code: \n 3502 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3503 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3504 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 3505 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3506 * 3507 * \note 3508 * Call this function after changing the PLL input frequency, for example if 3509 * \ref Cy_SysClk_ClkPathSetSource() is called. 3510 * 3511 * \note 3512 * Do not call this function when the PLL is enabled. If it is called, then this function 3513 * returns immediately with an error return value and no register updates. 3514 * 3515 * \note 3516 * Call \ref SystemCoreClockUpdate after this function calling 3517 * if it affects the CLK_HF0 frequency. 3518 * 3519 * \note 3520 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3521 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 3522 * 3523 * \note 3524 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3525 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 3526 * 3527 * \note 3528 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3529 * 3530 *******************************************************************************/ 3531 cy_en_sysclk_status_t Cy_SysClk_Pll200MConfigure(uint32_t pllNum, const cy_stc_pll_config_t *config); 3532 3533 3534 /******************************************************************************* 3535 * Function Name: Cy_SysClk_Pll200MManualConfigure 3536 ****************************************************************************//** 3537 * 3538 * Manually configures a 200M PLL based on user inputs. 3539 * 3540 * \param pllNum Selects which PLL to configure. 3541 * 3542 * \param config \ref cy_stc_pll_manual_config_t 3543 * 3544 * \return Error / status code: \n 3545 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3546 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3547 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3548 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3549 * For the PSoC 64 devices there are possible situations when function returns 3550 * the PRA error status code. This is because for PSoC 64 devices the function 3551 * uses the PRA driver to change the protected registers. Refer to 3552 * \ref cy_en_pra_status_t for more details. 3553 * 3554 * \note 3555 * Call this function after changing the PLL input frequency; for example if 3556 * \ref Cy_SysClk_ClkPathSetSource() is called. 3557 * 3558 * \note 3559 * Do not call this function when the PLL is enabled. If it is called, then this function 3560 * returns immediately with an error return value and no register updates. 3561 * 3562 * \note 3563 * Call \ref SystemCoreClockUpdate after this function calling 3564 * if it affects the CLK_HF0 frequency. 3565 * 3566 * \note 3567 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3568 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 3569 * 3570 * \note 3571 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3572 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 3573 * 3574 * \note 3575 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3576 * 3577 *******************************************************************************/ 3578 cy_en_sysclk_status_t Cy_SysClk_Pll200MManualConfigure(uint32_t pllNum, const cy_stc_pll_manual_config_t *config); 3579 3580 3581 /******************************************************************************* 3582 * Function Name: Cy_SysClk_Pll200MGetConfiguration 3583 ****************************************************************************//** 3584 * 3585 * Reports configuration settings for 200M PLL. 3586 * 3587 * \param pllNum Selects which PLL to report. 3588 * 3589 * \param config \ref cy_stc_pll_manual_config_t 3590 * 3591 * \return Error / status code: \n 3592 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 3593 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3594 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3595 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3596 * 3597 * \note 3598 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3599 * 3600 *******************************************************************************/ 3601 cy_en_sysclk_status_t Cy_SysClk_Pll200MGetConfiguration(uint32_t pllNum, cy_stc_pll_manual_config_t *config); 3602 3603 3604 /******************************************************************************* 3605 * Function Name: Cy_SysClk_Pll200MEnable 3606 ****************************************************************************//** 3607 * 3608 * Enables the 200M PLL. The PLL should be configured before calling this function. 3609 * 3610 * \param pllNum Selects which PLL to enable. 3611 * 3612 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 3613 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 3614 * and manually check for lock using \ref Cy_SysClk_PllLocked. 3615 * 3616 * \return Error / status code: \n 3617 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 3618 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 3619 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3620 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3621 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3622 * 3623 * \note 3624 * Call \ref SystemCoreClockUpdate after this function calling 3625 * if it affects the CLK_HF0 frequency. 3626 * 3627 * \note 3628 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3629 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 3630 * 3631 * \note 3632 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3633 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 3634 * 3635 * \note 3636 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3637 * 3638 *******************************************************************************/ 3639 cy_en_sysclk_status_t Cy_SysClk_Pll200MEnable(uint32_t pllNum, uint32_t timeoutus); 3640 3641 3642 /******************************************************************************* 3643 * Function Name: Cy_SysClk_Pll200MIsEnabled 3644 ****************************************************************************//** 3645 * 3646 * Reports whether or not the selected 200M PLL is enabled. 3647 * 3648 * \param pllNum Selects which PLL to check. 3649 * 3650 * \return 3651 * false = disabled \n 3652 * true = enabled 3653 * 3654 * \note 3655 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3656 * 3657 *******************************************************************************/ 3658 bool Cy_SysClk_Pll200MIsEnabled(uint32_t pllNum); 3659 3660 3661 /******************************************************************************* 3662 * Function Name: Cy_SysClk_Pll200MLocked 3663 ****************************************************************************//** 3664 * 3665 * Reports whether or not the selected 200M PLL is locked. 3666 * 3667 * \param pllNum Selects which PLL to check. 3668 * 3669 * \return 3670 * false = not locked \n 3671 * true = locked 3672 * 3673 * \note 3674 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3675 * 3676 *******************************************************************************/ 3677 bool Cy_SysClk_Pll200MLocked(uint32_t pllNum); 3678 3679 3680 /******************************************************************************* 3681 * Function Name: Cy_SysClk_Pll200MLostLock 3682 ****************************************************************************//** 3683 * 3684 * Reports whether or not the selected 200M PLL lost its lock since the last time this 3685 * function was called. Clears the lost lock indicator. 3686 * 3687 * \param pllNum Selects which PLL to check. 3688 * 3689 * \return 3690 * false = did not lose lock \n 3691 * true = lost lock 3692 * 3693 * \note 3694 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3695 * 3696 *******************************************************************************/ 3697 bool Cy_SysClk_Pll200MLostLock(uint32_t pllNum); 3698 3699 3700 /******************************************************************************* 3701 * Function Name: Cy_SysClk_Pll200MDisable 3702 ****************************************************************************//** 3703 * 3704 * Disables the selected 200M PLL. 3705 * 3706 * \param pllNum Selects which PLL to disable. 3707 * 3708 * \return Error / status code: \n 3709 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 3710 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3711 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3712 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3713 * 3714 * \note 3715 * Call \ref SystemCoreClockUpdate after this function calling 3716 * if it affects the CLK_HF0 frequency. 3717 * 3718 * \note 3719 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3720 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 3721 * 3722 * \note 3723 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3724 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 3725 * 3726 * \sideeffect 3727 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 3728 * If AUTO mode should be used, call \ref Cy_SysClk_PllConfigure or 3729 * \ref Cy_SysClk_PllManualConfigure before calling \ref Cy_SysClk_PllEnable. 3730 * 3731 * \note 3732 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3733 * 3734 *******************************************************************************/ 3735 cy_en_sysclk_status_t Cy_SysClk_Pll200MDisable(uint32_t pllNum); 3736 3737 /******************************************************************************* 3738 * Function Name: Cy_SysClk_Pll200MGetFrequency 3739 ****************************************************************************//** 3740 * 3741 * Gets the frequency of PLL200M 3742 * 3743 * \param pllNum Selects which PLL to check. 3744 * 3745 * \return 3746 * PLL200M Frequency 3747 * 3748 * \note 3749 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3750 * 3751 *******************************************************************************/ 3752 uint32_t Cy_SysClk_Pll200MGetFrequency(uint32_t pllNum); 3753 3754 /* Only include PLL400M functions for devices that can support it. */ 3755 #if defined (CY_SRSS_PLL400M_PRESENT) && (CY_SRSS_PLL400M_PRESENT == 1u) 3756 /******************************************************************************* 3757 * Function Name: Cy_SysClk_Pll400MConfigure 3758 ****************************************************************************//** 3759 * 3760 * Configures 400M PLL. 3761 * The configuration formula used is: 3762 * Fout = pll_clk * (P / Q / div_out), where: 3763 * Fout is the desired output frequency 3764 * pll_clk is the frequency of the input source 3765 * P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. 3766 * Q is the reference divider. Its value is in bitfield REFERENCE_DIV. 3767 * div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. 3768 * 3769 * \param pllNum Selects which PLL to configure 3770 * 3771 * \param config \ref cy_stc_pll_config_t 3772 * 3773 * \return Error / status code: \n 3774 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3775 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3776 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 3777 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3778 * 3779 * \note 3780 * Call this function after changing the PLL input frequency, for example if 3781 * \ref Cy_SysClk_ClkPathSetSource() is called. 3782 * 3783 * \note 3784 * Do not call this function when the PLL is enabled. If it is called, then this function 3785 * returns immediately with an error return value and no register updates. 3786 * 3787 * \note 3788 * Call \ref SystemCoreClockUpdate after this function calling 3789 * if it affects the CLK_HF0 frequency. 3790 * 3791 * \note 3792 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3793 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 3794 * 3795 * \note 3796 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3797 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 3798 * 3799 * \note 3800 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3801 * 3802 *******************************************************************************/ 3803 cy_en_sysclk_status_t Cy_SysClk_Pll400MConfigure(uint32_t pllNum, const cy_stc_pll_config_t *config); 3804 3805 3806 /******************************************************************************* 3807 * Function Name: Cy_SysClk_Pll400MManualConfigure 3808 ****************************************************************************//** 3809 * 3810 * Manually configures a 400M PLL based on user inputs. 3811 * 3812 * \param pllNum Selects which PLL to configure. 3813 * 3814 * \param config \ref cy_stc_pll_manual_config_t 3815 * 3816 * \return Error / status code: \n 3817 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3818 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3819 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3820 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3821 * 3822 * \note 3823 * Call this function after changing the PLL input frequency; for example if 3824 * \ref Cy_SysClk_ClkPathSetSource() is called. 3825 * 3826 * \note 3827 * Do not call this function when the PLL is enabled. If it is called, then this function 3828 * returns immediately with an error return value and no register updates. 3829 * 3830 * \note 3831 * Call \ref SystemCoreClockUpdate after this function calling 3832 * if it affects the CLK_HF0 frequency. 3833 * 3834 * \note 3835 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3836 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 3837 * 3838 * \note 3839 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3840 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 3841 * 3842 * \note 3843 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3844 * 3845 *******************************************************************************/ 3846 cy_en_sysclk_status_t Cy_SysClk_Pll400MManualConfigure(uint32_t pllNum, const cy_stc_pll_manual_config_t *config); 3847 3848 3849 /******************************************************************************* 3850 * Function Name: Cy_SysClk_Pll400MGetConfiguration 3851 ****************************************************************************//** 3852 * 3853 * Reports configuration settings for 400M PLL. 3854 * 3855 * \param pllNum Selects which PLL to report. 3856 * 3857 * \param config \ref cy_stc_pll_manual_config_t 3858 * 3859 * \return Error / status code: \n 3860 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 3861 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3862 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3863 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3864 * 3865 * \note 3866 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3867 * 3868 *******************************************************************************/ 3869 cy_en_sysclk_status_t Cy_SysClk_Pll400MGetConfiguration(uint32_t pllNum, cy_stc_pll_manual_config_t *config); 3870 3871 3872 /******************************************************************************* 3873 * Function Name: Cy_SysClk_Pll400MEnable 3874 ****************************************************************************//** 3875 * 3876 * Enables the 400M PLL. The PLL should be configured before calling this function. 3877 * 3878 * \param pllNum Selects which PLL to enable. 3879 * 3880 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 3881 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 3882 * and manually check for lock using \ref Cy_SysClk_PllLocked. 3883 * 3884 * \return Error / status code: \n 3885 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 3886 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 3887 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3888 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3889 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3890 * 3891 * \note 3892 * Call \ref SystemCoreClockUpdate after this function calling 3893 * if it affects the CLK_HF0 frequency. 3894 * 3895 * \note 3896 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3897 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 3898 * 3899 * \note 3900 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3901 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 3902 * 3903 * \note 3904 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3905 * 3906 *******************************************************************************/ 3907 cy_en_sysclk_status_t Cy_SysClk_Pll400MEnable(uint32_t pllNum, uint32_t timeoutus); 3908 3909 3910 /******************************************************************************* 3911 * Function Name: Cy_SysClk_Pll400MIsEnabled 3912 ****************************************************************************//** 3913 * 3914 * Reports whether or not the selected 400M PLL is enabled. 3915 * 3916 * \param pllNum Selects which PLL to check. 3917 * 3918 * \return 3919 * false = disabled \n 3920 * true = enabled 3921 * 3922 * \note 3923 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3924 * 3925 *******************************************************************************/ 3926 bool Cy_SysClk_Pll400MIsEnabled(uint32_t pllNum); 3927 3928 3929 /******************************************************************************* 3930 * Function Name: Cy_SysClk_Pll400MLocked 3931 ****************************************************************************//** 3932 * 3933 * Reports whether or not the selected 400M PLL is locked. 3934 * 3935 * \param pllNum Selects which PLL to check. 3936 * 3937 * \return 3938 * false = not locked \n 3939 * true = locked 3940 * 3941 * \note 3942 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3943 * 3944 *******************************************************************************/ 3945 bool Cy_SysClk_Pll400MLocked(uint32_t pllNum); 3946 3947 3948 /******************************************************************************* 3949 * Function Name: Cy_SysClk_Pll400MLostLock 3950 ****************************************************************************//** 3951 * 3952 * Reports whether or not the selected 400M PLL lost its lock since the last time this 3953 * function was called. Clears the lost lock indicator. 3954 * 3955 * \param pllNum Selects which PLL to check. 3956 * 3957 * \return 3958 * false = did not lose lock \n 3959 * true = lost lock 3960 * 3961 * \note 3962 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 3963 * 3964 *******************************************************************************/ 3965 bool Cy_SysClk_Pll400MLostLock(uint32_t pllNum); 3966 3967 3968 /******************************************************************************* 3969 * Function Name: Cy_SysClk_Pll400MDisable 3970 ****************************************************************************//** 3971 * 3972 * Disables the selected 400M PLL. 3973 * 3974 * \param pllNum Selects which PLL to disable. 3975 * 3976 * \return Error / status code: \n 3977 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 3978 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3979 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3980 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3981 * 3982 * \note 3983 * Call \ref SystemCoreClockUpdate after this function calling 3984 * if it affects the CLK_HF0 frequency. 3985 * 3986 * \note 3987 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3988 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 3989 * 3990 * \note 3991 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3992 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 3993 * 3994 * \sideeffect 3995 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 3996 * If AUTO mode should be used, call \ref Cy_SysClk_PllConfigure or 3997 * \ref Cy_SysClk_PllManualConfigure before calling \ref Cy_SysClk_PllEnable. 3998 * 3999 * \note 4000 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 4001 * 4002 *******************************************************************************/ 4003 cy_en_sysclk_status_t Cy_SysClk_Pll400MDisable(uint32_t pllNum); 4004 4005 /******************************************************************************* 4006 * Function Name: Cy_SysClk_Pll400MGetFrequency 4007 ****************************************************************************//** 4008 * 4009 * Gets the frequency of PLL400M 4010 * 4011 * \param pllNum Selects which PLL to check. 4012 * 4013 * \return 4014 * PLL400M Frequency 4015 * 4016 * \note 4017 * This API is available only for CAT1A (TVIIBE only) and CAT1C devices. 4018 * 4019 *******************************************************************************/ 4020 uint32_t Cy_SysClk_Pll400MGetFrequency(uint32_t pllNum); 4021 #endif /* defined (CY_SRSS_PLL400M_PRESENT) && (CY_SRSS_PLL400M_PRESENT == 1u) */ 4022 4023 #endif /* defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2) */ 4024 4025 /** \} group_sysclk_pll_funcs */ 4026 4027 #endif 4028 4029 4030 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 4031 /* ========================================================================== */ 4032 /* =========================== IHO SECTION ============================ */ 4033 /* ========================================================================== */ 4034 4035 /** 4036 * \addtogroup group_sysclk_iho_funcs 4037 * \{ 4038 */ 4039 4040 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) 4041 4042 /******************************************************************************* 4043 * Function Name: Cy_SysClk_IhoEnable 4044 ****************************************************************************//** 4045 * 4046 * Enables the IHO. 4047 * 4048 * \note 4049 * Call \ref SystemCoreClockUpdate after this function calling 4050 * if it affects the CLK_HF0 frequency. 4051 * 4052 * \note 4053 * This API is available for CAT1B and CAT1D. 4054 * 4055 * \note 4056 * Take into account the possible platform specific clkHf (and further 4057 * clocking chain links) frequency limitations while using this API. 4058 * 4059 *******************************************************************************/ 4060 void Cy_SysClk_IhoEnable(void); 4061 4062 4063 /******************************************************************************* 4064 * Function Name: Cy_SysClk_IhoIsEnabled 4065 ****************************************************************************//** 4066 * 4067 * Reports whether or not the selected IHO is enabled. 4068 * 4069 * \return 4070 * false = disabled \n 4071 * true = enabled 4072 * 4073 * \note 4074 * This API is available for CAT1B and CAT1D. 4075 * 4076 *******************************************************************************/ 4077 bool Cy_SysClk_IhoIsEnabled(void); 4078 4079 /******************************************************************************* 4080 * Function Name: Cy_SysClk_IhoDisable 4081 ****************************************************************************//** 4082 * 4083 * Disables IHO. 4084 * 4085 * \note 4086 * Call \ref SystemCoreClockUpdate after this function calling 4087 * if it affects the CLK_HF0 frequency. 4088 * 4089 * \note 4090 * This API is available for CAT1B and CAT1D. 4091 * 4092 *******************************************************************************/ 4093 void Cy_SysClk_IhoDisable(void); 4094 4095 #endif 4096 4097 #if defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 4098 4099 /******************************************************************************* 4100 * Function Name: Cy_SysClk_IhoDeepsleepEnable 4101 ****************************************************************************//** 4102 * 4103 * Enables the IHO during deepsleep mode 4104 * 4105 * \note 4106 * Call \ref SystemCoreClockUpdate after this function calling 4107 * if it affects the CLK_HF0 frequency. 4108 * 4109 * \note 4110 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 4111 * 4112 *******************************************************************************/ 4113 void Cy_SysClk_IhoDeepsleepEnable(void); 4114 4115 4116 /******************************************************************************* 4117 * Function Name: Cy_SysClk_IhoIsDeepsleepEnabled 4118 ****************************************************************************//** 4119 * 4120 * Reports whether or not the selected IHO is enabled during deepsleep mode. 4121 * 4122 * \return 4123 * false = disabled \n 4124 * true = enabled 4125 * 4126 * \note 4127 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 4128 * 4129 *******************************************************************************/ 4130 bool Cy_SysClk_IhoIsDeepsleepEnabled(void); 4131 4132 /******************************************************************************* 4133 * Function Name: Cy_SysClk_IhoDeepsleepDisable 4134 ****************************************************************************//** 4135 * 4136 * Disables IHO during deepsleep mode. 4137 * 4138 * \note 4139 * Call \ref SystemCoreClockUpdate after this function calling 4140 * if it affects the CLK_HF0 frequency. 4141 * 4142 * \note 4143 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 4144 * 4145 *******************************************************************************/ 4146 void Cy_SysClk_IhoDeepsleepDisable(void); 4147 4148 /******************************************************************************* 4149 * Function Name: Cy_SysClk_IhoDeepsleepDisable 4150 ****************************************************************************//** 4151 * 4152 * Set the trim value for IHO. 4153 * 4154 * \param trimVal Trim value to be set for IHO. 4155 * 4156 * \note 4157 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 4158 * 4159 *******************************************************************************/ 4160 void Cy_SysClk_IhoSetTrim(uint32_t trimVal); 4161 4162 /******************************************************************************* 4163 * Function Name: Cy_SysClk_IhoDeepsleepDisable 4164 ****************************************************************************//** 4165 * 4166 * Get the trim value configured for IHO. 4167 * 4168 * \return 4169 * Configured IHO Trim value. 4170 * 4171 * \note 4172 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 4173 * 4174 *******************************************************************************/ 4175 uint32_t Cy_SysClk_IhoGetTrim(void); 4176 4177 4178 #endif/* CY_IP_MXS22SRSS*/ 4179 4180 /** \} group_sysclk_iho_funcs */ 4181 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)*/ 4182 4183 /* ========================================================================== */ 4184 /* =========================== IMO SECTION ============================ */ 4185 /* ========================================================================== */ 4186 4187 /** 4188 * \addtogroup group_sysclk_imo_funcs 4189 * \{ 4190 */ 4191 #if defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) 4192 4193 /******************************************************************************* 4194 * Function Name: Cy_SysClk_ImoEnable 4195 ****************************************************************************//** 4196 * 4197 * Enables the IMO. 4198 * 4199 * \note 4200 * This API is available for CAT1A (TVIIBE only), CAT1B and CAT1C devices. 4201 * 4202 *******************************************************************************/ 4203 void Cy_SysClk_ImoEnable(void); 4204 4205 /******************************************************************************* 4206 * Function Name: Cy_SysClk_ImoIsEnabled 4207 ****************************************************************************//** 4208 * 4209 * Reports whether or not the selected IMO is enabled. 4210 * 4211 * \return 4212 * false = disabled \n 4213 * true = enabled 4214 * 4215 * \note 4216 * This API is available for CAT1A (TVIIBE only), CAT1B and CAT1C devices. 4217 * 4218 *******************************************************************************/ 4219 bool Cy_SysClk_ImoIsEnabled(void); 4220 4221 /******************************************************************************* 4222 * Function Name: Cy_SysClk_ImoDisable 4223 ****************************************************************************//** 4224 * 4225 * Disables IMO. 4226 * 4227 * 4228 * \note 4229 * This API is available for CAT1A (TVIIBE only), CAT1B and CAT1C devices. 4230 * 4231 *******************************************************************************/ 4232 void Cy_SysClk_ImoDisable(void); 4233 #endif /* defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) */ 4234 4235 #if defined (CY_IP_MXS40SSRSS) 4236 4237 /******************************************************************************* 4238 * Function Name: Cy_SysClk_ImoDeepsleepEnable 4239 ****************************************************************************//** 4240 * 4241 * Enables the IMO during deepsleep mode 4242 * 4243 * \note 4244 * This API is available for CAT1B devices. 4245 * 4246 *******************************************************************************/ 4247 void Cy_SysClk_ImoDeepsleepEnable(void); 4248 4249 4250 /******************************************************************************* 4251 * Function Name: Cy_SysClk_ImoIsDeepsleepEnabled 4252 ****************************************************************************//** 4253 * 4254 * Reports whether or not the selected IMO is enabled during deepsleep mode. 4255 * 4256 * \return 4257 * false = disabled \n 4258 * true = enabled 4259 * 4260 * \note 4261 * This API is available for CAT1B devices. 4262 * 4263 *******************************************************************************/ 4264 bool Cy_SysClk_ImoIsDeepsleepEnabled(void); 4265 4266 /******************************************************************************* 4267 * Function Name: Cy_SysClk_ImoDeepsleepDisable 4268 ****************************************************************************//** 4269 * 4270 * Disables IMO during deepsleep mode. 4271 * 4272 * \note 4273 * This API is available for CAT1B devices. 4274 * 4275 *******************************************************************************/ 4276 void Cy_SysClk_ImoDeepsleepDisable(void); 4277 #endif /* defined (CY_IP_MXS40SSRSS) */ 4278 /** \} group_sysclk_imo_funcs */ 4279 4280 /* ========================================================================== */ 4281 /* =========================== ILO SECTION ============================ */ 4282 /* ========================================================================== */ 4283 /** 4284 * \addtogroup group_sysclk_ilo_funcs 4285 * \{ 4286 */ 4287 4288 #if defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) 4289 /******************************************************************************* 4290 * Function Name: Cy_SysClk_IloEnable 4291 ****************************************************************************//** 4292 * 4293 * Enables the ILO. 4294 * 4295 * \note The watchdog timer (WDT) must be unlocked before calling this function. 4296 * 4297 * \funcusage 4298 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloEnable 4299 * 4300 * \note 4301 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 4302 * 4303 *******************************************************************************/ 4304 void Cy_SysClk_IloEnable(void); 4305 4306 4307 /******************************************************************************* 4308 * Function Name: Cy_SysClk_IloIsEnabled 4309 ****************************************************************************//** 4310 * 4311 * Reports the Enabled/Disabled status of the ILO. 4312 * 4313 * \return Boolean status of ILO: true - Enabled, false - Disabled. 4314 * 4315 * \funcusage 4316 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable 4317 * 4318 * \note 4319 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 4320 * 4321 *******************************************************************************/ 4322 bool Cy_SysClk_IloIsEnabled(void); 4323 4324 4325 /******************************************************************************* 4326 * Function Name: Cy_SysClk_IloDisable 4327 ****************************************************************************//** 4328 * 4329 * Disables the ILO. ILO can't be disabled if WDT is enabled. 4330 * 4331 * \return Error / status code: \n 4332 * CY_SYSCLK_SUCCESS - ILO successfully disabled \n 4333 * CY_SYSCLK_INVALID_STATE - Cannot disable the ILO if the WDT is enabled. 4334 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 4335 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 4336 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 4337 * uses the PRA driver to change the protected registers. Refer to 4338 * \ref cy_en_pra_status_t for more details. 4339 * 4340 * \note The watchdog timer (WDT) must be unlocked before calling this function. 4341 * Do not call this function if the WDT is enabled, because the WDT is clocked by 4342 * the ILO. 4343 * 4344 * \funcusage 4345 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable 4346 * 4347 * \note 4348 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 4349 * 4350 *******************************************************************************/ 4351 cy_en_sysclk_status_t Cy_SysClk_IloDisable(void); 4352 4353 4354 /******************************************************************************* 4355 * Function Name: Cy_SysClk_IloHibernateOn 4356 ****************************************************************************//** 4357 * 4358 * Controls whether the ILO stays on during a hibernate, or through an XRES or 4359 * brown-out detect (BOD) event. 4360 * 4361 * \param on 4362 * true = ILO stays on during hibernate or across XRES/BOD. \n 4363 * false = ILO turns off for hibernate or XRES/BOD. 4364 * 4365 * \note Writes to the register/bit are ignored if the watchdog (WDT) is locked. 4366 * 4367 * \funcusage 4368 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloHibernateOn 4369 * 4370 * \note 4371 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 4372 * 4373 *******************************************************************************/ 4374 void Cy_SysClk_IloHibernateOn(bool on); 4375 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) */ 4376 4377 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) || defined (CY_DOXYGEN) 4378 /******************************************************************************* 4379 * Function Name: Cy_SysClk_IloSrcEnable 4380 ****************************************************************************//** 4381 * 4382 * Enables the ILO. 4383 * 4384 * \param iloNum - ILO index , 0 : ILO0, 1: ILO1 4385 * 4386 * \funcusage 4387 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloSrcEnable 4388 * 4389 * \note The watchdog timer (WDT) must be unlocked before calling this function. 4390 * 4391 * \note 4392 * This API is available for CAT1A (TVIIBE only) and CAT1C devices. 4393 * 4394 *******************************************************************************/ 4395 void Cy_SysClk_IloSrcEnable(uint32_t iloNum); 4396 4397 4398 /******************************************************************************* 4399 * Function Name: Cy_SysClk_IloSrcIsEnabled 4400 ****************************************************************************//** 4401 * 4402 * Reports the Enabled/Disabled status of the ILO. 4403 * 4404 * \param iloNum - ILO index , ILO0 or ILO1 4405 * 4406 * \funcusage 4407 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloSrcIsEnabled 4408 * 4409 * \return Boolean status of ILO: true - Enabled, false - Disabled. 4410 * 4411 * \note 4412 * This API is available for CAT1A (TVIIBE only) and CAT1C devices. 4413 * 4414 *******************************************************************************/ 4415 bool Cy_SysClk_IloSrcIsEnabled(uint32_t iloNum); 4416 4417 4418 /******************************************************************************* 4419 * Function Name: Cy_SysClk_IloSrcDisable 4420 ****************************************************************************//** 4421 * 4422 * Disables the ILO. ILO can't be disabled if WDT is enabled. 4423 * 4424 * \param iloNum - ILO index , 0 : ILO0, 1: ILO1 4425 * 4426 * \funcusage 4427 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloSrcDisable 4428 * 4429 * \return Error / status code: \n 4430 * CY_SYSCLK_SUCCESS - ILO successfully disabled \n 4431 * CY_SYSCLK_INVALID_STATE - Cannot disable the ILO if the WDT is enabled. 4432 * 4433 * \note The watchdog timer (WDT) must be unlocked before calling this function. 4434 * Do not call this function if the WDT is enabled, because the WDT is clocked by 4435 * the ILO. 4436 * 4437 * \note 4438 * This API is available for CAT1A (TVIIBE only) and CAT1C devices. 4439 * 4440 *******************************************************************************/ 4441 cy_en_sysclk_status_t Cy_SysClk_IloSrcDisable(uint32_t iloNum); 4442 4443 4444 /******************************************************************************* 4445 * Function Name: Cy_SysClk_IloSrcHibernateOn 4446 ****************************************************************************//** 4447 * 4448 * Controls whether the ILO0 stays on during a hibernate, or through an XRES or 4449 * brown-out detect (BOD) event, this feature is not available for ILO1. 4450 * 4451 * \param iloNum - ILO index , 0 : ILO0, 1: ILO1(Feature not available, ignored) 4452 * 4453 * \param on 4454 * true = ILO stays on during hibernate or across XRES/BOD. \n 4455 * false = ILO turns off for hibernate or XRES/BOD. 4456 * 4457 * \funcusage 4458 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloSrcHibernateOn 4459 * 4460 * \note Writes to the register/bit are ignored if the watchdog (WDT) is locked. 4461 * 4462 * \note 4463 * This API is available for CAT1A (TVIIBE only) and CAT1C devices. 4464 * 4465 *******************************************************************************/ 4466 void Cy_SysClk_IloSrcHibernateOn(uint32_t iloNum, bool on); 4467 4468 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) */ 4469 4470 /** \} group_sysclk_ilo_funcs */ 4471 4472 4473 /* ========================================================================== */ 4474 /* =========================== PILO SECTION =========================== */ 4475 /* ========================================================================== */ 4476 /** 4477 * \addtogroup group_sysclk_pilo_funcs 4478 * \{ 4479 */ 4480 4481 /******************************************************************************* 4482 * Function Name: Cy_SysClk_PiloEnable 4483 ****************************************************************************//** 4484 * 4485 * Enables the PILO. 4486 * 4487 * \note This function blocks for 1 millisecond between enabling the PILO and 4488 * releasing the PILO reset. 4489 * 4490 * \funcusage 4491 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloEnable 4492 * 4493 *******************************************************************************/ 4494 void Cy_SysClk_PiloEnable(void); 4495 4496 4497 /******************************************************************************* 4498 * Function Name: Cy_SysClk_PiloIsEnabled 4499 ****************************************************************************//** 4500 * 4501 * Reports the Enabled/Disabled status of the PILO. 4502 * 4503 * \return Boolean status of PILO: true - Enabled, false - Disabled. 4504 * 4505 * \funcusage 4506 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable 4507 * 4508 *******************************************************************************/ 4509 bool Cy_SysClk_PiloIsEnabled(void); 4510 4511 4512 /******************************************************************************* 4513 * Function Name: Cy_SysClk_PiloDisable 4514 ****************************************************************************//** 4515 * 4516 * Disables the PILO. 4517 * 4518 * \funcusage 4519 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable 4520 * 4521 *******************************************************************************/ 4522 void Cy_SysClk_PiloDisable(void); 4523 4524 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) 4525 4526 /******************************************************************************* 4527 * Function Name: Cy_SysClk_PiloSetTrim 4528 ****************************************************************************//** 4529 * 4530 * Sets the PILO trim bits, which adjusts the PILO frequency. This is typically 4531 * done after measuring the PILO frequency; see \ref Cy_SysClk_StartClkMeasurementCounters(). 4532 * 4533 * \funcusage 4534 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim 4535 * 4536 *******************************************************************************/ 4537 void Cy_SysClk_PiloSetTrim(uint32_t trimVal); 4538 4539 4540 /******************************************************************************* 4541 * Function Name: Cy_SysClk_PiloGetTrim 4542 ****************************************************************************//** 4543 * 4544 * Reports the current PILO trim bits value. 4545 * 4546 * \funcusage 4547 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim 4548 * 4549 *******************************************************************************/ 4550 uint32_t Cy_SysClk_PiloGetTrim(void); 4551 #endif /* defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2) */ 4552 4553 4554 #if defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4555 /******************************************************************************* 4556 * Function Name: Cy_SysClk_PiloBackupEnable 4557 ****************************************************************************//** 4558 * 4559 * Enables the PILO as always on if Backup Domain is present. 4560 * 4561 * \note 4562 * This API is available for CAT1B & CAT1D devices. 4563 * 4564 *******************************************************************************/ 4565 void Cy_SysClk_PiloBackupEnable(void); 4566 4567 /******************************************************************************* 4568 * Function Name: Cy_SysClk_PiloBackupDisable 4569 ****************************************************************************//** 4570 * 4571 * Disables the PILO as always on if Backup Domain is present. 4572 * 4573 * \note 4574 * This API is available for CAT1B & CAT1D devices. 4575 * 4576 *******************************************************************************/ 4577 void Cy_SysClk_PiloBackupDisable(void); 4578 4579 /******************************************************************************* 4580 * Function Name: Cy_SysClk_PiloOkay 4581 ****************************************************************************//** 4582 * 4583 * Reports the status of the PILO. 4584 * 4585 * \return 4586 * true = okay \n 4587 * false = not okay 4588 * 4589 * \note 4590 * This API is available for CAT1B(20829) devices. 4591 * 4592 *******************************************************************************/ 4593 bool Cy_SysClk_PiloOkay(void); 4594 4595 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) */ 4596 4597 #if defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4598 4599 /******************************************************************************* 4600 * Function Name: Cy_SysClk_PiloTcscEnable 4601 ****************************************************************************//** 4602 * 4603 * Enables the PILO TCSC(Second order temperature curvature correction) Feature. 4604 * 4605 * \note 4606 * This API is available for CAT1B devices. 4607 * 4608 *******************************************************************************/ 4609 void Cy_SysClk_PiloTcscEnable(void); 4610 4611 4612 /******************************************************************************* 4613 * Function Name: Cy_SysClk_PiloTcscDisable 4614 ****************************************************************************//** 4615 * 4616 * Disables the PILO TCSC(Second order temperature curvature correction) Feature. 4617 * 4618 * \note 4619 * This API is available for CAT1B devices. 4620 * 4621 *******************************************************************************/ 4622 void Cy_SysClk_PiloTcscDisable(void); 4623 4624 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) */ 4625 4626 /** \} group_sysclk_pilo_funcs */ 4627 4628 4629 /* ========================================================================== */ 4630 /* ========================== ALTHF SECTION =========================== */ 4631 /* ========================================================================== */ 4632 /** 4633 * \addtogroup group_sysclk_alt_hf_funcs 4634 * \{ 4635 */ 4636 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4637 /******************************************************************************* 4638 * Function Name: Cy_SysClk_AltHfGetFrequency 4639 ****************************************************************************//** 4640 * 4641 * Reports the frequency of the Alternative High-Frequency Clock 4642 * 4643 * \note 4644 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 4645 * 4646 * \funcusage 4647 * \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() 4648 * 4649 *******************************************************************************/ 4650 uint32_t Cy_SysClk_AltHfGetFrequency(void); 4651 #endif 4652 4653 #if defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4654 /******************************************************************************* 4655 * Function Name: Cy_SysClk_AltHfEnable 4656 ****************************************************************************//** 4657 * 4658 * Enables the ATLHF. 4659 * 4660 * \note 4661 * This API is available for CAT1B devices. 4662 * 4663 * \return Error / status code: \n 4664 * CY_SYSCLK_SUCCESS - ALTHF successfully disabled \n 4665 * CY_SYSCLK_TIMEOUT - ALTHF enabling failed due to timeout 4666 * 4667 *******************************************************************************/ 4668 cy_en_sysclk_status_t Cy_SysClk_AltHfEnable(uint32_t timeoutus); 4669 4670 /******************************************************************************* 4671 * Function Name: Cy_SysClk_IsAltHfEnabled 4672 ****************************************************************************//** 4673 * 4674 * Reports if ALTHF is enabled or not 4675 * 4676 * \note 4677 * This API is available for CAT1B devices. 4678 * 4679 * \return Status of ALTHF \n 4680 * true = Enabled \n 4681 * false = Not Enabled 4682 * 4683 *******************************************************************************/ 4684 bool Cy_SysClk_IsAltHfEnabled(void); 4685 4686 #endif /* defined (CY_IP_MXS40SSRSS) */ 4687 4688 /** \} group_sysclk_alt_hf_funcs */ 4689 4690 4691 /* ========================================================================== */ 4692 /* ========================== ALTLF SECTION =========================== */ 4693 /* ========================================================================== */ 4694 /** \cond For future usage */ 4695 uint32_t Cy_SysClk_AltLfGetFrequency(void); 4696 bool Cy_SysClk_AltLfIsEnabled(void); 4697 /** \endcond */ 4698 4699 4700 /* ========================================================================== */ 4701 /* ==================== CLOCK MEASUREMENT SECTION ===================== */ 4702 /* ========================================================================== */ 4703 /** 4704 * \addtogroup group_sysclk_calclk_enums 4705 * \{ 4706 */ 4707 /** Defines all possible clock sources */ 4708 #if defined(CY_IP_MXS22SRSS) 4709 typedef enum 4710 { 4711 CY_SYSCLK_MEAS_CLK_NC = 0U, 4712 CY_SYSCLK_MEAS_CLK_ILO = 1U, 4713 CY_SYSCLK_MEAS_CLK_WCO = 2U, 4714 CY_SYSCLK_MEAS_CLK_BAK = 3U, 4715 CY_SYSCLK_MEAS_CLK_ALTLF = 4U, 4716 CY_SYSCLK_MEAS_CLK_LFCLK = 5U, 4717 CY_SYSCLK_MEAS_CLK_IMO = 6U, 4718 CY_SYSCLK_MEAS_CLK_SLPCTRL = 7U, 4719 CY_SYSCLK_MEAS_CLK_PILO = 8U, 4720 CY_SYSCLK_MEAS_CLK_ECO_PRESCALER = 9U, 4721 CY_SYSCLK_MEAS_CLK_MF = 10U, 4722 CY_SYSCLK_MEAS_CLK_FAST_CLKS = 0x100U, 4723 CY_SYSCLK_MEAS_CLK_IHO = 0x101U, 4724 CY_SYSCLK_MEAS_CLK_EXT = 0x102U, 4725 CY_SYSCLK_MEAS_CLK_ECO = 0x103U, 4726 CY_SYSCLK_MEAS_CLK_ALTHF0 = 0x105U, 4727 CY_SYSCLK_MEAS_CLK_ALTHF1 = 0x106U, 4728 CY_SYSCLK_MEAS_CLK_TIMERCLK = 0x108U, 4729 CY_SYSCLK_MEAS_CLK_PATH_CLKS = 0x900U, 4730 CY_SYSCLK_MEAS_CLK_PATH0 = 0x900U, 4731 CY_SYSCLK_MEAS_CLK_PATH1 = 0x901U, 4732 CY_SYSCLK_MEAS_CLK_PATH2 = 0x902U, 4733 CY_SYSCLK_MEAS_CLK_PATH3 = 0x903U, 4734 CY_SYSCLK_MEAS_CLK_PATH4 = 0x904U, 4735 CY_SYSCLK_MEAS_CLK_PATH5 = 0x905U, 4736 CY_SYSCLK_MEAS_CLK_PATH6 = 0x906U, 4737 CY_SYSCLK_MEAS_CLK_PATH7 = 0x907U, 4738 CY_SYSCLK_MEAS_CLK_PATH8 = 0x908U, 4739 CY_SYSCLK_MEAS_CLK_PATH9 = 0x909U, 4740 CY_SYSCLK_MEAS_CLK_PATH10 = 0x90AU, 4741 CY_SYSCLK_MEAS_CLK_PATH11 = 0x90BU, 4742 CY_SYSCLK_MEAS_CLK_PATH12 = 0x90CU, 4743 CY_SYSCLK_MEAS_CLK_PATH13 = 0x90DU, 4744 CY_SYSCLK_MEAS_CLK_PATH14 = 0x90EU, 4745 CY_SYSCLK_MEAS_CLK_PATH15 = 0x90FU, 4746 CY_SYSCLK_MEAS_CLK_CLKHFS = 0xA00U, 4747 CY_SYSCLK_MEAS_CLK_CLKHF0 = 0xA00U, 4748 CY_SYSCLK_MEAS_CLK_CLKHF1 = 0xA01U, 4749 CY_SYSCLK_MEAS_CLK_CLKHF2 = 0xA02U, 4750 CY_SYSCLK_MEAS_CLK_CLKHF3 = 0xA03U, 4751 CY_SYSCLK_MEAS_CLK_CLKHF4 = 0xA04U, 4752 CY_SYSCLK_MEAS_CLK_CLKHF5 = 0xA05U, 4753 CY_SYSCLK_MEAS_CLK_CLKHF6 = 0xA06U, 4754 CY_SYSCLK_MEAS_CLK_CLKHF7 = 0xA07U, 4755 CY_SYSCLK_MEAS_CLK_CLKHF8 = 0xA08U, 4756 CY_SYSCLK_MEAS_CLK_CLKHF9 = 0xA09U, 4757 CY_SYSCLK_MEAS_CLK_CLKHF10 = 0xA0AU, 4758 CY_SYSCLK_MEAS_CLK_CLKHF11 = 0xA0BU, 4759 CY_SYSCLK_MEAS_CLK_CLKHF12 = 0xA0CU, 4760 CY_SYSCLK_MEAS_CLK_CLKHF13 = 0xA0DU, 4761 CY_SYSCLK_MEAS_CLK_CLKHF14 = 0xA0EU, 4762 CY_SYSCLK_MEAS_CLK_CLKHF15 = 0xA0FU, 4763 CY_SYSCLK_MEAS_CLK_LAST_CLK = 0xA10U 4764 } cy_en_meas_clks_t; 4765 #else 4766 typedef enum 4767 { 4768 CY_SYSCLK_MEAS_CLK_NC = 0U, 4769 CY_SYSCLK_MEAS_CLK_ILO = 1U, 4770 CY_SYSCLK_MEAS_CLK_WCO = 2U, 4771 CY_SYSCLK_MEAS_CLK_BAK = 3U, 4772 CY_SYSCLK_MEAS_CLK_ALTLF = 4U, 4773 CY_SYSCLK_MEAS_CLK_LFCLK = 5U, 4774 CY_SYSCLK_MEAS_CLK_IMO = 6U, 4775 CY_SYSCLK_MEAS_CLK_SLPCTRL = 7U, 4776 CY_SYSCLK_MEAS_CLK_PILO = 8U, 4777 CY_SYSCLK_MEAS_CLK_ILO1 = 9U, 4778 CY_SYSCLK_MEAS_CLK_ECO_PRESCALER = 10U, 4779 CY_SYSCLK_MEAS_CLK_LPECO = 11U, 4780 CY_SYSCLK_MEAS_CLK_LPECO_PRESCALER = 12U, 4781 CY_SYSCLK_MEAS_CLK_MFO = 13U, 4782 CY_SYSCLK_MEAS_CLK_FAST_CLKS = 0x100U, 4783 CY_SYSCLK_MEAS_CLK_ECO = 0x101U, 4784 CY_SYSCLK_MEAS_CLK_EXT = 0x102U, 4785 CY_SYSCLK_MEAS_CLK_ALTHF = 0x103U, 4786 CY_SYSCLK_MEAS_CLK_TIMERCLK = 0x104U, 4787 CY_SYSCLK_MEAS_CLK_IHO = 0x108U, 4788 CY_SYSCLK_MEAS_CLK_PWR = 0x109U, 4789 CY_SYSCLK_MEAS_CLK_PATH_CLKS = 0x500U, 4790 CY_SYSCLK_MEAS_CLK_PATH0 = 0x500U, 4791 CY_SYSCLK_MEAS_CLK_PATH1 = 0x501U, 4792 CY_SYSCLK_MEAS_CLK_PATH2 = 0x502U, 4793 CY_SYSCLK_MEAS_CLK_PATH3 = 0x503U, 4794 CY_SYSCLK_MEAS_CLK_PATH4 = 0x504U, 4795 CY_SYSCLK_MEAS_CLK_PATH5 = 0x505U, 4796 CY_SYSCLK_MEAS_CLK_PATH6 = 0x506U, 4797 CY_SYSCLK_MEAS_CLK_PATH7 = 0x507U, 4798 CY_SYSCLK_MEAS_CLK_PATH8 = 0x508U, 4799 CY_SYSCLK_MEAS_CLK_PATH9 = 0x509U, 4800 CY_SYSCLK_MEAS_CLK_PATH10 = 0x50AU, 4801 CY_SYSCLK_MEAS_CLK_PATH11 = 0x50BU, 4802 CY_SYSCLK_MEAS_CLK_PATH12 = 0x50CU, 4803 CY_SYSCLK_MEAS_CLK_PATH13 = 0x50DU, 4804 CY_SYSCLK_MEAS_CLK_PATH14 = 0x50EU, 4805 CY_SYSCLK_MEAS_CLK_PATH15 = 0x50FU, 4806 CY_SYSCLK_MEAS_CLK_CLKHFS = 0x600U, 4807 CY_SYSCLK_MEAS_CLK_CLKHF0 = 0x600U, 4808 CY_SYSCLK_MEAS_CLK_CLKHF1 = 0x601U, 4809 CY_SYSCLK_MEAS_CLK_CLKHF2 = 0x602U, 4810 CY_SYSCLK_MEAS_CLK_CLKHF3 = 0x603U, 4811 CY_SYSCLK_MEAS_CLK_CLKHF4 = 0x604U, 4812 CY_SYSCLK_MEAS_CLK_CLKHF5 = 0x605U, 4813 CY_SYSCLK_MEAS_CLK_CLKHF6 = 0x606U, 4814 CY_SYSCLK_MEAS_CLK_CLKHF7 = 0x607U, 4815 CY_SYSCLK_MEAS_CLK_CLKHF8 = 0x608U, 4816 CY_SYSCLK_MEAS_CLK_CLKHF9 = 0x609U, 4817 CY_SYSCLK_MEAS_CLK_CLKHF10 = 0x60AU, 4818 CY_SYSCLK_MEAS_CLK_CLKHF11 = 0x60BU, 4819 CY_SYSCLK_MEAS_CLK_CLKHF12 = 0x60CU, 4820 CY_SYSCLK_MEAS_CLK_CLKHF13 = 0x60DU, 4821 CY_SYSCLK_MEAS_CLK_CLKHF14 = 0x60EU, 4822 CY_SYSCLK_MEAS_CLK_CLKHF15 = 0x60FU, 4823 CY_SYSCLK_MEAS_CLK_LAST_CLK = 0x610U 4824 } cy_en_meas_clks_t; 4825 #endif 4826 /** \} group_sysclk_calclk_enums */ 4827 4828 /** 4829 * \addtogroup group_sysclk_calclk_structs 4830 * \{ 4831 */ 4832 #if (defined(CY_DEVICE_SECURE)) 4833 /** PRA structure for Cy_SysClk_StartClkMeasurementCounters function parameters */ 4834 typedef struct 4835 { 4836 cy_en_meas_clks_t clock1; /**< clock1 */ 4837 uint32_t count1; /**< count */ 4838 cy_en_meas_clks_t clock2; /**< clock2 */ 4839 } cy_stc_pra_start_clk_measurement_t; 4840 4841 #endif /* (defined(CY_DEVICE_SECURE)) */ 4842 /** \} group_sysclk_calclk_structs */ 4843 4844 /** 4845 * \addtogroup group_sysclk_calclk_funcs 4846 * \{ 4847 */ 4848 /******************************************************************************* 4849 * Function Name: Cy_SysClk_StartClkMeasurementCounters 4850 ****************************************************************************//** 4851 * 4852 * Assigns clocks to the clock measurement counters, and starts counting. The counters 4853 * let you measure a clock frequency using another clock as a reference. There are two 4854 * counters. 4855 * 4856 * - One counter (counter1), which is clocked by clock1, is loaded with an initial 4857 * value and counts down to zero. 4858 * - The second counter (counter2), which is clocked by clock2, counts up until 4859 * the first counter reaches zero. 4860 * 4861 * Either clock1 or clock2 can be a reference clock; the other clock becomes the 4862 * measured clock. The reference clock frequency is always known. \n 4863 * After calling this function, call \ref Cy_SysClk_ClkMeasurementCountersDone() 4864 * to determine when counting is done; that is, counter1 has counted down to zero. 4865 * Then call \ref Cy_SysClk_ClkMeasurementCountersGetFreq() to calculate the frequency 4866 * of the measured clock. 4867 * 4868 * \param clock1 The clock for counter1 4869 * 4870 * \param count1 The initial value for counter1, from which counter1 counts down to zero. 4871 * 4872 * \param clock2 The clock for counter2 4873 * 4874 * \return Error / status code: \n 4875 * CY_SYSCLK_INVALID_STATE if already doing a measurement \n 4876 * CY_SYSCLK_BAD_PARAM if invalid clock input parameter \n 4877 * else CY_SYSCLK_SUCCESS 4878 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 4879 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 4880 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 4881 * uses the PRA driver to change the protected registers. Refer to 4882 * \ref cy_en_pra_status_t for more details. 4883 * 4884 * \note The counters are both 24-bit, so the maximum value of count1 is 0xFFFFFF. 4885 * If clock2 frequency is greater than clock1, make sure that count1 is low enough 4886 * that counter2 does not overflow before counter1 reaches zero. 4887 * \note The time to complete a measurement is count1 / clock1 frequency. 4888 * \note The clocks for both counters must have a nonzero frequency, or 4889 * \ref Cy_SysClk_ClkMeasurementCountersGetFreq() incorrectly reports the result of the 4890 * previous measurement. 4891 * \note Do not enter a device low power mode (Sleep, Deep Sleep) while doing a measurement; 4892 * the measured clock frequency may not be accurate. 4893 * 4894 * \funcusage 4895 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_StartClkMeasurementCounters 4896 * 4897 *******************************************************************************/ 4898 cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2); 4899 4900 4901 /******************************************************************************* 4902 * Function Name: Cy_SysClk_ClkMeasurementCountersGetFreq 4903 ****************************************************************************//** 4904 * 4905 * Calculates the frequency of the indicated measured clock (clock1 or clock2). 4906 * - If clock1 is the measured clock, its frequency is: clock1 frequency = (count1 / count2) * clock2 frequency 4907 * - If clock2 is the measured clock, its frequency is: clock2 frequency = (count2 / count1) * clock1 frequency 4908 * 4909 * Call this function only after counting is done; see \ref Cy_SysClk_ClkMeasurementCountersDone(). 4910 * 4911 * \param measuredClock False (0) if the measured clock is clock1; true (1) 4912 * if the measured clock is clock2. 4913 * 4914 * \param refClkFreq The reference clock frequency (clock1 or clock2). 4915 * 4916 * \return The frequency of the measured clock, in Hz. 4917 * \warning The function returns zero, if during measurement device was in the 4918 * Deep Sleep or partially blocking flash operation occurred. It means that 4919 * current measurement is not valid and you should call the 4920 * Cy_SysClk_StartClkMeasurementCounters() function once again. 4921 * 4922 * \funcusage 4923 * Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage. 4924 * 4925 *******************************************************************************/ 4926 uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq); 4927 4928 4929 /******************************************************************************* 4930 * Function Name: Cy_SysClk_ClkMeasurementCountersDone 4931 ****************************************************************************//** 4932 * 4933 * Checks if clock measurement counting is done, that is, counter1 has counted down 4934 * to zero. Call \ref Cy_SysClk_StartClkMeasurementCounters() before calling this function. 4935 * 4936 * \return Status of calibration counters: \n 4937 * true = done \n 4938 * false = not done 4939 * 4940 * \funcusage 4941 * Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage. 4942 * 4943 *******************************************************************************/ 4944 bool Cy_SysClk_ClkMeasurementCountersDone(void); 4945 /** \} group_sysclk_calclk_funcs */ 4946 4947 4948 /* ========================================================================== */ 4949 /* ========================== TRIM SECTION ============================ */ 4950 /* ========================================================================== */ 4951 /** 4952 * \addtogroup group_sysclk_trim_funcs 4953 * \{ 4954 */ 4955 4956 #if defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) 4957 4958 /******************************************************************************* 4959 * Function Name: Cy_SysClk_IloTrim 4960 ****************************************************************************//** 4961 * 4962 * Trims the ILO to be as close to 32,768 Hz as possible. 4963 * 4964 * \param iloFreq current ILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters 4965 * and other measurement functions to obtain the current frequency of the ILO. 4966 * 4967 * \return Change in trim value - 0 if done; that is, no change in trim value. 4968 * 4969 * \note The watchdog timer (WDT) must be unlocked before calling this function. 4970 * 4971 * \funcusage 4972 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloTrim 4973 * 4974 *******************************************************************************/ 4975 int32_t Cy_SysClk_IloTrim(uint32_t iloFreq); 4976 #endif 4977 4978 #if defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4979 /******************************************************************************* 4980 * Function Name: Cy_SysClk_IloSetTrim 4981 ****************************************************************************//** 4982 * 4983 * Set ILO Trim Value 4984 * 4985 * \param trimVal Trim value to be set for ILO. 4986 * 4987 * \note 4988 * The function is applicable only for a CAT1B Devices. 4989 * 4990 *******************************************************************************/ 4991 void Cy_SysClk_IloSetTrim(uint32_t trimVal); 4992 4993 4994 /******************************************************************************* 4995 * Function Name: Cy_SysClk_IloGetTrim 4996 ****************************************************************************//** 4997 * 4998 * Gets the ILO Trim Value. 4999 * 5000 * \return ILO Trim Value. 5001 * 5002 * \note 5003 * The function is applicable only for a CAT1B Devices. 5004 * 5005 *******************************************************************************/ 5006 uint32_t Cy_SysClk_IloGetTrim(void); 5007 5008 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) */ 5009 5010 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) 5011 5012 /******************************************************************************* 5013 * Function Name: Cy_SysClk_PiloTrim 5014 ****************************************************************************//** 5015 * 5016 * Trims the PILO to be as close to 32,768 Hz as possible. 5017 * 5018 * \param piloFreq current PILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters 5019 * and other measurement functions to obtain the current frequency of the PILO. 5020 * 5021 * \return Change in trim value; 0 if done, that is, no change in trim value. 5022 * 5023 * \funcusage 5024 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloTrim 5025 * 5026 *******************************************************************************/ 5027 int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq); 5028 5029 /******************************************************************************* 5030 * Function Name: Cy_SysClk_PiloInitialTrim 5031 ****************************************************************************//** 5032 * 5033 * Initial trims the PILO to be as close to 32,768 Hz as possible. 5034 * This function takes ECO ALTHF as reference clock and calculate Fine PILO 5035 * frequency trimming, by using binary search algorithm. 5036 * 5037 * This function requires configured BLE ECO ALTHF clock. 5038 * Use ModusToolbox Device Configurator to configure BLE ECO ALTHF clock. 5039 * 5040 * \note 5041 * This function must be call after every power-up. 5042 * 5043 * \funcusage 5044 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloInitialTrimAndUpdateTrimStep 5045 * 5046 *******************************************************************************/ 5047 void Cy_SysClk_PiloInitialTrim(void); 5048 5049 /******************************************************************************* 5050 * Function Name: Cy_SysClk_PiloUpdateTrimStep 5051 ****************************************************************************//** 5052 * 5053 * Calculates and updates the PILO trim step size (stepSize variable). 5054 * The stepSize value is used by \ref Cy_SysClk_PiloTrim function during periodical 5055 * PILO calibration. 5056 * 5057 * This function requires configured BLE ECO ALTHF clock. 5058 * Use ModusToolbox Device Configurator to configure BLE ECO ALTHF clock. 5059 * 5060 * \note 5061 * This function must be call after every power-up after call of 5062 * \ref Cy_SysClk_PiloInitialTrim function. 5063 * 5064 * \note 5065 * To achieve best trimming results it is recommended to configure BLE ECO ALTHF 5066 * reference clock to 16 MHz. 5067 * 5068 * \funcusage 5069 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloInitialTrimAndUpdateTrimStep 5070 * 5071 *******************************************************************************/ 5072 void Cy_SysClk_PiloUpdateTrimStep(void); 5073 5074 #endif /* defined (CY_IP_MXS40SRSS) */ 5075 5076 /** \} group_sysclk_trim_funcs */ 5077 5078 5079 /* ========================================================================== */ 5080 /* ====================== POWER MANAGEMENT SECTION ==================== */ 5081 /* ========================================================================== */ 5082 /** 5083 * \addtogroup group_sysclk_pm_funcs 5084 * \{ 5085 */ 5086 /******************************************************************************* 5087 * Function Name: Cy_SysClk_DeepSleepCallback 5088 ****************************************************************************//** 5089 * 5090 * Callback function to be used when entering system Deep Sleep mode. 5091 * This function is applicable if: 5092 * - The FLL is enabled 5093 * - The PLL is enabled and is driven by ECO 5094 * 5095 * This function performs the following: 5096 * 5097 * 1. Before entering Deep Sleep, the clock configuration is saved in SRAM. 5098 * If the FLL/PLL source is the ECO, then the FLL/PLL is bypassed and the 5099 * source is changed to IMO. \n 5100 * If the FLL is enabled - it is just bypassed. 5101 * 2. Upon wakeup from Deep Sleep, the function waits for ECO stabilization, 5102 * then restores the configuration and waits for the FLL/PLL to regain their 5103 * frequency locks. \n 5104 * If ECO is not used and FLL is enabled - it waits for FLL lock and unbypasses it. 5105 * 5106 * The function prevents entry into Deep Sleep mode if the measurement counters 5107 * are currently counting; see \ref Cy_SysClk_StartClkMeasurementCounters. 5108 * 5109 * This function can be called during execution of \ref Cy_SysPm_CpuEnterDeepSleep. 5110 * To do so, register this function as a callback before calling 5111 * \ref Cy_SysPm_CpuEnterDeepSleep - specify \ref CY_SYSPM_DEEPSLEEP as the callback 5112 * type and call \ref Cy_SysPm_RegisterCallback. 5113 * 5114 * \note 5115 * This function is recommended to be the last callback that is registered. 5116 * Doing so minimizes the time spent on low power mode entry and exit. \n 5117 * This function implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t. 5118 * So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL. \n 5119 * This function does not support such cases as, for example, FLL is enabled 5120 * but bypassed by user code before entering Deep Sleep. \n 5121 * You can use this callback implementation as an example to design custom low-power 5122 * callbacks for certain user application. 5123 * 5124 * \param callbackParams 5125 * structure with the syspm callback parameters, 5126 * see \ref cy_stc_syspm_callback_params_t. 5127 * 5128 * \param mode 5129 * Callback mode, see \ref cy_en_syspm_callback_mode_t 5130 * 5131 * \return Error / status code; see \ref cy_en_syspm_status_t. Pass if not doing 5132 * a clock measurement, otherwise Fail. Timeout if timeout waiting for ECO, FLL 5133 * or PLL to get stable / regain its frequency lock. 5134 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 5135 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 5136 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 5137 * uses the PRA driver to change the protected registers. Refer to 5138 * \ref cy_en_pra_status_t for more details. 5139 * 5140 * \funcusage 5141 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_DeepSleepCallback 5142 * 5143 *******************************************************************************/ 5144 cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams, cy_en_syspm_callback_mode_t mode); 5145 /** \} group_sysclk_pm_funcs */ 5146 5147 5148 /* ========================================================================== */ 5149 /* =========================== WCO SECTION ============================ */ 5150 /* ========================================================================== */ 5151 /** 5152 * \addtogroup group_sysclk_wco_enums 5153 * \{ 5154 */ 5155 /** WCO bypass modes */ 5156 typedef enum 5157 { 5158 CY_SYSCLK_WCO_NOT_BYPASSED = 0U, /**< WCO is not bypassed crystal is used */ 5159 CY_SYSCLK_WCO_BYPASSED = 1U /**< WCO is bypassed external clock must be supplied on XTAL pin */ 5160 } cy_en_wco_bypass_modes_t; 5161 5162 #if defined (CY_IP_MXS28SRSS) 5163 /** WCO GM Config */ 5164 /** 5165 * \note 5166 * This enum is available for CAT1B devices. 5167 **/ 5168 typedef enum 5169 { 5170 CY_SYSCLK_WCO_GM_0P5 = 0U, /**< WCO GM - 0.5x */ 5171 CY_SYSCLK_WCO_GM_1P0 = 1U, /**< WCO GM - 1.0x */ 5172 CY_SYSCLK_WCO_GM_1P5 = 2U, /**< WCO GM - 1.5x */ 5173 CY_SYSCLK_WCO_GM_2P0 = 3U, /**< WCO GM - 2.0x */ 5174 CY_SYSCLK_WCO_GM_2P5 = 4U, /**< WCO GM - 2.5x */ 5175 CY_SYSCLK_WCO_GM_3P0 = 5U, /**< WCO GM - 3.0x */ 5176 CY_SYSCLK_WCO_GM_3P5 = 6U, /**< WCO GM - 3.5x */ 5177 CY_SYSCLK_WCO_GM_4P0 = 7U, /**< WCO GM - 4.0x */ 5178 } cy_en_wco_gain_ctrl_modes_t; 5179 #endif /* CY_IP_MXS28SRSS */ 5180 5181 #if defined (CY_IP_MXS40SRSS) 5182 /** \cond BWC */ 5183 /** 5184 * \note 5185 * This enum is available for CAT1A devices. 5186 **/ 5187 typedef enum 5188 { 5189 CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, 5190 CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, 5191 CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO 5192 } cy_en_wco_csv_supervisor_clock_t; 5193 5194 #endif /* CY_IP_MXS40SRSS */ 5195 5196 5197 /** 5198 * Clock supervisor clock loss window. There must be one clock of the supervised 5199 * clock within this many clocks of the supervising clock. 5200 * See registers CLK_CSV_HF_CTL and CLK_CSV_WCO_CTL, bitfield CSV_LOSS_WINDOW. 5201 */ 5202 typedef enum 5203 { 5204 CY_SYSCLK_CSV_LOSS_4_CYCLES = 0U, /**< 1 clock must be seen within 4 cycles of the supervising clock */ 5205 CY_SYSCLK_CSV_LOSS_8_CYCLES = 1U, /**< 1 clock must be seen within 8 cycles of the supervising clock */ 5206 CY_SYSCLK_CSV_LOSS_16_CYCLES = 2U, /**< 1 clock must be seen within 16 cycles of the supervising clock */ 5207 CY_SYSCLK_CSV_LOSS_32_CYCLES = 3U, /**< 1 clock must be seen within 32 cycles of the supervising clock */ 5208 CY_SYSCLK_CSV_LOSS_64_CYCLES = 4U, /**< 1 clock must be seen within 64 cycles of the supervising clock */ 5209 CY_SYSCLK_CSV_LOSS_128_CYCLES = 5U, /**< 1 clock must be seen within 128 cycles of the supervising clock */ 5210 CY_SYSCLK_CSV_LOSS_256_CYCLES = 6U, /**< 1 clock must be seen within 256 cycles of the supervising clock */ 5211 CY_SYSCLK_CSV_LOSS_512_CYCLES = 7U /**< 1 clock must be seen within 512 cycles of the supervising clock */ 5212 } cy_en_csv_loss_window_t; 5213 5214 /** 5215 * Clock supervisor error actions. See register CLK_CSV_HF_CTL[CSV_FREQ_ACTION and CSV_LOSS_ACTION]. 5216 */ 5217 typedef enum 5218 { 5219 CY_SYSCLK_CSV_ERROR_IGNORE = 0U, /**< Ignore the error reported by the clock supervisor */ 5220 CY_SYSCLK_CSV_ERROR_FAULT = 1U, /**< Trigger a fault when an error is reported by the clock supervisor */ 5221 CY_SYSCLK_CSV_ERROR_RESET = 2U, /**< Trigger a reset when an error is reported by the clock supervisor */ 5222 CY_SYSCLK_CSV_ERROR_FAULT_RESET = 3U /**< Trigger a fault then reset when an error is reported by the supervisor */ 5223 } cy_en_csv_error_actions_t; 5224 5225 #if defined (CY_IP_MXS28SRSS) 5226 /** WCO CSV supervisor clock selections */ 5227 /** 5228 * \note 5229 * This enum is available for CAT1B devices. 5230 **/ 5231 typedef enum 5232 { 5233 CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, /**< WCO CSV supervisor clock source is the ILO */ 5234 CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, /**< WCO CSV supervisor clock source is the alternate low-frequency clock (ALTLF) */ 5235 CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO /**< WCO CSV supervisor clock source is the PILO */ 5236 } cy_en_wco_csv_supervisor_clock_t; 5237 5238 /** \endcond */ 5239 5240 /** \} group_sysclk_wco_enums */ 5241 5242 /** \cond BWC */ 5243 5244 /** 5245 * \addtogroup group_sysclk_wco_structs 5246 * \{ 5247 */ 5248 /** 5249 * This structure is used to configure the clock supervisor for the WCO. 5250 */ 5251 /** 5252 * \note 5253 * This structure is available for CAT1B devices. 5254 **/ 5255 typedef struct 5256 { 5257 cy_en_wco_csv_supervisor_clock_t supervisorClock; /**< supervisor clock selection */ 5258 bool enableLossDetection; /**< 1= enabled, 0= disabled. Note that if loss detection is enabled, writes to other register bits are ignored */ 5259 cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */ 5260 cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */ 5261 } cy_stc_wco_csv_config_t; 5262 5263 #endif /* CY_IP_MXS28SRSS */ 5264 5265 /** \} group_sysclk_wco_structs */ 5266 5267 #if defined (CY_IP_MXS40SRSS) 5268 /** 5269 * \note 5270 * This structure is available for CAT1A devices. 5271 **/ 5272 typedef struct 5273 { 5274 cy_en_wco_csv_supervisor_clock_t supervisorClock; 5275 bool enableLossDetection; 5276 cy_en_csv_loss_window_t lossWindow; 5277 cy_en_csv_error_actions_t lossAction; 5278 } cy_stc_wco_csv_config_t; 5279 /** \endcond */ 5280 #endif /* CY_IP_MXS40SRSS */ 5281 5282 /** 5283 * \addtogroup group_sysclk_wco_funcs 5284 * \{ 5285 */ 5286 /******************************************************************************* 5287 * Function Name: Cy_SysClk_WcoEnable 5288 ****************************************************************************//** 5289 * 5290 * Enables the WCO. 5291 * 5292 * \param timeoutus amount of time in microseconds to wait for the WCO to be ready. 5293 * If WCO is not ready, WCO is stopped. To avoid waiting for WCO ready set this to 0, 5294 * and manually check if WCO is okay using \ref Cy_SysClk_WcoOkay. 5295 * 5296 * \return Error / status code: \n 5297 * CY_SYSCLK_SUCCESS - WCO successfully enabled \n 5298 * CY_SYSCLK_TIMEOUT - Timeout waiting for WCO to stabilize 5299 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 5300 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 5301 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 5302 * uses the PRA driver to change the protected registers. Refer to 5303 * \ref cy_en_pra_status_t for more details. 5304 * 5305 * \funcusage 5306 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoEnable 5307 * 5308 *******************************************************************************/ 5309 cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus); 5310 5311 5312 /******************************************************************************* 5313 * Function Name: Cy_SysClk_WcoOkay 5314 ****************************************************************************//** 5315 * 5316 * Reports the status of the WCO_OK bit. 5317 * 5318 * \return 5319 * true = okay \n 5320 * false = not okay 5321 * 5322 * \funcusage 5323 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoOkay 5324 * 5325 *******************************************************************************/ 5326 bool Cy_SysClk_WcoOkay(void); 5327 5328 5329 /******************************************************************************* 5330 * Function Name: Cy_SysClk_WcoDisable 5331 ****************************************************************************//** 5332 * 5333 * Disables the WCO. 5334 * 5335 * \note 5336 * We need to set writable option using Cy_RTC_WriteEnable 5337 * before disabling WCO, and clear writable option after disabling WCO. 5338 * 5339 * \funcusage 5340 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoDisable 5341 * 5342 *******************************************************************************/ 5343 void Cy_SysClk_WcoDisable(void); 5344 5345 5346 #if defined (CY_IP_MXS28SRSS) 5347 /******************************************************************************* 5348 * Function Name: Cy_SysClk_WcoGainControl 5349 ****************************************************************************//** 5350 * 5351 * Sets the GM(Loop Gain Control) for WCO. 5352 * 5353 * \param gmMode \ref cy_en_wco_gain_ctrl_modes_t 5354 * 5355 * \funcusage 5356 * TBD 5357 * 5358 * \note 5359 * This API is available for CAT1B devices. 5360 * 5361 *******************************************************************************/ 5362 void Cy_SysClk_WcoGainControl(cy_en_wco_gain_ctrl_modes_t gmMode); 5363 5364 #endif /* CY_IP_MXS28SRSS */ 5365 5366 /******************************************************************************* 5367 * Function Name: Cy_SysClk_WcoBypass 5368 ****************************************************************************//** 5369 * 5370 * Sets whether the WCO is bypassed or not. If it is bypassed, then a 32-kHz clock 5371 * must be provided on the wco_out pin. 5372 * 5373 * \param bypass \ref cy_en_wco_bypass_modes_t 5374 * 5375 * \funcusage 5376 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoBypass 5377 * 5378 *******************************************************************************/ 5379 void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass); 5380 /** \} group_sysclk_wco_funcs */ 5381 5382 5383 /* ========================================================================== */ 5384 /* ============================ MF SECTION ============================ */ 5385 /* ========================================================================== */ 5386 5387 5388 /** 5389 * \addtogroup group_sysclk_clk_mf_enums 5390 * \{ 5391 */ 5392 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined(CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 5393 5394 /** 5395 * \note 5396 * This Enumeration is available for CAT1B devices. 5397 **/ 5398 /** 5399 * Medium frequency (clkMf) input sources. See CLK_MF_SELECT register, MFCLK_SEL bits. 5400 * Used with functions \ref Cy_SysClk_ClkMfSetSource, and \ref Cy_SysClk_ClkMfGetSource. 5401 */ 5402 #if defined(CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 5403 5404 typedef enum 5405 { 5406 CY_SYSCLK_CLKMF_IN_IMO = 0U, /**< clkMf is sourced by the internal low speed oscillator (IMO) */ 5407 CY_SYSCLK_CLKMF_IN_ILO = 1U, /**< clkMf is sourced by the internal low speed oscillator (ILO) */ 5408 CY_SYSCLK_CLKMF_IN_WCO = 2U, /**< clkMf is sourced by the watch crystal oscillator (WCO) */ 5409 CY_SYSCLK_CLKMF_IN_ALTLF = 3U, /**< clkMf is sourced by the Alternate Low Frequency Clock (ALTLF) */ 5410 CY_SYSCLK_CLKMF_IN_PILO = 4U, /**< clkMf is sourced by the precision low speed oscillator (PILO) */ 5411 CY_SYSCLK_CLKMF_IN_ECO_PRESCALER = 5U, /**< clkMf is sourced by the External Clock Oscillator (ECO Prescaler) */ 5412 CY_SYSCLK_CLKMF_IN_IHO = 6U, /**< clkMf is sourced by the internal high speed oscillator (IHO) */ 5413 } cy_en_clkmf_in_sources_t; 5414 5415 #else 5416 5417 typedef enum 5418 { 5419 CY_SYSCLK_CLKMF_IN_MFO = 0U, /**< clkMf is sourced by the internal low speed oscillator (MFO) */ 5420 CY_SYSCLK_CLKMF_IN_ILO = 1U, /**< clkMf is sourced by the internal low speed oscillator (ILO) */ 5421 CY_SYSCLK_CLKMF_IN_WCO = 2U, /**< clkMf is sourced by the watch crystal oscillator (WCO) */ 5422 CY_SYSCLK_CLKMF_IN_ALTLF = 3U, /**< clkMf is sourced by the Alternate Low Frequency Clock (ALTLF) */ 5423 CY_SYSCLK_CLKMF_IN_PILO = 4U, /**< clkMf is sourced by the precision low speed oscillator (PILO) */ 5424 CY_SYSCLK_CLKMF_IN_ILO1 = 5U, /**< clkMf is sourced by the precision low speed oscillator (ILO1) */ 5425 CY_SYSCLK_CLKMF_IN_ECO_PRESCALER = 6U, /**< clkMf is sourced by the External Clock Oscillator (ECO Prescaler) */ 5426 CY_SYSCLK_CLKMF_IN_LPECO = 7U, /**< clkMf is sourced by the External Clock Oscillator (LPECO) */ 5427 } cy_en_clkmf_in_sources_t; 5428 5429 #endif 5430 5431 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined (CY_DOXYGEN) */ 5432 5433 /** \} group_sysclk_clk_mf_enums */ 5434 5435 /** 5436 * \addtogroup group_sysclk_mf_funcs 5437 * \{ 5438 */ 5439 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) 5440 5441 /******************************************************************************* 5442 * Function Name: Cy_SysClk_MfoEnable 5443 ****************************************************************************//** 5444 * 5445 * Enables the MFO. 5446 * 5447 * \param deepSleepEnable enables MFO operation is Deep Sleep low power mode. 5448 * 5449 * \funcusage 5450 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5451 * 5452 *******************************************************************************/ 5453 void Cy_SysClk_MfoEnable(bool deepSleepEnable); 5454 5455 5456 /******************************************************************************* 5457 * Function Name: Cy_SysClk_MfoIsEnabled 5458 ****************************************************************************//** 5459 * 5460 * Reports whether MFO is enabled or not. 5461 * 5462 * \return 5463 * false - disabled \n 5464 * true - enabled 5465 * 5466 * \funcusage 5467 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable 5468 * 5469 *******************************************************************************/ 5470 bool Cy_SysClk_MfoIsEnabled(void); 5471 5472 5473 /******************************************************************************* 5474 * Function Name: Cy_SysClk_MfoDisable 5475 ****************************************************************************//** 5476 * 5477 * Disables the MFO. 5478 * 5479 * \funcusage 5480 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable 5481 * 5482 *******************************************************************************/ 5483 void Cy_SysClk_MfoDisable(void); 5484 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) */ 5485 5486 /** \cond internal */ 5487 #define CY_SYSCLK_MF_DIVIDER_MIN (1U) 5488 #define CY_SYSCLK_MF_DIVIDER_MAX (256U) 5489 #define CY_SYSCLK_IS_MF_DIVIDER_VALID(locDiv) ((CY_SYSCLK_MF_DIVIDER_MIN <= (locDiv)) && ((locDiv) <= CY_SYSCLK_MF_DIVIDER_MAX)) 5490 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) 5491 /** 5492 * \note 5493 * This macro is available for CAT1B devices. 5494 **/ 5495 5496 #define CY_SYSCLK_IF_MF_SOURCE_VALID(mfClkSrc) (((mfClkSrc) == CY_SYSCLK_CLKMF_IN_MFO) || \ 5497 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_ILO) || \ 5498 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_WCO) || \ 5499 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_ALTLF) || \ 5500 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_PILO) || \ 5501 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_ILO1) || \ 5502 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_ECO_PRESCALER)) 5503 5504 #endif 5505 /** \endcond */ 5506 5507 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) 5508 /******************************************************************************* 5509 * Function Name: Cy_SysClk_ClkMfEnable 5510 ****************************************************************************//** 5511 * 5512 * Enables the CLK_MF. 5513 * 5514 * \funcusage 5515 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5516 * 5517 *******************************************************************************/ 5518 void Cy_SysClk_ClkMfEnable(void); 5519 5520 5521 /******************************************************************************* 5522 * Function Name: Cy_SysClk_ClkMfIsEnabled 5523 ****************************************************************************//** 5524 * 5525 * Reports whether CLK_MF is enabled or not. 5526 * 5527 * \return 5528 * false - disabled \n 5529 * true - enabled 5530 * 5531 * \note 5532 * This API is available for CAT1A and CAT1B devices. 5533 * 5534 * \funcusage 5535 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5536 * 5537 *******************************************************************************/ 5538 bool Cy_SysClk_ClkMfIsEnabled(void); 5539 5540 5541 /******************************************************************************* 5542 * Function Name: Cy_SysClk_ClkMfDisable 5543 ****************************************************************************//** 5544 * 5545 * Disables the CLK_MF. 5546 * 5547 * \note 5548 * This API is available for CAT1A and CAT1B devices. 5549 * 5550 * \funcusage 5551 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable 5552 * 5553 *******************************************************************************/ 5554 void Cy_SysClk_ClkMfDisable(void); 5555 5556 5557 /******************************************************************************* 5558 * Function Name: Cy_SysClk_ClkMfSetDivider 5559 ****************************************************************************//** 5560 * 5561 * Sets the clock divider for CLK_MF. 5562 * 5563 * \pre If the CLK_MF is already enabled - it should be disabled 5564 * prior to use this function by \ref Cy_SysClk_ClkMfDisable. 5565 * 5566 * \param divider divider value between 1 and 256. 5567 * 5568 * \note 5569 * This API is available for CAT1A and CAT1B devices. 5570 * 5571 * \funcusage 5572 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5573 * 5574 *******************************************************************************/ 5575 void Cy_SysClk_ClkMfSetDivider(uint32_t divider); 5576 5577 5578 /******************************************************************************* 5579 * Function Name: Cy_SysClk_ClkMfGetDivider 5580 ****************************************************************************//** 5581 * 5582 * Returns the clock divider of CLK_MF. 5583 * 5584 * \return divider value in range 1..256. 5585 * 5586 * \note 5587 * This API is available for CAT1A and CAT1B devices. 5588 * 5589 * \funcusage 5590 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5591 * 5592 *******************************************************************************/ 5593 uint32_t Cy_SysClk_ClkMfGetDivider(void); 5594 5595 5596 /******************************************************************************* 5597 * Function Name: Cy_SysClk_ClkMfGetFrequency 5598 ****************************************************************************//** 5599 * 5600 * Reports the output clock signal frequency of CLK_MF. 5601 * 5602 * \return The frequency, in Hz. 5603 * 5604 * \note 5605 * This API is available for CAT1A and CAT1B devices. 5606 * 5607 * \funcusage 5608 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5609 * 5610 *******************************************************************************/ 5611 uint32_t Cy_SysClk_ClkMfGetFrequency(void); 5612 5613 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) */ 5614 5615 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined (CY_DOXYGEN) 5616 5617 /******************************************************************************* 5618 * Function Name: Cy_SysClk_ClkMfSetSource 5619 ****************************************************************************//** 5620 * 5621 * Sets the source for the Medium frequency clock(clkMf). 5622 * 5623 * \param source \ref cy_en_clkmf_in_sources_t 5624 * 5625 * \note 5626 * This API is available for CAT1B devices. 5627 * 5628 *******************************************************************************/ 5629 void Cy_SysClk_ClkMfSetSource(cy_en_clkmf_in_sources_t source); 5630 5631 5632 /******************************************************************************* 5633 * Function Name: Cy_SysClk_ClkMfGetSource 5634 ****************************************************************************//** 5635 * 5636 * Reports the source for the Medium frequency clock (clkMf). 5637 * 5638 * \return \ref cy_en_clkmf_in_sources_t 5639 * 5640 * \note 5641 * This API is available for CAT1B devices. 5642 * 5643 *******************************************************************************/ 5644 cy_en_clkmf_in_sources_t Cy_SysClk_ClkMfGetSource(void); 5645 5646 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) */ 5647 5648 /** \} group_sysclk_mf_funcs */ 5649 5650 /* ========================================================================== */ 5651 /* ========================= clkHf[n] SECTION ========================= */ 5652 /* ========================================================================== */ 5653 /** 5654 * \addtogroup group_sysclk_clk_hf_enums 5655 * \{ 5656 */ 5657 /** 5658 * Selects which clkHf input, or root mux, to configure. 5659 * See CLK_ROOT_SELECT registers, bits ROOT_MUX. 5660 * Used with functions \ref Cy_SysClk_ClkHfSetSource and \ref Cy_SysClk_ClkHfGetSource. 5661 */ 5662 typedef enum 5663 { 5664 CY_SYSCLK_CLKHF_IN_CLKPATH0 = 0U, /**< clkHf input is Clock Path 0 */ 5665 CY_SYSCLK_CLKHF_IN_CLKPATH1 = 1U, /**< clkHf input is Clock Path 1 */ 5666 CY_SYSCLK_CLKHF_IN_CLKPATH2 = 2U, /**< clkHf input is Clock Path 2 */ 5667 CY_SYSCLK_CLKHF_IN_CLKPATH3 = 3U, /**< clkHf input is Clock Path 3 */ 5668 CY_SYSCLK_CLKHF_IN_CLKPATH4 = 4U, /**< clkHf input is Clock Path 4 */ 5669 CY_SYSCLK_CLKHF_IN_CLKPATH5 = 5U, /**< clkHf input is Clock Path 5 */ 5670 CY_SYSCLK_CLKHF_IN_CLKPATH6 = 6U, /**< clkHf input is Clock Path 6 */ 5671 CY_SYSCLK_CLKHF_IN_CLKPATH7 = 7U, /**< clkHf input is Clock Path 7 */ 5672 CY_SYSCLK_CLKHF_IN_CLKPATH8 = 8U, /**< clkHf input is Clock Path 8 */ 5673 CY_SYSCLK_CLKHF_IN_CLKPATH9 = 9U, /**< clkHf input is Clock Path 9 */ 5674 CY_SYSCLK_CLKHF_IN_CLKPATH10 = 10U, /**< clkHf input is Clock Path 10 */ 5675 CY_SYSCLK_CLKHF_IN_CLKPATH11 = 11U, /**< clkHf input is Clock Path 11 */ 5676 CY_SYSCLK_CLKHF_IN_CLKPATH12 = 12U, /**< clkHf input is Clock Path 12 */ 5677 CY_SYSCLK_CLKHF_IN_CLKPATH13 = 13U, /**< clkHf input is Clock Path 13 */ 5678 CY_SYSCLK_CLKHF_IN_CLKPATH14 = 14U, /**< clkHf input is Clock Path 14 */ 5679 CY_SYSCLK_CLKHF_IN_CLKPATH15 = 15U, /**< clkHf input is Clock Path 15 */ 5680 } cy_en_clkhf_in_sources_t; 5681 5682 #if defined (CY_IP_MXS28SRSS) 5683 /** 5684 * clkHf clock supervisor input sources. See register CLK_CSV_HF_CTL[CSV_MUX]. 5685 */ 5686 /** 5687 * \note 5688 * This enum is available for CAT1B devices. 5689 **/ 5690 typedef enum 5691 { 5692 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0U, /**< Supervising clock is the IMO */ 5693 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1U, /**< Supervising clock is the external clock */ 5694 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2U /**< Supervising clock is clk_althf */ 5695 } cy_en_clkhf_csv_supervisor_clock_t; 5696 #endif /* CY_IP_MXS28SRSS */ 5697 5698 /** \} group_sysclk_clk_hf_enums */ 5699 5700 /** 5701 * \addtogroup group_sysclk_clk_hf_enums 5702 * \{ 5703 */ 5704 /** 5705 * clkHf divider values. See CLK_ROOT_SELECT registers, bits ROOT_DIV. 5706 * Used with functions \ref Cy_SysClk_ClkHfSetDivider and \ref Cy_SysClk_ClkHfGetDivider. 5707 */ 5708 #if defined (CY_IP_MXS22SRSS) || (defined (CY_MXS40SSRSS_VER_1_2) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) 5709 typedef enum 5710 { 5711 CY_SYSCLK_CLKHF_NO_DIVIDE = 0U, /**< don't divide clkHf */ 5712 CY_SYSCLK_CLKHF_DIVIDE_BY_2 = 1U, /**< divide clkHf by 2 */ 5713 CY_SYSCLK_CLKHF_DIVIDE_BY_3 = 2U, /**< divide clkHf by 3 */ 5714 CY_SYSCLK_CLKHF_DIVIDE_BY_4 = 3U, /**< divide clkHf by 4 */ 5715 CY_SYSCLK_CLKHF_DIVIDE_BY_5 = 4U, /**< divide clkHf by 5 */ 5716 CY_SYSCLK_CLKHF_DIVIDE_BY_6 = 5U, /**< divide clkHf by 6 */ 5717 CY_SYSCLK_CLKHF_DIVIDE_BY_7 = 6U, /**< divide clkHf by 7 */ 5718 CY_SYSCLK_CLKHF_DIVIDE_BY_8 = 7U, /**< divide clkHf by 8 */ 5719 CY_SYSCLK_CLKHF_DIVIDE_BY_9 = 8U, /**< divide clkHf by 9 */ 5720 CY_SYSCLK_CLKHF_DIVIDE_BY_10 = 9U, /**< divide clkHf by 10 */ 5721 CY_SYSCLK_CLKHF_DIVIDE_BY_11 = 10U, /**< divide clkHf by 11 */ 5722 CY_SYSCLK_CLKHF_DIVIDE_BY_12 = 11U, /**< divide clkHf by 12 */ 5723 CY_SYSCLK_CLKHF_DIVIDE_BY_13 = 12U, /**< divide clkHf by 13 */ 5724 CY_SYSCLK_CLKHF_DIVIDE_BY_14 = 13U, /**< divide clkHf by 14 */ 5725 CY_SYSCLK_CLKHF_DIVIDE_BY_15 = 14U, /**< divide clkHf by 15 */ 5726 CY_SYSCLK_CLKHF_DIVIDE_BY_16 = 15U, /**< divide clkHf by 16 */ 5727 CY_SYSCLK_CLKHF_MAX_DIVIDER /**< Max divider */ 5728 } cy_en_clkhf_dividers_t; 5729 #else 5730 typedef enum 5731 { 5732 CY_SYSCLK_CLKHF_NO_DIVIDE = 0U, /**< don't divide clkHf */ 5733 CY_SYSCLK_CLKHF_DIVIDE_BY_2 = 1U, /**< divide clkHf by 2 */ 5734 CY_SYSCLK_CLKHF_DIVIDE_BY_4 = 2U, /**< divide clkHf by 4 */ 5735 CY_SYSCLK_CLKHF_DIVIDE_BY_8 = 3U, /**< divide clkHf by 8 */ 5736 CY_SYSCLK_CLKHF_MAX_DIVIDER /**< Max divider */ 5737 } cy_en_clkhf_dividers_t; 5738 #endif 5739 5740 #if defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) 5741 /** 5742 * clkhf csv reference clock input sources. See register CSV_REF_SEL 5743 */ 5744 /** 5745 * \note 5746 * This enum is available for CAT1B(PSoC C3), CAT1D devices. 5747 **/ 5748 typedef enum 5749 { 5750 CY_SYSCLK_CLKHF_CSV_REF_IMO = 0U, /**< Reference clock is the IMO */ 5751 CY_SYSCLK_CLKHF_CSV_REF_EXT = 1U, /**< Reference clock is the external clock */ 5752 CY_SYSCLK_CLKHF_CSV_REF_ECO = 2U, /**< Reference clock is ECO */ 5753 CY_SYSCLK_CLKHF_CSV_REF_ALTHF0 = 3U, /**< Reference clock is ALTHF0 */ 5754 CY_SYSCLK_CLKHF_CSV_REF_IHO = 4U, /**< Reference clock is IHO */ 5755 CY_SYSCLK_CLKHF_CSV_REF_ALTHF1 = 5U /**< Reference clock is ALTHF1 */ 5756 } cy_en_clkhf_csv_ref_clk_t; 5757 5758 /** 5759 * clkhf csv supported action when an anomaly is detected. 5760 */ 5761 /** 5762 * \note 5763 * This enum is available for CAT1B(PSoC C3), CAT1D devices. 5764 **/ 5765 typedef enum 5766 { 5767 CY_SYSCLK_CLKHF_CSV_ACTION_FAULT = 0U, /**< Generates a fault */ 5768 CY_SYSCLK_CLKHF_CSV_ACTION_RESET = 1U /**< Generates a Reset */ 5769 } cy_en_clkhf_csv_action_t; 5770 #endif /* CY_IP_MXS22SRSS, CY_IP_MXS40SSRSS && (CY_MXS40SSRSS_VER_1_2 > 0UL) */ 5771 5772 /** \} group_sysclk_clk_hf_enums */ 5773 5774 #if defined (CY_IP_MXS40SRSS) 5775 /** \cond BWC */ 5776 typedef enum 5777 { 5778 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0U, 5779 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1U, 5780 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2U 5781 } cy_en_clkhf_csv_supervisor_clock_t; 5782 5783 typedef struct 5784 { 5785 cy_en_clkhf_csv_supervisor_clock_t supervisorClock; 5786 uint16_t supervisingWindow; 5787 bool enableFrequencyFaultDetection; 5788 uint16_t frequencyLowerLimit; 5789 uint16_t frequencyUpperLimit; 5790 cy_en_csv_error_actions_t frequencyAction; 5791 bool enableLossDetection; 5792 cy_en_csv_loss_window_t lossWindow; 5793 cy_en_csv_error_actions_t lossAction; 5794 } cy_stc_clkhf_csv_config_t; 5795 5796 #if (defined (CY_DEVICE_SECURE)) 5797 /** PRA structure for Cy_SysClk_ClkHfSetSource function parameters */ 5798 typedef struct 5799 { 5800 uint32_t clkHf; /**< clkHF */ 5801 cy_en_clkhf_in_sources_t source; /**< Source */ 5802 } cy_stc_pra_clkhfsetsource_t; 5803 5804 /** PRA structure for Cy_SysClk_ClkHfSetSource function parameters */ 5805 typedef struct 5806 { 5807 uint32_t clkHf; /**< clkHF */ 5808 cy_en_clkhf_dividers_t divider; /**< divider */ 5809 } cy_stc_pra_clkhfsetdivider_t; 5810 #endif /* (defined (CY_DEVICE_SECURE)) */ 5811 5812 #define altHfFreq (cy_BleEcoClockFreqHz) 5813 /** \endcond */ 5814 #endif /* CY_IP_MXS40SRSS */ 5815 5816 5817 /** 5818 * \addtogroup group_sysclk_clk_hf_structs 5819 * \{ 5820 */ 5821 #if defined (CY_IP_MXS28SRSS) 5822 /** \cond BWC */ 5823 /** 5824 * This structure is used to configure the clock supervisor for clkHf. 5825 */ 5826 /** 5827 * \note 5828 * This structure is available for CAT1B devices. 5829 **/ 5830 typedef struct 5831 { 5832 cy_en_clkhf_csv_supervisor_clock_t supervisorClock; /**< \ref cy_en_clkhf_csv_supervisor_clock_t */ 5833 uint16_t supervisingWindow; /**< Number of supervising clock cycles */ 5834 bool enableFrequencyFaultDetection; /**< 1= enabled, 0= disabled */ 5835 uint16_t frequencyLowerLimit; /**< Lowest frequency in kHz that supervised clock can go */ 5836 uint16_t frequencyUpperLimit; /**< Highest frequency in kHz that supervised clock can go */ 5837 cy_en_csv_error_actions_t frequencyAction; /**< \ref cy_en_csv_error_actions_t */ 5838 bool enableLossDetection; /**< 1= enabled, 0= disabled */ 5839 cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */ 5840 cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */ 5841 } cy_stc_clkhf_csv_config_t; 5842 5843 /** \endcond */ 5844 #endif 5845 5846 #if defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) 5847 /** 5848 * \note 5849 * This structure is available for CAT1B(PSoC C3), CAT1D devices. 5850 **/ 5851 typedef struct 5852 { 5853 uint32_t startTime; /**< Startup delay time, after enable or DeepSleep wakeup, from reference clock start to monitored clock start. */ 5854 uint32_t lowerLimit; /**< Lower limit in reference clock cycles, before the next monitored clock event is allowed to happen. */ 5855 uint32_t upperLimit; /**< Upper limit in reference clock cycles, before (or same time) the next monitored clock event must happen. */ 5856 uint32_t period; /**< Period in monitored clock cycles, before the next monitored clock event happens. */ 5857 } cy_stc_clkhf_csv_manual_config_t; 5858 5859 /** 5860 * \note 5861 * This structure is available for CAT1B(PSoC C3), CAT1D devices. 5862 **/ 5863 typedef struct 5864 { 5865 uint32_t clkHf; /**< Configure CSV for the selected CLKHF */ 5866 cy_en_clkhf_csv_ref_clk_t refClk; /**< Reference clock */ 5867 } cy_stc_clkhf_csv_hf_config_t; 5868 #endif 5869 5870 /** \} group_sysclk_clk_hf_structs */ 5871 5872 #if defined (CY_IP_MXS28SRSS) 5873 /** \cond INTERNAL */ 5874 /** 5875 * \note 5876 * It is available for CAT1B devices. 5877 **/ 5878 extern uint32_t altHfFreq; /* Internal storage for BLE ECO frequency user setting */ 5879 /** \endcond */ 5880 #endif /* CY_IP_MXS28SRSS */ 5881 5882 /** 5883 * \addtogroup group_sysclk_clk_hf_funcs 5884 * \{ 5885 */ 5886 5887 5888 /******************************************************************************* 5889 * Function Name: Cy_SysClk_ClkHfEnable 5890 ****************************************************************************//** 5891 * 5892 * Enables the selected clkHf. 5893 * 5894 * \param clkHf Selects which clkHf to enable. 5895 * 5896 * \return \ref cy_en_sysclk_status_t 5897 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 5898 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 5899 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 5900 * uses the PRA driver to change the protected registers. Refer to 5901 * \ref cy_en_pra_status_t for more details. 5902 * 5903 * \funcusage 5904 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource 5905 * 5906 *******************************************************************************/ 5907 cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf); 5908 5909 5910 /******************************************************************************* 5911 * Function Name: Cy_SysClk_ClkHfIsEnabled 5912 ****************************************************************************//** 5913 * 5914 * Reports the Enabled/Disabled status of clkHf. 5915 * 5916 * \param clkHf Selects which clkHf to check. 5917 * 5918 * \return Boolean status of clkHf: true - Enabled, false - Disabled. 5919 * 5920 * \funcusage 5921 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable 5922 * 5923 * \note 5924 * This API is available for CAT1A devices. 5925 * 5926 *******************************************************************************/ 5927 bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf); 5928 5929 5930 /******************************************************************************* 5931 * Function Name: Cy_SysClk_ClkHfDisable 5932 ****************************************************************************//** 5933 * 5934 * Disables the selected clkHf. 5935 * 5936 * \param clkHf Selects which clkHf to enable. 5937 * 5938 * \return \ref cy_en_sysclk_status_t 5939 * 5940 * \note clkHf[0] cannot be disabled. 5941 * 5942 * \funcusage 5943 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable 5944 * 5945 *******************************************************************************/ 5946 cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf); 5947 5948 5949 /******************************************************************************* 5950 * Function Name: Cy_SysClk_ClkHfSetSource 5951 ****************************************************************************//** 5952 * 5953 * Selects the source of the selected clkHf. 5954 * 5955 * \param clkHf selects which clkHf mux to configure. 5956 * 5957 * \param source \ref cy_en_clkhf_in_sources_t 5958 * 5959 * \return \ref cy_en_sysclk_status_t 5960 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 5961 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 5962 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 5963 * uses the PRA driver to change the protected registers. Refer to 5964 * \ref cy_en_pra_status_t for more details. 5965 * 5966 * \note 5967 * Call \ref SystemCoreClockUpdate after this function calling 5968 * if it affects the CLK_HF0 frequency. 5969 * 5970 * \note 5971 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 5972 * CLK_HF0 frequency is increasing. 5973 * 5974 * \note 5975 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 5976 * CLK_HF0 frequency is decreasing. 5977 * 5978 * \funcusage 5979 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource 5980 * 5981 * \note 5982 * Take into account the possible platform specific clkHf (and further 5983 * clocking chain links) frequency limitations while using this API. 5984 * 5985 * \note It takes four cycles of the originally selected clock to switch away 5986 * from it. Do not disable the original clock during this time. 5987 * 5988 *******************************************************************************/ 5989 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source); 5990 5991 5992 /******************************************************************************* 5993 * Function Name: Cy_SysClk_ClkHfGetSource 5994 ****************************************************************************//** 5995 * 5996 * Reports the source of the selected clkHf. 5997 * 5998 * \param clkHf selects which clkHf to get the source of. 5999 * 6000 * \return \ref cy_en_clkhf_in_sources_t 6001 * 6002 * \funcusage 6003 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource 6004 * 6005 *******************************************************************************/ 6006 cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf); 6007 6008 6009 /******************************************************************************* 6010 * Function Name: Cy_SysClk_ClkHfSetDivider 6011 ****************************************************************************//** 6012 * 6013 * Sets the pre-divider for a clkHf. 6014 * 6015 * \param clkHf selects which clkHf divider to configure. 6016 * 6017 * \param divider \ref cy_en_clkhf_dividers_t 6018 * 6019 * \return \ref cy_en_sysclk_status_t 6020 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 6021 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 6022 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 6023 * uses the PRA driver to change the protected registers. Refer to 6024 * \ref cy_en_pra_status_t for more details. 6025 * 6026 * \note Also call \ref Cy_SysClk_ClkHfSetSource to set the clkHf source. 6027 * 6028 * \note 6029 * Call \ref SystemCoreClockUpdate after this function calling 6030 * if it affects the CLK_HF0 frequency. 6031 * 6032 * \note 6033 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 6034 * CLK_HF0 frequency is increasing. 6035 * 6036 * \note 6037 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 6038 * CLK_HF0 frequency is decreasing. 6039 * 6040 * \note 6041 * Take into account the possible platform specific clkHf (and further 6042 * clocking chain links) frequency limitations while using this API. 6043 * 6044 * \funcusage 6045 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider 6046 * 6047 *******************************************************************************/ 6048 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider); 6049 6050 6051 /******************************************************************************* 6052 * Function Name: Cy_SysClk_ClkHfGetDivider 6053 ****************************************************************************//** 6054 * 6055 * Reports the pre-divider value for a clkHf. 6056 * 6057 * \param clkHf selects which clkHf to check divider of. 6058 * 6059 * \return \ref cy_en_clkhf_dividers_t 6060 * 6061 * \funcusage 6062 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider 6063 * 6064 *******************************************************************************/ 6065 cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf); 6066 6067 6068 /******************************************************************************* 6069 * Function Name: Cy_SysClk_ClkHfGetFrequency 6070 ****************************************************************************//** 6071 * 6072 * Reports the frequency of the selected clkHf 6073 * 6074 * \param clkHf Selects the clkHf 6075 * 6076 * \return The frequency, in Hz. 6077 * 6078 * \note 6079 * The reported frequency may be zero, which indicates unknown. This happens if 6080 * the source input is dsi_out or clk_altlf. 6081 * 6082 * \note 6083 * Calculates the HF frequency irrespective of whether HF is enabled or not. 6084 * 6085 * \funcusage 6086 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider 6087 * 6088 *******************************************************************************/ 6089 uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf); 6090 6091 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_DOXYGEN) 6092 /******************************************************************************* 6093 * Function Name: Cy_SysClk_ClkHfDirectSel 6094 ****************************************************************************//** 6095 * 6096 * Enable/Disable the direct source selection as IMO for CLK_HF[[n]] 6097 * 6098 * \param clkHf Selects the clkHf 6099 * 6100 * \param enable True - Selects IMO for CAT1B/CAT1C or IHO for CAT1D, False - Selects Root Mux 6101 * 6102 * \return \ref cy_en_sysclk_status_t 6103 * CY_SYSCLK_BAD_PARAM - If clkhf is incorrect. 6104 * CY_SYSCLK_SUCCESS - If successfully Enabled/Disabled. 6105 * 6106 * \note 6107 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6108 * 6109 *******************************************************************************/ 6110 cy_en_sysclk_status_t Cy_SysClk_ClkHfDirectSel(uint32_t clkHf, bool enable); 6111 6112 /******************************************************************************* 6113 * Function Name: Cy_SysClk_IsClkHfDirectSelEnabled 6114 ****************************************************************************//** 6115 * 6116 * Checks if direct source selection as IMO for CLK_HF[[n]] is enabled/disabled 6117 * 6118 * \param clkHf Selects the clkHf 6119 * 6120 * \return 6121 * True - IMO selected for CAT1A/CAT1B/CAT1C or IHO for CAT1D, False - Root Mux is selected. 6122 * 6123 * \note 6124 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6125 * 6126 *******************************************************************************/ 6127 bool Cy_SysClk_IsClkHfDirectSelEnabled(uint32_t clkHf); 6128 6129 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_DOXYGEN) */ 6130 6131 #if defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 6132 /******************************************************************************* 6133 * Function Name: Cy_SysClk_ClkHfGetMaskOnPath 6134 ****************************************************************************//** 6135 * 6136 * Get Mask value for the HF Clocks selected and enabled for clkPath as source 6137 * e.g. Mask return will have Bit 0 set if HFCLK0 is enabled and source is clkPath 6138 * 6139 * \param clkPath clock path 6140 * 6141 * \return 6142 * mask of CLKHF for which clock path is set 6143 * 6144 * \note 6145 * This API is available CAT1D for LP PLL 6146 * 6147 *******************************************************************************/ 6148 uint32_t Cy_SysClk_ClkHfGetMaskOnPath(cy_en_clkhf_in_sources_t clkPath); 6149 6150 /******************************************************************************* 6151 * Function Name: Cy_SysClk_ClkHfAllGetMask 6152 ****************************************************************************//** 6153 * 6154 * Get Mask value for the all HF Clocks 6155 * e.g. Mask return will have Bit 0 set if HFCLK0 is enabled 6156 * 6157 * \return 6158 * mask of CLKHF 6159 * 6160 * \note 6161 * This API is available only for CAT1D devices 6162 * 6163 *******************************************************************************/ 6164 uint32_t Cy_SysClk_ClkHfAllGetMask(void); 6165 6166 /******************************************************************************* 6167 * Function Name: Cy_SysClk_ClkHfEnableDividerWithMask 6168 ****************************************************************************//** 6169 * 6170 * Divide all the enabled CLK_HF's with the divider value. 6171 * 6172 * \param clkHfMask CLKHF mask for of the Clocks 6173 * 6174 * \param divider Divider Value \ref cy_en_clkhf_dividers_t 6175 * 6176 * \note 6177 * This API is available for CAT1D devices 6178 * 6179 *******************************************************************************/ 6180 void Cy_SysClk_ClkHfEnableDividerWithMask(uint32_t clkHfMask, cy_en_clkhf_dividers_t divider); 6181 6182 /******************************************************************************* 6183 * Function Name: Cy_SysClk_ClkHfEnableDirectMuxWithMask 6184 ****************************************************************************//** 6185 * 6186 * Enable/ Disable the clock path for the HF Clocks in clkHfMask 6187 * in disable case ROOT path will be enabled 6188 * in enable case ROOT path will be disabled 6189 * 6190 * \param clkHfMask CLKHF mask for of the Clocks 6191 * 6192 * \param enable to enable or disable direct path 6193 * 6194 * \note 6195 * This API is available CAT1D for LP PLL, CDT_005549-196 6196 * 6197 *******************************************************************************/ 6198 void Cy_SysClk_ClkHfEnableDirectMuxWithMask(uint32_t clkHfMask, bool enable); 6199 #endif /* (defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)) */ 6200 6201 #if defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) 6202 6203 /******************************************************************************* 6204 * Function Name: Cy_SysClk_ClkHfCsvGetRefFrequency 6205 ****************************************************************************//** 6206 * 6207 * Get the clkHf csv reference clock frequency. 6208 * 6209 * \param refClk Reference clock source. 6210 * 6211 * \return \ref cy_en_sysclk_status_t. 6212 * 6213 * \note 6214 * This API is available for CAT1B(PSoC C3), CAT1D devices. 6215 * 6216 * \funcusage 6217 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfCSVConfig 6218 * 6219 *******************************************************************************/ 6220 uint32_t Cy_SysClk_ClkHfCsvGetRefFrequency(cy_en_clkhf_csv_ref_clk_t refClk); 6221 6222 6223 /******************************************************************************* 6224 * Function Name: Cy_SysClk_ClkHfCsvManualConfigure 6225 ****************************************************************************//** 6226 * 6227 * Manually configures the clkHf csv based on user inputs. 6228 * 6229 * \param hfConfig Selects the clkHf, reference clock for csv operation. 6230 * 6231 * \param csvConfig Selects the csv configuration required. 6232 * 6233 * \return The frequency in Hz. 6234 * 6235 * \note 6236 * This API is available for CAT1B(PSoC C3), CAT1D devices. 6237 * 6238 * \funcusage 6239 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfCSVConfig 6240 * 6241 *******************************************************************************/ 6242 cy_en_sysclk_status_t Cy_SysClk_ClkHfCsvManualConfigure(const cy_stc_clkhf_csv_hf_config_t * hfConfig, const cy_stc_clkhf_csv_manual_config_t * csvConfig); 6243 6244 6245 /******************************************************************************* 6246 * Function Name: Cy_SysClk_ClkHfCsvConfigure 6247 ****************************************************************************//** 6248 * 6249 * Configures clkhf csv. 6250 * 6251 * The configuration formula used is: 6252 * Lower_limit = Target - Required accuracy/2 6253 * Upper_limit = Target + Required accuracy/2 6254 * Period = Target / (Reference frequency / Monitor frequency) 6255 * Start_time = (Period +3) * (Reference frequency / Monitor frequency) - Upper_limit 6256 * 6257 * \param hfConfig Selects the clkHf, reference clock for csv operation. 6258 * 6259 * \param accuracy Required accuracy. 6260 * 6261 * \return \ref cy_en_sysclk_status_t. 6262 * 6263 * \note 6264 * This API is available for CAT1B(PSoC C3), CAT1D devices. 6265 * 6266 * \funcusage 6267 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfCSVConfig 6268 * 6269 *******************************************************************************/ 6270 cy_en_sysclk_status_t Cy_SysClk_ClkHfCsvConfigure(const cy_stc_clkhf_csv_hf_config_t * hfConfig, uint32_t accuracy); 6271 6272 6273 /******************************************************************************* 6274 * Function Name: Cy_SysClk_ClkHfCsvAction 6275 ****************************************************************************//** 6276 * 6277 * Configures the action taken when an anomaly is detected on the clkHf. 6278 * 6279 * \param clkHf Selects the clkHf. 6280 * 6281 * \param action Action to be taken when anomaly is detected \ref cy_en_clkhf_csv_action_t 6282 * 6283 * \note 6284 * This API is available for CAT1B(PSoC C3), CAT1D devices. 6285 * 6286 * \funcusage 6287 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfCSVConfig 6288 * 6289 *******************************************************************************/ 6290 void Cy_SysClk_ClkHfCsvAction(uint32_t clkHf, cy_en_clkhf_csv_action_t action); 6291 6292 6293 /******************************************************************************* 6294 * Function Name: Cy_SysClk_ClkHfCsvEnable 6295 ****************************************************************************//** 6296 * 6297 * Enables the csv for the provided clkHf. 6298 * 6299 * \param clkHf Selects the clkHf. 6300 * 6301 * \note 6302 * This API is available for CAT1B(PSoC C3), CAT1D devices. 6303 * 6304 * \funcusage 6305 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfCSVConfig 6306 * 6307 *******************************************************************************/ 6308 void Cy_SysClk_ClkHfCsvEnable(uint32_t clkHf); 6309 6310 6311 /******************************************************************************* 6312 * Function Name: Cy_SysClk_ClkHfCsvDisable 6313 ****************************************************************************//** 6314 * 6315 * Disables the csv for the provided clkHf. 6316 * 6317 * \param clkHf Selects the clkHf. 6318 * 6319 * \note 6320 * This API is available for CAT1B(PSoC C3), CAT1D devices. 6321 * 6322 * \funcusage 6323 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfCSVConfig 6324 * 6325 *******************************************************************************/ 6326 void Cy_SysClk_ClkHfCsvDisable(uint32_t clkHf); 6327 6328 6329 /******************************************************************************* 6330 * Function Name: Cy_SysClk_IsClkHfCsvEnabled 6331 ****************************************************************************//** 6332 * 6333 * Returns the enabled status of csv for the provided clkHf. 6334 * 6335 * \param clkHf Selects the clkHf. 6336 * 6337 * \return \ref cy_en_sysclk_status_t. 6338 * 6339 * \note 6340 * This API is available for CAT1B(PSoC C3), CAT1D devices. 6341 * 6342 * \funcusage 6343 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfCSVConfig 6344 * 6345 *******************************************************************************/ 6346 bool Cy_SysClk_IsClkHfCsvEnabled(uint32_t clkHf); 6347 6348 #endif 6349 6350 /** \} group_sysclk_clk_hf_funcs */ 6351 6352 6353 /* ========================================================================== */ 6354 /* ========================= clk_fast SECTION ========================= */ 6355 /* ========================================================================== */ 6356 /** 6357 * \addtogroup group_sysclk_clk_fast_funcs 6358 * \{ 6359 */ 6360 6361 #if (defined (CY_IP_MXS40SRSS) && defined (CY_IP_M4CPUSS)) || defined (CY_DOXYGEN) 6362 6363 /******************************************************************************* 6364 * Function Name: Cy_SysClk_ClkFastSetDivider 6365 ****************************************************************************//** 6366 * 6367 * Sets the clock divider for the fast clock, which sources the main processor. 6368 * The source of this divider is clkHf[0]. 6369 * 6370 * \param divider divider value between 0 and 255. 6371 * Causes integer division of (divider value + 1), or division by 1 to 256. 6372 * 6373 * \note 6374 * Call \ref SystemCoreClockUpdate after this function calling. 6375 * 6376 * \note 6377 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 6378 * CLK_FAST frequency is increasing. 6379 * 6380 * \note 6381 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 6382 * CLK_FAST frequency is decreasing. 6383 * 6384 * \note 6385 * This API is available only for CAT1A devices. 6386 * 6387 * \funcusage 6388 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider 6389 * 6390 *******************************************************************************/ 6391 void Cy_SysClk_ClkFastSetDivider(uint8_t divider); 6392 6393 6394 /******************************************************************************* 6395 * Function Name: Cy_SysClk_ClkFastGetDivider 6396 ****************************************************************************//** 6397 * 6398 * Returns the clock divider for the fast clock. 6399 * 6400 * \return The divider value for the fast clock. 6401 * The integer division done is by (divider value + 1), or division by 1 to 256. 6402 * 6403 * \note 6404 * This API is available only for CAT1A devices. 6405 * 6406 * \funcusage 6407 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider 6408 * 6409 *******************************************************************************/ 6410 uint8_t Cy_SysClk_ClkFastGetDivider(void); 6411 6412 6413 /******************************************************************************* 6414 * Function Name: Cy_SysClk_ClkFastGetFrequency 6415 ****************************************************************************//** 6416 * 6417 * Reports the frequency of the fast clock. 6418 * 6419 * \return The frequency, in Hz. 6420 * 6421 * \note 6422 * This API is available only for CAT1A devices. 6423 * 6424 * \funcusage 6425 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider 6426 * 6427 *******************************************************************************/ 6428 uint32_t Cy_SysClk_ClkFastGetFrequency(void); 6429 6430 #endif /* (defined (CY_IP_MXS40SRSS) && defined (CY_IP_M4CPUSS)) || defined (CY_DOXYGEN) */ 6431 6432 #if (defined (CY_IP_MXS40SRSS) && defined (CY_IP_M7CPUSS)) || defined (CY_DOXYGEN) 6433 6434 /******************************************************************************* 6435 * Function Name: Cy_SysClk_ClkFastSrcSetDivider 6436 ****************************************************************************//** 6437 * 6438 * Sets the clock divider for the fast clock, which sources the main processor. 6439 * The source of this divider is clkHf[0]. 6440 * 6441 * \param clkFastNum 0 for CLOCK_FAST_0 and 1 for CLOCK_FAST_1 6442 * 6443 * \param intDiv Integer divider 6444 * 6445 * \param fracDiv Fractional divider 6446 * 6447 * \note 6448 * Call \ref SystemCoreClockUpdate after this function calling. 6449 * 6450 * \note 6451 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 6452 * CLK_FAST frequency is increasing. 6453 * 6454 * \note 6455 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 6456 * CLK_FAST frequency is decreasing. 6457 * 6458 * \note 6459 * This API is available only for CAT1C devices. 6460 * 6461 *******************************************************************************/ 6462 void Cy_SysClk_ClkFastSrcSetDivider(uint32_t clkFastNum, uint8_t intDiv, uint8_t fracDiv); 6463 6464 6465 /******************************************************************************* 6466 * Function Name: Cy_SysClk_ClkFastSrcGetDivider 6467 ****************************************************************************//** 6468 * 6469 * Returns the Integer and Fractional clock divider for the fast clock. 6470 * 6471 * \param clkFastNum 0 for CLOCK_FAST_0 and 1 for CLOCK_FAST_1 6472 * 6473 * \param dividerIntValue - Integer divider 6474 * 6475 * \param dividerFracValue - Fractional divider 6476 * 6477 * \return None. Loads pointed-to variables. 6478 * 6479 * \note 6480 * This API is available only for CAT1C devices. 6481 * 6482 *******************************************************************************/ 6483 void Cy_SysClk_ClkFastSrcGetDivider(uint32_t clkFastNum, uint32_t *dividerIntValue, uint32_t *dividerFracValue); 6484 6485 6486 /******************************************************************************* 6487 * Function Name: Cy_SysClk_ClkFastSrcGetFrequency 6488 ****************************************************************************//** 6489 * 6490 * Reports the frequency of the fast clock. 6491 * 6492 * \param clkFastNum 0 for CLOCK_FAST_0 and 1 for CLOCK_FAST_1 6493 * 6494 * \return The frequency, in Hz. 6495 * 6496 * \note 6497 * This API is available only for CAT1C devices. 6498 * 6499 *******************************************************************************/ 6500 uint32_t Cy_SysClk_ClkFastSrcGetFrequency(uint32_t clkFastNum); 6501 6502 #endif /* (defined (CY_IP_MXS40SRSS) && defined (CY_IP_M7CPUSS)) || defined (CY_DOXYGEN) */ 6503 6504 /** \} group_sysclk_clk_fast_funcs */ 6505 6506 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXPERI_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) 6507 6508 /* ========================================================================== */ 6509 /* ======================== PERI SECTION ========================== */ 6510 /* ========================================================================== */ 6511 6512 /** 6513 * \addtogroup group_sysclk_clk_peripheral_group_enums 6514 * \{ 6515 */ 6516 /** 6517 * Slave control Register Numbers 6518 * Used with functions \ref Cy_SysClk_ClkHfSetDivider and \ref Cy_SysClk_ClkHfGetDivider. 6519 */ 6520 typedef enum 6521 { 6522 CY_SYSCLK_PERI_GROUP_SL_CTL = 0U, /**<Selects SL_CTL*/ 6523 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) 6524 CY_SYSCLK_PERI_GROUP_SL_CTL2 = 1U, /**<Selects SL_CTL2*/ 6525 CY_SYSCLK_PERI_GROUP_SL_CTL3 = 2U, /**<Selects SL_CTL3*/ 6526 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) */ 6527 } cy_en_peri_grp_sl_ctl_num_t; 6528 6529 /** \} group_sysclk_clk_peripheral_group_enums */ 6530 6531 /** \cond internal */ 6532 /* Macro to validate if the SL control register number passed */ 6533 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) 6534 #define CY_SYSCLK_IS_SL_CTL_NUM_VALID(slaveCtl) (((slaveCtl) == CY_SYSCLK_PERI_GROUP_SL_CTL) || \ 6535 ((slaveCtl) == CY_SYSCLK_PERI_GROUP_SL_CTL2) || \ 6536 ((slaveCtl) == CY_SYSCLK_PERI_GROUP_SL_CTL3)) 6537 #else 6538 #define CY_SYSCLK_IS_SL_CTL_NUM_VALID(slaveCtl) (((slaveCtl) == CY_SYSCLK_PERI_GROUP_SL_CTL)) 6539 6540 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) */ 6541 6542 /** \endcond */ 6543 6544 6545 /** 6546 * \addtogroup group_sysclk_clk_peripheral_group_funcs 6547 * \{ 6548 */ 6549 /******************************************************************************* 6550 * Function Name: Cy_SysClk_PeriGroupSetDivider 6551 ****************************************************************************//** 6552 * 6553 * Sets the divider value for a particular group 6554 * 6555 * \return \ref cy_en_sysclk_status_t 6556 * 6557 * \param groupNum Selects the PERI Group Number 6558 * \note 6559 * Input of groupNum parameter will be 6560 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 6561 * /include/\<series\>_config.h) 6562 * CAT1B/CAT1C - group number 6563 * 6564 * \param divider Selects the divider value 6565 * 6566 * \note 6567 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6568 * 6569 * \note 6570 * Clock divider functionality is product specific, Refer to TRM before using this API 6571 * Example:- 6572 * For CAT1B devices Group-0 does not have the clock divider functionality. 6573 * For CAT1C devices Group-0,1 and 2 does not have the clock divider functionality. 6574 * For the above not supported groups this API will return success, but write will 6575 * not happen. 6576 * 6577 *******************************************************************************/ 6578 cy_en_sysclk_status_t Cy_SysClk_PeriGroupSetDivider(uint32_t groupNum, uint32_t divider); 6579 6580 6581 /******************************************************************************* 6582 * Function Name: Cy_SysClk_PeriGroupGetDivider 6583 ****************************************************************************//** 6584 * 6585 * Gets the divider value for a particular group 6586 * 6587 * \return Divider value 6588 * 6589 * \param groupNum Selects the PERI Group Number 6590 * \note 6591 * Input of groupNum parameter will be 6592 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 6593 * /include/\<series\>_config.h) 6594 * CAT1B/CAT1C - group number 6595 * 6596 * \note 6597 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6598 * 6599 * \note 6600 * Clock divider functionality is product specific, Refer to TRM before using this API 6601 * Example:- 6602 * For CAT1B devices Group-0 does not have the clock divider functionality. 6603 * For CAT1C devices Group-0,1 and 2 does not have the clock divider functionality. 6604 * For the above not supported groups this API returns zero. 6605 * 6606 *******************************************************************************/ 6607 uint32_t Cy_SysClk_PeriGroupGetDivider(uint32_t groupNum); 6608 6609 6610 /******************************************************************************* 6611 * Function Name: Cy_SysClk_PeriGroupSetSlaveCtl 6612 ****************************************************************************//** 6613 * 6614 * Sets the particular Slave Control value for a particular group 6615 * 6616 * \return \ref cy_en_sysclk_status_t 6617 * 6618 * \param groupNum Selects the PERI Group Number 6619 * \note 6620 * Input of groupNum parameter will be 6621 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 6622 * /include/\<series\>_config.h) 6623 * CAT1B/CAT1C - group number 6624 * 6625 * \param slaveCtl Selects the Slave Control Register Number 6626 * 6627 * \param value Value to be written 6628 * 6629 * \note 6630 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6631 * 6632 *******************************************************************************/ 6633 cy_en_sysclk_status_t Cy_SysClk_PeriGroupSetSlaveCtl(uint32_t groupNum, cy_en_peri_grp_sl_ctl_num_t slaveCtl, uint32_t value); 6634 6635 /******************************************************************************* 6636 * Function Name: Cy_SysClk_PeriGroupGetSlaveCtl 6637 ****************************************************************************//** 6638 * 6639 * Gets the particular Slave Control value for a particular group 6640 * 6641 * \return Slave Control register value for a particular group 6642 * 6643 * \param groupNum Selects the PERI Group Number 6644 * \note 6645 * Input of groupNum parameter will be 6646 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 6647 * /include/\<series\>_config.h) 6648 * CAT1B/CAT1C - group number 6649 * 6650 * \param slaveCtl Selects the Slave Control Register Number 6651 * 6652 * \note 6653 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6654 * 6655 *******************************************************************************/ 6656 uint32_t Cy_SysClk_PeriGroupGetSlaveCtl(uint32_t groupNum, cy_en_peri_grp_sl_ctl_num_t slaveCtl); 6657 6658 /******************************************************************************* 6659 * Function Name: Cy_SysClk_IsPeriGroupSlaveCtlSet 6660 ****************************************************************************//** 6661 * 6662 * Gets the mask value of particular slave control register for a particular group 6663 * 6664 * \return Divider value 6665 * 6666 * \param groupNum Selects the PERI Group Number 6667 * \note 6668 * Input of groupNum parameter will be 6669 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 6670 * /include/\<series\>_config.h) 6671 * CAT1B/CAT1C - group number 6672 * 6673 * \param slaveCtl Selects the Slave Control Register Number 6674 * 6675 * \param slaveMsk Selects the bit position(s) that needs to be obtained 6676 * 6677 * \note 6678 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6679 * 6680 *******************************************************************************/ 6681 bool Cy_SysClk_IsPeriGroupSlaveCtlSet(uint32_t groupNum,cy_en_peri_grp_sl_ctl_num_t slaveCtl, uint32_t slaveMsk); 6682 6683 #if defined (CY_IP_MXS22SRSS) 6684 /******************************************************************************* 6685 * Function Name: Cy_SysClk_PeriGroupSlaveInit 6686 ****************************************************************************//** 6687 * 6688 * Initializes an IP 6689 * 6690 * \param periNum Selects the PERI Number 6691 * 6692 * \param groupNum Selects the PERI Group Number 6693 * \note 6694 * Input of groupNum parameter will be 6695 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1D 6696 * /include/\<series\>_config.h) 6697 * 6698 * \param slaveNum Selects the bit position of the IP that needs to be enabled 6699 * 6700 * \param clkHfNum Selects the CLK_HF number that needs to be enabled for 6701 * the IP to get enabled. 6702 * 6703 * \note 6704 * This API is available only for CAT1D devices. 6705 * 6706 *******************************************************************************/ 6707 void Cy_SysClk_PeriGroupSlaveInit(uint32_t periNum, uint32_t groupNum, uint32_t slaveNum, uint32_t clkHfNum); 6708 6709 /******************************************************************************* 6710 * Function Name: Cy_SysClk_PeriGroupSlaveDeinit 6711 ****************************************************************************//** 6712 * 6713 * Deinitializes an IP 6714 * 6715 * \param periNum Selects the PERI Number 6716 * 6717 * \param groupNum Selects the PERI Group Number 6718 * \note 6719 * Input of groupNum parameter will be 6720 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1D 6721 * /include/\<series\>_config.h) 6722 * 6723 * \param slaveNum Selects the bit position of the IP that needs to be disabled 6724 * 6725 * \note 6726 * This API is available only for CAT1D devices. 6727 * 6728 *******************************************************************************/ 6729 void Cy_SysClk_PeriGroupSlaveDeinit(uint32_t periNum, uint32_t groupNum, uint32_t slaveNum); 6730 6731 #endif /* defined (CY_IP_MXS22SRSS) */ 6732 6733 /** \} group_sysclk_clk_peripheral_group_funcs */ 6734 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXPERI_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) */ 6735 6736 /* ========================================================================== */ 6737 /* ======================== clk_peri SECTION ========================== */ 6738 /* ========================================================================== */ 6739 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SRSS) 6740 6741 /** 6742 * \addtogroup group_sysclk_clk_peri_funcs 6743 * \{ 6744 */ 6745 6746 6747 /******************************************************************************* 6748 * Function Name: Cy_SysClk_ClkPeriSetDivider 6749 ****************************************************************************//** 6750 * 6751 * Sets the clock divider for the peripheral clock tree. All peripheral clock 6752 * dividers are sourced from this clock. Also the Cortex M0+ clock divider is 6753 * sourced from this clock. The source of this divider is clkHf[0] 6754 * 6755 * \param divider divider value between 0 and 255 6756 * Causes integer division of (divider value + 1), or division by 1 to 256. 6757 * 6758 * \note 6759 * Call \ref SystemCoreClockUpdate after this function calling. 6760 * 6761 * \note 6762 * This API is available for CAT1A & CAT1C devices. 6763 * 6764 * \funcusage 6765 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider 6766 * 6767 *******************************************************************************/ 6768 void Cy_SysClk_ClkPeriSetDivider(uint8_t divider); 6769 6770 6771 /******************************************************************************* 6772 * Function Name: Cy_SysClk_ClkPeriGetFrequency 6773 ****************************************************************************//** 6774 * 6775 * Reports the frequency of the peri clock. 6776 * 6777 * \return The frequency, in Hz. 6778 * 6779 * \note 6780 * This API is available for CAT1A & CAT1C devices. 6781 * 6782 * \funcusage 6783 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider 6784 * 6785 *******************************************************************************/ 6786 uint32_t Cy_SysClk_ClkPeriGetFrequency(void); 6787 6788 6789 /******************************************************************************* 6790 * Function Name: Cy_SysClk_ClkPeriGetDivider 6791 ****************************************************************************//** 6792 * 6793 * Returns the clock divider of the peripheral (peri) clock. 6794 * 6795 * \return The divider value. 6796 * The integer division done is by (divider value + 1), or division by 1 to 256. 6797 * 6798 * \note 6799 * This API is available for CAT1A & CAT1C devices. 6800 * 6801 * \funcusage 6802 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider 6803 * 6804 *******************************************************************************/ 6805 uint8_t Cy_SysClk_ClkPeriGetDivider(void); 6806 /** \} group_sysclk_clk_peri_funcs */ 6807 6808 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SRSS) */ 6809 6810 /* ========================================================================== */ 6811 /* ===================== clk_peripherals SECTION ====================== */ 6812 /* ========================================================================== */ 6813 /** 6814 * \addtogroup group_sysclk_clk_peripheral_enums 6815 * \{ 6816 */ 6817 /** Programmable clock divider types */ 6818 typedef enum 6819 { 6820 CY_SYSCLK_DIV_8_BIT = 0U, /**< Divider Type is an 8 bit divider */ 6821 CY_SYSCLK_DIV_16_BIT = 1U, /**< Divider Type is a 16 bit divider */ 6822 CY_SYSCLK_DIV_16_5_BIT = 2U, /**< Divider Type is a 16.5 bit fractional divider */ 6823 CY_SYSCLK_DIV_24_5_BIT = 3U /**< Divider Type is a 24.5 bit fractional divider */ 6824 } cy_en_divider_types_t; 6825 /** \} group_sysclk_clk_peripheral_enums */ 6826 6827 6828 /** 6829 * \addtogroup group_sysclk_clk_peripheral_funcs 6830 * \{ 6831 */ 6832 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) || defined (CY_IP_MXS22SRSS) 6833 6834 /******************************************************************************* 6835 * Function Name: Cy_SysClk_PeriPclkSetDivider 6836 ****************************************************************************//** 6837 * 6838 * Sets one of the programmable clock dividers. This is only used for integer 6839 * dividers. Use \ref Cy_SysClk_PeriphSetFracDivider for setting factional dividers. 6840 * 6841 * \pre If the specified clock divider is already enabled - it should be disabled 6842 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 6843 * 6844 * \param ipBlock specifies ip block to connect the clock divider to. 6845 * 6846 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6847 * 6848 * \param dividerNum the divider number. 6849 * 6850 * \param dividerValue divider value 6851 * Causes integer division of (divider value + 1), or division by 1 to 256 6852 * (8-bit divider) or 1 to 65536 (16-bit divider). 6853 * 6854 * \return \ref cy_en_sysclk_status_t 6855 * 6856 * \note 6857 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6858 * 6859 *******************************************************************************/ 6860 cy_en_sysclk_status_t 6861 Cy_SysClk_PeriPclkSetDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, 6862 uint32_t dividerNum, uint32_t dividerValue); 6863 6864 6865 /******************************************************************************* 6866 * Function Name: Cy_SysClk_PeriPclkGetDivider 6867 ****************************************************************************//** 6868 * 6869 * Returns the integer divider value for the specified divider. One works for 6870 * integer dividers. Use \ref Cy_SysClk_PeriphGetFracDivider to get the fractional 6871 * divider value 6872 * 6873 * \param ipBlock specifies ip block to connect the clock divider to. 6874 * 6875 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6876 * 6877 * \param dividerNum specifies which divider of the selected type to configure 6878 * 6879 * \return The divider value. 6880 * The integer division done is by (divider value + 1), or division by 1 to 256 6881 * (8-bit divider) or 1 to 65536 (16-bit divider). 6882 * 6883 * \note 6884 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6885 * 6886 *******************************************************************************/ 6887 uint32_t Cy_SysClk_PeriPclkGetDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 6888 6889 6890 /******************************************************************************* 6891 * Function Name: Cy_SysClk_PeriPclkGetFracDivider 6892 ****************************************************************************//** 6893 * 6894 * Reports the integer and fractional parts of the divider 6895 * 6896 * \param ipBlock specifies ip block to connect the clock divider to. 6897 * 6898 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6899 * 6900 * \param dividerNum specifies which divider of the selected type to configure 6901 * 6902 * \param *dividerIntValue pointer to return integer divider value 6903 * 6904 * \param *dividerFracValue pointer to return fractional divider value 6905 * 6906 * \return None. Loads pointed-to variables. 6907 * 6908 * \note 6909 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6910 * 6911 *******************************************************************************/ 6912 void Cy_SysClk_PeriPclkGetFracDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, 6913 uint32_t *dividerIntValue, uint32_t *dividerFracValue); 6914 6915 6916 /******************************************************************************* 6917 * Function Name: Cy_SysClk_PeriPclkSetFracDivider 6918 ****************************************************************************//** 6919 * 6920 * Sets one of the programmable clock dividers. This function should only be used 6921 * for fractional clock dividers. 6922 * 6923 * \pre If the specified clock divider is already enabled - it should be disabled 6924 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 6925 * 6926 * \param ipBlock specifies ip block to connect the clock divider to. 6927 * 6928 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6929 * 6930 * \param dividerNum specifies which divider of the selected type to configure 6931 * 6932 * \param dividerIntValue the integer divider value 6933 * The source of the divider is peri_clk, which is a divided version of hf_clk[0]. 6934 * The divider value causes integer division of (divider value + 1), or division 6935 * by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider). 6936 * 6937 * \param dividerFracValue the fraction part of the divider 6938 * The fractional divider can be 0-31, thus it divides the clock by 1/32 for each 6939 * count. To divide the clock by 11/32nds set this value to 11. 6940 * 6941 * \return \ref cy_en_sysclk_status_t 6942 * 6943 * \note 6944 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6945 * 6946 *******************************************************************************/ 6947 cy_en_sysclk_status_t 6948 Cy_SysClk_PeriPclkSetFracDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, 6949 uint32_t dividerIntValue, uint32_t dividerFracValue); 6950 6951 6952 /******************************************************************************* 6953 * Function Name: Cy_SysClk_PeriPclkAssignDivider 6954 ****************************************************************************//** 6955 * 6956 * Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB. 6957 * 6958 * \param ipBlock specifies ip block to connect the clock divider to. 6959 * 6960 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6961 * 6962 * \param dividerNum specifies which divider of the selected type to configure 6963 * 6964 * \return \ref cy_en_sysclk_status_t 6965 * 6966 * \note 6967 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6968 * 6969 *******************************************************************************/ 6970 cy_en_sysclk_status_t 6971 Cy_SysClk_PeriPclkAssignDivider(en_clk_dst_t ipBlock, 6972 cy_en_divider_types_t dividerType, uint32_t dividerNum); 6973 6974 6975 /******************************************************************************* 6976 * Function Name: Cy_SysClk_PeriPclkGetAssignedDivider 6977 ****************************************************************************//** 6978 * 6979 * Reports which clock divider is assigned to a selected IP block. 6980 * 6981 * \param ipBlock specifies ip block to connect the clock divider to. 6982 * 6983 * \return The divider type and number 6984 * 6985 * \note 6986 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 6987 * 6988 *******************************************************************************/ 6989 uint32_t Cy_SysClk_PeriPclkGetAssignedDivider(en_clk_dst_t ipBlock); 6990 6991 6992 /******************************************************************************* 6993 * Function Name: Cy_SysClk_PeriPclkEnableDivider 6994 ****************************************************************************//** 6995 * 6996 * Enables the selected divider. 6997 * 6998 * \param ipBlock specifies ip block to connect the clock divider to. 6999 * 7000 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 7001 * 7002 * \param dividerNum specifies which divider of the selected type to configure 7003 * 7004 * \note This function also sets the phase alignment bits such that the enabled 7005 * divider is aligned to clk_peri. See \ref Cy_SysClk_PeriphDisableDivider() 7006 * for information on how to phase-align a divider after it is enabled. 7007 * 7008 * \note 7009 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 7010 * 7011 *******************************************************************************/ 7012 cy_en_sysclk_status_t 7013 Cy_SysClk_PeriPclkEnableDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 7014 7015 7016 /******************************************************************************* 7017 * Function Name: Cy_SysClk_PeriPclkDisableDivider 7018 ****************************************************************************//** 7019 * 7020 * Disables a selected divider. 7021 * 7022 * \param ipBlock specifies ip block to connect the clock divider to. 7023 * 7024 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 7025 * 7026 * \param dividerNum specifies which divider of the selected type to configure. 7027 * 7028 * \note 7029 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 7030 * 7031 *******************************************************************************/ 7032 cy_en_sysclk_status_t 7033 Cy_SysClk_PeriPclkDisableDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 7034 7035 7036 /******************************************************************************* 7037 * Function Name: Cy_SysClk_PeriPclkEnablePhaseAlignDivider 7038 ****************************************************************************//** 7039 * 7040 * First disables a selected divider (\ref Cy_SysClk_PeriphDisableDivider), 7041 * then aligns that divider to another programmable divider, and enables the 7042 * selected divider. The divider to align to must already be enabled in order 7043 * to align a divider to it. 7044 * 7045 * \param ipBlock specifies ip block to connect the clock divider to. 7046 * 7047 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 7048 * 7049 * \param dividerNum specifies which divider of the selected type to configure. 7050 * 7051 * \param dividerTypePA type of divider to phase-align to; \ref cy_en_divider_types_t. 7052 * 7053 * \param dividerNumPA divider number of type specified to phase align to. 7054 * 7055 * \note 7056 * To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA 7057 * to 63. 7058 * 7059 * \note 7060 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 7061 * 7062 *******************************************************************************/ 7063 cy_en_sysclk_status_t 7064 Cy_SysClk_PeriPclkEnablePhaseAlignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, 7065 cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA); 7066 7067 /******************************************************************************* 7068 * Function Name: Cy_SysClk_PeriPclkGetFrequency 7069 ****************************************************************************//** 7070 * 7071 * Reports the frequency of the output of a given peripheral divider. 7072 * 7073 * \param ipBlock specifies ip block to connect the clock divider to. 7074 * 7075 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 7076 * 7077 * \param dividerNum specifies which divider of the selected type to configure 7078 * 7079 * \return The frequency, in Hz. 7080 * 7081 * \note 7082 * The reported frequency may be zero, which indicates unknown. This happens if 7083 * the source input is dsi_out or clk_altlf. 7084 * 7085 * \note 7086 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 7087 * 7088 * \funcusage 7089 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetFrequency 7090 * 7091 *******************************************************************************/ 7092 uint32_t Cy_SysClk_PeriPclkGetFrequency(en_clk_dst_t ipBlock, 7093 cy_en_divider_types_t dividerType, 7094 uint32_t dividerNum); 7095 7096 /******************************************************************************* 7097 * Function Name: Cy_SysClk_PeriPclkGetDividerEnabled 7098 ****************************************************************************//** 7099 * 7100 * Reports the enabled/disabled state of the selected divider. 7101 * 7102 * \param ipBlock specifies ip block to connect the clock divider to. 7103 * 7104 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 7105 * 7106 * \param dividerNum specifies which divider of the selected type to configure. 7107 * 7108 * \note 7109 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 7110 * 7111 *******************************************************************************/ 7112 bool Cy_SysClk_PeriPclkGetDividerEnabled(en_clk_dst_t ipBlock, 7113 cy_en_divider_types_t dividerType, 7114 uint32_t dividerNum); 7115 7116 /******************************************************************************* 7117 * Function Name: Cy_Sysclk_PeriPclkGetClkHfNum 7118 ****************************************************************************//** 7119 * 7120 * Reports the corresponding CLK_HF* number for a particular PERI PCLK group 7121 * 7122 * \param ipBlock specifies ip block to connect the clock divider to. 7123 * 7124 * \return The CLK_HF* number. 7125 * 7126 * \note 7127 * This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices. 7128 * 7129 *******************************************************************************/ 7130 uint32_t Cy_Sysclk_PeriPclkGetClkHfNum(uint32_t ipBlock); 7131 7132 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) || defined (CY_IP_MXS22SRSS) */ 7133 7134 /******************************************************************************* 7135 * Function Name: Cy_SysClk_PeriphSetDivider 7136 ****************************************************************************//** 7137 * 7138 * Sets one of the programmable clock dividers. This is only used for integer 7139 * dividers. Use \ref Cy_SysClk_PeriphSetFracDivider for setting factional dividers. 7140 * 7141 * \pre If the specified clock divider is already enabled - it should be disabled 7142 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 7143 * 7144 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 7145 * 7146 * \param dividerNum the divider number. 7147 * 7148 * \param dividerValue divider value 7149 * Causes integer division of (divider value + 1), or division by 1 to 256 7150 * (8-bit divider) or 1 to 65536 (16-bit divider). 7151 * 7152 * \return \ref cy_en_sysclk_status_t 7153 * 7154 * \note 7155 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkSetDivider. 7156 * 7157 * \funcusage 7158 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider 7159 * 7160 *******************************************************************************/ 7161 cy_en_sysclk_status_t 7162 Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, 7163 uint32_t dividerNum, uint32_t dividerValue); 7164 7165 7166 /******************************************************************************* 7167 * Function Name: Cy_SysClk_PeriphGetDivider 7168 ****************************************************************************//** 7169 * 7170 * Returns the integer divider value for the specified divider. One works for 7171 * integer dividers. Use \ref Cy_SysClk_PeriphGetFracDivider to get the fractional 7172 * divider value 7173 * 7174 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 7175 * 7176 * \param dividerNum specifies which divider of the selected type to configure 7177 * 7178 * \return The divider value. 7179 * The integer division done is by (divider value + 1), or division by 1 to 256 7180 * (8-bit divider) or 1 to 65536 (16-bit divider). 7181 * 7182 * \note 7183 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetDivider. 7184 * 7185 * \funcusage 7186 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider 7187 * 7188 *******************************************************************************/ 7189 uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum); 7190 7191 7192 /******************************************************************************* 7193 * Function Name: Cy_SysClk_PeriphSetFracDivider 7194 ****************************************************************************//** 7195 * 7196 * Sets one of the programmable clock dividers. This function should only be used 7197 * for fractional clock dividers. 7198 * 7199 * \pre If the specified clock divider is already enabled - it should be disabled 7200 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 7201 * 7202 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 7203 * 7204 * \param dividerNum specifies which divider of the selected type to configure 7205 * 7206 * \param dividerIntValue the integer divider value 7207 * The source of the divider is peri_clk, which is a divided version of hf_clk[0]. 7208 * The divider value causes integer division of (divider value + 1), or division 7209 * by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider). 7210 * 7211 * \param dividerFracValue the fraction part of the divider 7212 * The fractional divider can be 0-31, thus it divides the clock by 1/32 for each 7213 * count. To divide the clock by 11/32nds set this value to 11. 7214 * 7215 * \return \ref cy_en_sysclk_status_t 7216 * 7217 * \note 7218 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkSetFracDivider. 7219 * 7220 * \funcusage 7221 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider 7222 * 7223 *******************************************************************************/ 7224 cy_en_sysclk_status_t 7225 Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, 7226 uint32_t dividerIntValue, uint32_t dividerFracValue); 7227 7228 7229 /******************************************************************************* 7230 * Function Name: Cy_SysClk_PeriphGetFracDivider 7231 ****************************************************************************//** 7232 * 7233 * Reports the integer and fractional parts of the divider 7234 * 7235 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 7236 * 7237 * \param dividerNum specifies which divider of the selected type to configure 7238 * 7239 * \param *dividerIntValue pointer to return integer divider value 7240 * 7241 * \param *dividerFracValue pointer to return fractional divider value 7242 * 7243 * \return None. Loads pointed-to variables. 7244 * 7245 * \note 7246 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetFracDivider. 7247 * 7248 * \funcusage 7249 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider 7250 * 7251 *******************************************************************************/ 7252 void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, 7253 uint32_t *dividerIntValue, uint32_t *dividerFracValue); 7254 7255 7256 /******************************************************************************* 7257 * Function Name: Cy_SysClk_PeriphAssignDivider 7258 ****************************************************************************//** 7259 * 7260 * Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB. 7261 * 7262 * \param ipBlock specifies ip block to connect the clock divider to. 7263 * 7264 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 7265 * 7266 * \param dividerNum specifies which divider of the selected type to configure 7267 * 7268 * \return \ref cy_en_sysclk_status_t 7269 * 7270 * \note 7271 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkAssignDivider. 7272 * 7273 * \funcusage 7274 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider 7275 * 7276 *******************************************************************************/ 7277 cy_en_sysclk_status_t 7278 Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, 7279 cy_en_divider_types_t dividerType, uint32_t dividerNum); 7280 7281 7282 /******************************************************************************* 7283 * Function Name: Cy_SysClk_PeriphGetAssignedDivider 7284 ****************************************************************************//** 7285 * 7286 * Reports which clock divider is assigned to a selected IP block. 7287 * 7288 * \param ipBlock specifies ip block to connect the clock divider to. 7289 * 7290 * \return The divider type and number 7291 * 7292 * \note 7293 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetAssignedDivider. 7294 * 7295 * \funcusage 7296 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider 7297 * 7298 *******************************************************************************/ 7299 uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock); 7300 7301 7302 /******************************************************************************* 7303 * Function Name: Cy_SysClk_PeriphEnableDivider 7304 ****************************************************************************//** 7305 * 7306 * Enables the selected divider. 7307 * 7308 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 7309 * 7310 * \param dividerNum specifies which divider of the selected type to configure 7311 * 7312 * \note This function also sets the phase alignment bits such that the enabled 7313 * divider is aligned to clk_peri. See \ref Cy_SysClk_PeriphDisableDivider() 7314 * for information on how to phase-align a divider after it is enabled. 7315 * 7316 * \note 7317 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkEnableDivider. 7318 * 7319 * \funcusage 7320 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnableDivider 7321 * 7322 *******************************************************************************/ 7323 cy_en_sysclk_status_t 7324 Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum); 7325 7326 7327 /******************************************************************************* 7328 * Function Name: Cy_SysClk_PeriphDisableDivider 7329 ****************************************************************************//** 7330 * 7331 * Disables a selected divider. 7332 * 7333 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 7334 * 7335 * \param dividerNum specifies which divider of the selected type to configure. 7336 * 7337 * \note 7338 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkDisableDivider. 7339 * 7340 * \funcusage 7341 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphDisableDivider 7342 * 7343 *******************************************************************************/ 7344 cy_en_sysclk_status_t 7345 Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum); 7346 7347 7348 /******************************************************************************* 7349 * Function Name: Cy_SysClk_PeriphEnablePhaseAlignDivider 7350 ****************************************************************************//** 7351 * 7352 * First disables a selected divider (\ref Cy_SysClk_PeriphDisableDivider), 7353 * then aligns that divider to another programmable divider, and enables the 7354 * selected divider. The divider to align to must already be enabled in order 7355 * to align a divider to it. 7356 * 7357 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 7358 * 7359 * \param dividerNum specifies which divider of the selected type to configure. 7360 * 7361 * \param dividerTypePA type of divider to phase-align to; \ref cy_en_divider_types_t. 7362 * 7363 * \param dividerNumPA divider number of type specified to phase align to. 7364 * 7365 * \note 7366 * To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA 7367 * to 63. 7368 * 7369 * \note 7370 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkEnablePhaseAlignDivider. 7371 * 7372 * \funcusage 7373 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnablePhaseAlignDivider 7374 * 7375 *******************************************************************************/ 7376 cy_en_sysclk_status_t 7377 Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, 7378 cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA); 7379 7380 7381 /******************************************************************************* 7382 * Function Name: Cy_SysClk_PeriphGetDividerEnabled 7383 ****************************************************************************//** 7384 * 7385 * Reports the enabled/disabled state of the selected divider. 7386 * 7387 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 7388 * 7389 * \param dividerNum specifies which divider of the selected type to configure. 7390 * 7391 * \return The enabled/disabled state; \n 7392 * false = disabled \n 7393 * true = enabled 7394 * 7395 * \note 7396 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetDividerEnabled. 7397 * 7398 * \funcusage 7399 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetDividerEnabled 7400 * 7401 *******************************************************************************/ 7402 bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum); 7403 7404 7405 /******************************************************************************* 7406 * Function Name: Cy_SysClk_PeriphGetFrequency 7407 ****************************************************************************//** 7408 * 7409 * Reports the frequency of the output of a given peripheral divider. 7410 * 7411 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 7412 * 7413 * \param dividerNum specifies which divider of the selected type to configure 7414 * 7415 * \return The frequency, in Hz. 7416 * 7417 * \note 7418 * The reported frequency may be zero, which indicates unknown. This happens if 7419 * the source input is dsi_out or clk_altlf. 7420 * 7421 * \note 7422 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetFrequency. 7423 * 7424 * \funcusage 7425 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetFrequency 7426 * 7427 *******************************************************************************/ 7428 uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum); 7429 7430 7431 /** \} group_sysclk_clk_peripheral_funcs */ 7432 7433 7434 /* ========================================================================== */ 7435 /* ========================= clk_slow SECTION ========================= */ 7436 /* ========================================================================== */ 7437 /** 7438 * \addtogroup group_sysclk_clk_slow_funcs 7439 * \{ 7440 */ 7441 7442 #if defined (CY_IP_MXS40SRSS) 7443 7444 /******************************************************************************* 7445 * Function Name: Cy_SysClk_ClkSlowSetDivider 7446 ****************************************************************************//** 7447 * 7448 * Sets the clock divider for the slow clock. 7449 * 7450 * \param divider Divider value between 0 and 255. 7451 * Causes integer division of (divider value + 1), or division by 1 to 256. 7452 * 7453 * \note 7454 * Call \ref SystemCoreClockUpdate after this function calling. 7455 * 7456 * \note 7457 * This API is available for CAT1A & CAT1C devices. 7458 * 7459 * \funcusage 7460 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider 7461 * 7462 *******************************************************************************/ 7463 void Cy_SysClk_ClkSlowSetDivider(uint8_t divider); 7464 7465 7466 /******************************************************************************* 7467 * Function Name: Cy_SysClk_ClkSlowGetDivider 7468 ****************************************************************************//** 7469 * 7470 * Reports the divider value for the slow clock. 7471 * 7472 * \return The divider value. 7473 * The integer division done is by (divider value + 1), or division by 1 to 256. 7474 * 7475 * \note 7476 * This API is available for CAT1A & CAT1C devices. 7477 * 7478 * \funcusage 7479 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider 7480 * 7481 *******************************************************************************/ 7482 uint8_t Cy_SysClk_ClkSlowGetDivider(void); 7483 7484 7485 /******************************************************************************* 7486 * Function Name: Cy_SysClk_ClkSlowGetFrequency 7487 ****************************************************************************//** 7488 * 7489 * Reports the frequency of the slow clock. 7490 * 7491 * \return The frequency, in Hz. 7492 * 7493 * \note 7494 * This API is available for CAT1A & CAT1C devices. 7495 * 7496 * \funcusage 7497 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider 7498 * 7499 *******************************************************************************/ 7500 uint32_t Cy_SysClk_ClkSlowGetFrequency(void); 7501 7502 #endif 7503 7504 /** \} group_sysclk_clk_slow_funcs */ 7505 7506 #if (defined (CY_IP_MXS40SRSS) && defined (CY_IP_M7CPUSS)) || defined (CY_DOXYGEN) 7507 7508 /* ========================================================================== */ 7509 /* ========================= clk_mem SECTION ========================= */ 7510 /* ========================================================================== */ 7511 /** 7512 * \addtogroup group_sysclk_clk_mem_funcs 7513 * \{ 7514 */ 7515 7516 /******************************************************************************* 7517 * Function Name: Cy_SysClk_ClkMemSetDivider 7518 ****************************************************************************//** 7519 * 7520 * Sets the clock divider for the Mem clock. The source of this clock is clkHf[0]. 7521 * 7522 * \param divider Divider value between 0 and 255. 7523 * Causes integer division of (divider value + 1), or division by 1 to 256. 7524 * 7525 * \note 7526 * Call \ref SystemCoreClockUpdate after this function calling. 7527 * 7528 * \note 7529 * This API is available for only CAT1C devices. 7530 * 7531 *******************************************************************************/ 7532 void Cy_SysClk_ClkMemSetDivider(uint8_t divider); 7533 7534 7535 /******************************************************************************* 7536 * Function Name: Cy_SysClk_ClkMemGetDivider 7537 ****************************************************************************//** 7538 * 7539 * Reports the divider value for the Mem clock. 7540 * 7541 * \return The divider value. 7542 * The integer division done is by (divider value + 1), or division by 1 to 256. 7543 * 7544 * \note 7545 * This API is available for only CAT1C devices. 7546 * 7547 *******************************************************************************/ 7548 uint8_t Cy_SysClk_ClkMemGetDivider(void); 7549 7550 7551 /******************************************************************************* 7552 * Function Name: Cy_SysClk_ClkMemGetFrequency 7553 ****************************************************************************//** 7554 * 7555 * Reports the frequency of the Mem clock. 7556 * 7557 * \return The frequency, in Hz. 7558 * 7559 * \note 7560 * This API is available for only CAT1C devices. 7561 * 7562 *******************************************************************************/ 7563 uint32_t Cy_SysClk_ClkMemGetFrequency(void); 7564 7565 #endif /* (defined (CY_IP_MXS40SRSS) && defined (CY_IP_M7CPUSS)) */ 7566 7567 /** \} group_sysclk_clk_mem_funcs */ 7568 7569 /* ========================================================================== */ 7570 /* =========================== clkLf SECTION ========================== */ 7571 /* ========================================================================== */ 7572 /** 7573 * \addtogroup group_sysclk_clk_lf_enums 7574 * \{ 7575 */ 7576 /** 7577 * Low frequency (clkLf) input sources. See CLK_SELECT register, LFCLK_SEL bits. 7578 * Used with functions \ref Cy_SysClk_ClkLfSetSource, and \ref Cy_SysClk_ClkLfGetSource. 7579 */ 7580 #if defined (CY_IP_MXS22SRSS) 7581 typedef enum 7582 { 7583 CY_SYSCLK_CLKLF_IN_PILO = 0U, /**< clkLf is sourced by the precision low speed oscillator (PILO) */ 7584 CY_SYSCLK_CLKLF_IN_WCO = 1U, /**< clkLf is sourced by the watch crystal oscillator (WCO) */ 7585 CY_SYSCLK_CLKLF_IN_ALTLF = 2U, /**< clkLf is sourced by the Alternate Low Frequency Clock (ALTLF) */ 7586 CY_SYSCLK_CLKLF_IN_ECO_PRESCALER = 3U, /**< clkLf is sourced by the External Clock Oscillator (ECO Prescaler) */ 7587 CY_SYSCLK_CLKLF_IN_ILO = 4U, /**< clkLf is sourced by the internal low speed oscillator (ILO) */ 7588 CY_SYSCLK_CLKLF_IN_MAX = 5U /**< clkLf MAX value*/ 7589 } cy_en_clklf_in_sources_t; 7590 7591 #else 7592 typedef enum 7593 { 7594 CY_SYSCLK_CLKLF_IN_ILO = 0U, /**< clkLf is sourced by the internal low speed oscillator (ILO) */ 7595 CY_SYSCLK_CLKLF_IN_WCO = 1U, /**< clkLf is sourced by the watch crystal oscillator (WCO) */ 7596 CY_SYSCLK_CLKLF_IN_ALTLF = 2U, /**< clkLf is sourced by the Alternate Low Frequency Clock (ALTLF) */ 7597 CY_SYSCLK_CLKLF_IN_PILO = 3U, /**< clkLf is sourced by the precision low speed oscillator (PILO) */ 7598 CY_SYSCLK_CLKLF_IN_ILO1 = 4U, /**< clkLf is sourced by the internal low speed oscillator (ILO1)*/ 7599 CY_SYSCLK_CLKLF_IN_ECO_PRESCALER = 5U, /**< clkLf is sourced by the External Clock Oscillator (ECO Prescaler) */ 7600 CY_SYSCLK_CLKLF_IN_LPECO_PRESCALER = 6U, /**< clkLf is sourced by the External Clock Oscillator (LP ECO Prescaler) */ 7601 CY_SYSCLK_CLKLF_IN_MAX = 7U /**< clkLf MAX value*/ 7602 } cy_en_clklf_in_sources_t; 7603 7604 #endif /* defined (CY_IP_MXS22SRSS) */ 7605 7606 #if defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) 7607 /** 7608 * clklf csv reference clock input sources. 7609 */ 7610 /** 7611 * \note 7612 * This enum is available for CAT1B(PSoC C3), CAT1D devices. 7613 **/ 7614 #if defined (CY_IP_MXS22SRSS) 7615 typedef enum 7616 { 7617 CY_SYSCLK_CLKLF_CSV_REF_PILO = 0U, /**< Reference clock is the precision low speed oscillator (PILO) */ 7618 CY_SYSCLK_CLKLF_CSV_REF_ILO = 1U, /**< Reference clock is the internal low speed oscillator (ILO) */ 7619 CY_SYSCLK_CLKLF_CSV_REF_WCO = 2U, /**< Reference clock is the External Clock Oscillator (ECO Prescaler) */ 7620 CY_SYSCLK_CLKLF_CSV_REF_TIMERCLK = 3U, /**< Reference clock is the timer clock */ 7621 } cy_en_clklf_csv_ref_clk_t; 7622 #else 7623 typedef enum 7624 { 7625 CY_SYSCLK_CLKLF_CSV_REF_IMO = 0U, /**< Reference clock is the IMO */ 7626 CY_SYSCLK_CLKLF_CSV_REF_EXT = 1U, /**< Reference clock is the external clock */ 7627 CY_SYSCLK_CLKLF_CSV_REF_ECO = 2U, /**< Reference clock is ECO */ 7628 CY_SYSCLK_CLKLF_CSV_REF_ALTHF0 = 3U, /**< Reference clock is ALTHF0 */ 7629 CY_SYSCLK_CLKLF_CSV_REF_IHO = 4U, /**< Reference clock is IHO */ 7630 CY_SYSCLK_CLKLF_CSV_REF_ALTHF1 = 5U /**< Reference clock is ALTHF1 */ 7631 } cy_en_clklf_csv_ref_clk_t; 7632 #endif 7633 #endif 7634 /** \} group_sysclk_clk_lf_enums */ 7635 7636 /** 7637 * \addtogroup group_sysclk_clk_lf_structs 7638 * \{ 7639 */ 7640 7641 #if defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) 7642 /** 7643 * \note 7644 * This structure is available for CAT1B(PSoC C3), CAT1D devices. 7645 **/ 7646 typedef struct 7647 { 7648 uint32_t startTime; /**< Startup delay time, after enable or DeepSleep wakeup, from reference clock start to monitored clock start. */ 7649 uint32_t lowerLimit; /**< Lower limit in reference clock cycles, before the next monitored clock event is allowed to happen. */ 7650 uint32_t upperLimit; /**< Upper limit in reference clock cycles, before (or same time) the next monitored clock event must happen. */ 7651 uint32_t period; /**< Period in monitored clock cycles, before the next monitored clock event happens. */ 7652 } cy_stc_clklf_csv_manual_config_t; 7653 7654 #endif 7655 7656 /** \} group_sysclk_clk_lf_structs */ 7657 7658 7659 /** 7660 * \addtogroup group_sysclk_clk_lf_funcs 7661 * \{ 7662 */ 7663 /******************************************************************************* 7664 * Function Name: Cy_SysClk_ClkLfSetSource 7665 ****************************************************************************//** 7666 * 7667 * Sets the source for the low frequency clock(clkLf). 7668 * 7669 * \param source \ref cy_en_clklf_in_sources_t 7670 * 7671 * \note The watchdog timer (WDT) must be unlocked before calling this function. 7672 * 7673 * \note It takes four cycles of the originally selected clock to switch away 7674 * from it. Do not disable the original clock during this time. 7675 * 7676 * \funcusage 7677 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource 7678 * 7679 *******************************************************************************/ 7680 void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source); 7681 7682 7683 /******************************************************************************* 7684 * Function Name: Cy_SysClk_ClkLfGetSource 7685 ****************************************************************************//** 7686 * 7687 * Reports the source for the low frequency clock (clkLf). 7688 * 7689 * \return \ref cy_en_clklf_in_sources_t 7690 * 7691 * \funcusage 7692 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource 7693 * 7694 *******************************************************************************/ 7695 cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void); 7696 7697 7698 #if defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) 7699 7700 /******************************************************************************* 7701 * Function Name: Cy_SysClk_ClkLfGetFrequency 7702 ****************************************************************************//** 7703 * 7704 * Reports the frequency of the clklf 7705 * 7706 * \return The frequency, in Hz. 7707 * 7708 * \funcusage 7709 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfCSVConfig 7710 * 7711 *******************************************************************************/ 7712 uint32_t Cy_SysClk_ClkLfGetFrequency(void); 7713 7714 7715 /******************************************************************************* 7716 * Function Name: Cy_SysClk_ClkLfCsvGetRefFrequency 7717 ****************************************************************************//** 7718 * 7719 * Get the clklf csv reference clock frequency. 7720 * 7721 * \param refClk Reference clock source. 7722 * 7723 * \return \ref cy_en_sysclk_status_t. 7724 * 7725 * \note 7726 * This API is available for CAT1B(PSoC C3), CAT1D devices. 7727 * 7728 * \funcusage 7729 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfCSVConfig 7730 * 7731 *******************************************************************************/ 7732 uint32_t Cy_SysClk_ClkLfCsvGetRefFrequency(cy_en_clklf_csv_ref_clk_t refClk); 7733 7734 7735 /******************************************************************************* 7736 * Function Name: Cy_SysClk_ClkLfCsvManualConfigure 7737 ****************************************************************************//** 7738 * 7739 * Manually configures the clklf csv based on user inputs. 7740 * 7741 * \param refClk Reference clock for csv operation. 7742 * 7743 * \param csvConfig Selects the csv configuration required. 7744 * 7745 * \return The frequency in Hz. 7746 * 7747 * \note 7748 * This API is available for CAT1B(PSoC C3), CAT1D devices. 7749 * 7750 * \funcusage 7751 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfCSVConfig 7752 * 7753 *******************************************************************************/ 7754 cy_en_sysclk_status_t Cy_SysClk_ClkLfCsvManualConfigure(cy_en_clklf_csv_ref_clk_t refClk, const cy_stc_clklf_csv_manual_config_t * csvConfig); 7755 7756 7757 /******************************************************************************* 7758 * Function Name: Cy_SysClk_ClkLfCsvConfigure 7759 ****************************************************************************//** 7760 * 7761 * Configures clklf csv. 7762 * 7763 * The configuration formula used is: 7764 * Lower_limit = Target - Required accuracy/2 7765 * Upper_limit = Target + Required accuracy/2 7766 * Period = Target / (Reference frequency / Monitor frequency) 7767 * Start_time = (Period +3) * (Reference frequency / Monitor frequency) - Upper_limit 7768 * 7769 * \param lfConfig Selects the reference clock for csv operation. 7770 * 7771 * \param accuracy Required accuracy. 7772 * 7773 * \return \ref cy_en_sysclk_status_t. 7774 * 7775 * \note 7776 * This API is available for CAT1B(PSoC C3), CAT1D devices. 7777 * 7778 * \funcusage 7779 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfCSVConfig 7780 * 7781 *******************************************************************************/ 7782 cy_en_sysclk_status_t Cy_SysClk_ClkLfCsvConfigure(cy_en_clklf_csv_ref_clk_t refClk, uint32_t accuracy); 7783 7784 7785 /******************************************************************************* 7786 * Function Name: Cy_SysClk_ClkLfCsvEnable 7787 ****************************************************************************//** 7788 * 7789 * Enables the csv for the clklf. 7790 * 7791 * \note 7792 * This API is available for CAT1B(PSoC C3), CAT1D devices. 7793 * 7794 * \funcusage 7795 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfCSVConfig 7796 * 7797 *******************************************************************************/ 7798 void Cy_SysClk_ClkLfCsvEnable(void); 7799 7800 7801 /******************************************************************************* 7802 * Function Name: Cy_SysClk_ClkLfCsvDisable 7803 ****************************************************************************//** 7804 * 7805 * Disables the csv for the clklf. 7806 * 7807 * \note 7808 * This API is available for CAT1B(PSoC C3), CAT1D devices. 7809 * 7810 * \funcusage 7811 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfCSVConfig 7812 * 7813 *******************************************************************************/ 7814 void Cy_SysClk_ClkLfCsvDisable(void); 7815 7816 7817 /******************************************************************************* 7818 * Function Name: Cy_SysClk_IsClkLfCsvEnabled 7819 ****************************************************************************//** 7820 * 7821 * Returns the enabled status of csv for the clklf. 7822 * 7823 * \return \ref cy_en_sysclk_status_t. 7824 * 7825 * \note 7826 * This API is available for CAT1B(PSoC C3), CAT1D devices. 7827 * 7828 * \funcusage 7829 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfCSVConfig 7830 * 7831 *******************************************************************************/ 7832 bool Cy_SysClk_IsClkLfCsvEnabled(void); 7833 7834 #endif 7835 7836 /** \} group_sysclk_clk_lf_funcs */ 7837 7838 7839 /* ========================================================================== */ 7840 /* ======================== clk_timer SECTION ========================= */ 7841 /* ========================================================================== */ 7842 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_DOXYGEN) 7843 7844 /** 7845 * \addtogroup group_sysclk_clk_timer_enums 7846 * \{ 7847 */ 7848 /** 7849 * Timer clock (clk_timer) input sources. See CLK_TIMER_CTL register, TIMER_SEL 7850 * and TIMER_HF0_DIV bits. Used with functions \ref Cy_SysClk_ClkTimerSetSource, and 7851 * \ref Cy_SysClk_ClkTimerGetSource. 7852 */ 7853 typedef enum 7854 { 7855 CY_SYSCLK_CLKTIMER_IN_IMO = 0x000U, /**< clk_timer is sourced by the internal main oscillator (IMO) */ 7856 CY_SYSCLK_CLKTIMER_IN_HF0_NODIV = 0x001U, /**< clk_timer is sourced by clkHf[0] undivided */ 7857 CY_SYSCLK_CLKTIMER_IN_HF0_DIV2 = 0x101U, /**< clk_timer is sourced by clkHf[0] divided by 2 */ 7858 CY_SYSCLK_CLKTIMER_IN_HF0_DIV4 = 0x201U, /**< clk_timer is sourced by clkHf[0] divided by 4 */ 7859 CY_SYSCLK_CLKTIMER_IN_HF0_DIV8 = 0x301U /**< clk_timer is sourced by clkHf[0] divided by 8 */ 7860 } cy_en_clktimer_in_sources_t; 7861 /** \} group_sysclk_clk_timer_enums */ 7862 7863 /** \cond */ 7864 #define CY_SRSS_CLK_TIMER_CTL_TIMER_Pos (SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos) 7865 #define CY_SRSS_CLK_TIMER_CTL_TIMER_Msk (SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk | SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk) 7866 /** \endcond */ 7867 7868 /** 7869 * \addtogroup group_sysclk_clk_timer_funcs 7870 * \{ 7871 */ 7872 7873 /******************************************************************************* 7874 * Function Name: Cy_SysClk_ClkTimerSetSource 7875 ****************************************************************************//** 7876 * 7877 * Sets the source for the timer clock (clk_timer). The timer clock can be used 7878 * as a source for SYSTICK as an alternate clock and one or more of the energy 7879 * profiler counters. 7880 * 7881 * \param source \ref cy_en_clktimer_in_sources_t 7882 * 7883 * \note 7884 * This API is available for CAT1A (excluding TVIIBE) devices. 7885 * 7886 * \funcusage 7887 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource 7888 * 7889 *******************************************************************************/ 7890 void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source); 7891 7892 7893 /******************************************************************************* 7894 * Function Name: Cy_SysClk_ClkTimerGetSource 7895 ****************************************************************************//** 7896 * 7897 * Reports the source for the timer clock (clk_timer). 7898 * 7899 * \return \ref cy_en_clktimer_in_sources_t 7900 * 7901 * \note 7902 * This API is available for CAT1A (excluding TVIIBE) devices. 7903 * 7904 * \funcusage 7905 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource 7906 * 7907 *******************************************************************************/ 7908 cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void); 7909 7910 7911 /******************************************************************************* 7912 * Function Name: Cy_SysClk_ClkTimerSetDivider 7913 ****************************************************************************//** 7914 * 7915 * Sets the divider for the timer clock (clk_timer). 7916 * 7917 * \param divider Divider value; valid range is 0 to 255. Divides the selected 7918 * source (\ref Cy_SysClk_ClkTimerSetSource) by the (value + 1). 7919 * 7920 * \note 7921 * Do not change the divider value while the timer clock is enabled. 7922 * 7923 * \note 7924 * This API is available for CAT1A (excluding TVIIBE) devices. 7925 * 7926 * \funcusage 7927 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider 7928 * 7929 *******************************************************************************/ 7930 void Cy_SysClk_ClkTimerSetDivider(uint8_t divider); 7931 7932 7933 /******************************************************************************* 7934 * Function Name: Cy_SysClk_ClkTimerGetDivider 7935 ****************************************************************************//** 7936 * 7937 * Reports the divider value for the timer clock (clk_timer). 7938 * 7939 * \return The divider value 7940 * 7941 * \note 7942 * This API is available for CAT1A (excluding TVIIBE) devices. 7943 * 7944 * \funcusage 7945 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider 7946 * 7947 *******************************************************************************/ 7948 uint8_t Cy_SysClk_ClkTimerGetDivider(void); 7949 7950 7951 /******************************************************************************* 7952 * Function Name: Cy_SysClk_ClkTimerEnable 7953 ****************************************************************************//** 7954 * 7955 * Enables the timer clock (clk_timer). The timer clock can be used as a source 7956 * for SYSTICK and one or more of the energy profiler counters. 7957 * 7958 * \note 7959 * This API is available for CAT1A (excluding TVIIBE) devices. 7960 * 7961 * 7962 * \funcusage 7963 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable 7964 * 7965 *******************************************************************************/ 7966 void Cy_SysClk_ClkTimerEnable(void); 7967 7968 7969 /******************************************************************************* 7970 * Function Name: Cy_SysClk_ClkTimerDisable 7971 ****************************************************************************//** 7972 * 7973 * Disables the timer clock (clk_timer). 7974 * 7975 * \note 7976 * This API is available for CAT1A (excluding TVIIBE) devices. 7977 * 7978 * \funcusage 7979 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable 7980 * 7981 *******************************************************************************/ 7982 void Cy_SysClk_ClkTimerDisable(void); 7983 7984 7985 /******************************************************************************* 7986 * Function Name: Cy_SysClk_ClkTimerIsEnabled 7987 ****************************************************************************//** 7988 * 7989 * Reports the Enabled/Disabled status of the Timer. 7990 * 7991 * \return Boolean status of Timer: true - Enabled, false - Disabled. 7992 * 7993 * \funcusage 7994 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable 7995 * 7996 * \note 7997 * This API is available for CAT1A (excluding TVIIBE) devices. 7998 * 7999 *******************************************************************************/ 8000 bool Cy_SysClk_ClkTimerIsEnabled(void); 8001 8002 8003 /******************************************************************************* 8004 * Function Name: Cy_SysClk_ClkTimerGetFrequency 8005 ****************************************************************************//** 8006 * 8007 * Reports the frequency of the timer clock (clk_timer). 8008 * \note If the the timer clock is not enabled - a zero frequency is reported. 8009 * 8010 * \funcusage 8011 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable 8012 * 8013 * \note 8014 * This API is available for CAT1A (excluding TVIIBE) devices. 8015 * 8016 *******************************************************************************/ 8017 uint32_t Cy_SysClk_ClkTimerGetFrequency(void); 8018 8019 #endif /*(defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) */ 8020 8021 8022 /** \} group_sysclk_clk_timer_funcs */ 8023 8024 8025 #if defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) 8026 /* ========================================================================== */ 8027 /* ========================= clk_pump SECTION ========================= */ 8028 /* ========================================================================== */ 8029 /** 8030 * \addtogroup group_sysclk_clk_pump_enums 8031 * \{ 8032 */ 8033 8034 /** 8035 * Pump clock (clk_pump) input sources. See CLK_SELECT register, PUMP_SEL bits. 8036 * Used with functions \ref Cy_SysClk_ClkPumpSetSource, and 8037 * \ref Cy_SysClk_ClkPumpGetSource. 8038 */ 8039 /** 8040 * \note 8041 * This enum is available for CAT1A, CAT1B and CAT1C devices. 8042 **/ 8043 typedef enum 8044 { 8045 CY_SYSCLK_PUMP_IN_CLKPATH0 = 0UL, /**< Pump clock input is clock path 0 */ 8046 CY_SYSCLK_PUMP_IN_CLKPATH1 = 1UL, /**< Pump clock input is clock path 1 */ 8047 CY_SYSCLK_PUMP_IN_CLKPATH2 = 2UL, /**< Pump clock input is clock path 2 */ 8048 CY_SYSCLK_PUMP_IN_CLKPATH3 = 3UL, /**< Pump clock input is clock path 3 */ 8049 CY_SYSCLK_PUMP_IN_CLKPATH4 = 4UL, /**< Pump clock input is clock path 4 */ 8050 CY_SYSCLK_PUMP_IN_CLKPATH5 = 5UL, /**< Pump clock input is clock path 5 */ 8051 CY_SYSCLK_PUMP_IN_CLKPATH6 = 6UL, /**< Pump clock input is clock path 6 */ 8052 CY_SYSCLK_PUMP_IN_CLKPATH7 = 7UL, /**< Pump clock input is clock path 7 */ 8053 CY_SYSCLK_PUMP_IN_CLKPATH8 = 8UL, /**< Pump clock input is clock path 8 */ 8054 CY_SYSCLK_PUMP_IN_CLKPATH9 = 9UL, /**< Pump clock input is clock path 9 */ 8055 CY_SYSCLK_PUMP_IN_CLKPATH10 = 10UL, /**< Pump clock input is clock path 10 */ 8056 CY_SYSCLK_PUMP_IN_CLKPATH11 = 11UL, /**< Pump clock input is clock path 11 */ 8057 CY_SYSCLK_PUMP_IN_CLKPATH12 = 12UL, /**< Pump clock input is clock path 12 */ 8058 CY_SYSCLK_PUMP_IN_CLKPATH13 = 13UL, /**< Pump clock input is clock path 13 */ 8059 CY_SYSCLK_PUMP_IN_CLKPATH14 = 14UL, /**< Pump clock input is clock path 14 */ 8060 CY_SYSCLK_PUMP_IN_CLKPATH15 = 15UL /**< Pump clock input is clock path 15 */ 8061 } cy_en_clkpump_in_sources_t; 8062 8063 /** 8064 * Pump clock (clk_pump) divide options. See CLK_SELECT register, PUMP_DIV bits. 8065 * Used with functions \ref Cy_SysClk_ClkPumpSetDivider, and 8066 * \ref Cy_SysClk_ClkPumpGetDivider. 8067 */ 8068 /** 8069 * \note 8070 * This enum is available for CAT1A, CAT1B and CAT1C devices. 8071 **/ 8072 typedef enum 8073 { 8074 CY_SYSCLK_PUMP_NO_DIV = 0U, /**< No division on pump clock */ 8075 CY_SYSCLK_PUMP_DIV_2 = 1U, /**< Pump clock divided by 2 */ 8076 CY_SYSCLK_PUMP_DIV_4 = 2U, /**< Pump clock divided by 4 */ 8077 CY_SYSCLK_PUMP_DIV_8 = 3U, /**< Pump clock divided by 8 */ 8078 CY_SYSCLK_PUMP_DIV_16 = 4U /**< Pump clock divided by 16 */ 8079 } cy_en_clkpump_divide_t; 8080 /** \} group_sysclk_clk_pump_enums */ 8081 8082 /** \cond */ 8083 #define CY_SYSCLK_FLL_IS_DIVIDER_VALID(div) (((div) == CY_SYSCLK_PUMP_NO_DIV) || \ 8084 ((div) == CY_SYSCLK_PUMP_DIV_2) || \ 8085 ((div) == CY_SYSCLK_PUMP_DIV_4) || \ 8086 ((div) == CY_SYSCLK_PUMP_DIV_8) || \ 8087 ((div) == CY_SYSCLK_PUMP_DIV_16)) 8088 /** \endcond */ 8089 8090 /** 8091 * \addtogroup group_sysclk_clk_pump_funcs 8092 * \{ 8093 */ 8094 /******************************************************************************* 8095 * Function Name: Cy_SysClk_ClkPumpSetSource 8096 ****************************************************************************//** 8097 * 8098 * Sets the source for the pump clock (clk_pump). The pump clock can be used for 8099 * the analog pumps in the CTBm block. 8100 * 8101 * \param source \ref cy_en_clkpump_in_sources_t 8102 * 8103 * \note 8104 * Do not change the source while the pump clock is enabled. 8105 * 8106 * \funcusage 8107 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource 8108 * 8109 * \note 8110 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 8111 * 8112 *******************************************************************************/ 8113 void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source); 8114 8115 8116 /******************************************************************************* 8117 * Function Name: Cy_SysClk_ClkPumpGetSource 8118 ****************************************************************************//** 8119 * 8120 * Reports the source for the pump clock (clk_pump). 8121 * 8122 * \return \ref cy_en_clkpump_in_sources_t 8123 * 8124 * \funcusage 8125 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource 8126 * 8127 * \note 8128 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 8129 * 8130 *******************************************************************************/ 8131 cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void); 8132 8133 8134 /******************************************************************************* 8135 * Function Name: Cy_SysClk_ClkPumpSetDivider 8136 ****************************************************************************//** 8137 * 8138 * Sets the divider of the pump clock (clk_pump). 8139 * 8140 * \param divider \ref cy_en_clkpump_divide_t 8141 * 8142 * \note 8143 * Do not change the divider value while the pump clock is enabled. 8144 * 8145 * \funcusage 8146 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider 8147 * 8148 * \note 8149 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 8150 * 8151 *******************************************************************************/ 8152 void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider); 8153 8154 8155 /******************************************************************************* 8156 * Function Name: Cy_SysClk_ClkPumpGetDivider 8157 ****************************************************************************//** 8158 * 8159 * Reports the divider value for the pump clock (clk_pump). 8160 * 8161 * \return \ref cy_en_clkpump_divide_t 8162 * 8163 * \funcusage 8164 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider 8165 * 8166 * \note 8167 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 8168 * 8169 *******************************************************************************/ 8170 cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void); 8171 8172 8173 /******************************************************************************* 8174 * Function Name: Cy_SysClk_ClkPumpEnable 8175 ****************************************************************************//** 8176 * 8177 * Enables the pump clock (clk_pump). The pump clock can be used for the analog 8178 * pumps in the CTBm block. 8179 * 8180 * \funcusage 8181 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable 8182 * 8183 * \note 8184 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 8185 * 8186 *******************************************************************************/ 8187 void Cy_SysClk_ClkPumpEnable(void); 8188 8189 8190 /******************************************************************************* 8191 * Function Name: Cy_SysClk_ClkPumpIsEnabled 8192 ****************************************************************************//** 8193 * 8194 * Reports the Enabled/Disabled status of the ClkPump. 8195 * 8196 * \return Boolean status of ClkPump: true - Enabled, false - Disabled. 8197 * 8198 * \funcusage 8199 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable 8200 * 8201 * \note 8202 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 8203 * 8204 *******************************************************************************/ 8205 bool Cy_SysClk_ClkPumpIsEnabled(void); 8206 8207 8208 /******************************************************************************* 8209 * Function Name: Cy_SysClk_ClkPumpDisable 8210 ****************************************************************************//** 8211 * 8212 * Disables the pump clock (clk_pump). 8213 * 8214 * \funcusage 8215 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable 8216 * 8217 * \note 8218 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 8219 * 8220 *******************************************************************************/ 8221 void Cy_SysClk_ClkPumpDisable(void); 8222 8223 8224 /******************************************************************************* 8225 * Function Name: Cy_SysClk_ClkPumpGetFrequency 8226 ****************************************************************************//** 8227 * 8228 * Reports the frequency of the pump clock (clk_pump). 8229 * \note If the the pump clock is not enabled - a zero frequency is reported. 8230 * 8231 * \funcusage 8232 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable 8233 * 8234 * \note 8235 * This API is available for CAT1A (excluding TVIIBE) and CAT1B devices. 8236 * 8237 *******************************************************************************/ 8238 uint32_t Cy_SysClk_ClkPumpGetFrequency(void); 8239 /** \} group_sysclk_clk_pump_funcs */ 8240 #endif /* defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) */ 8241 8242 /* ========================================================================== */ 8243 /* ========================== clk_bak SECTION ========================= */ 8244 /* ========================================================================== */ 8245 /** 8246 * \addtogroup group_sysclk_clk_bak_enums 8247 * \{ 8248 */ 8249 /** 8250 * Backup domain clock (clk_bak) input sources. See BACKUP->CTL register, 8251 * CLK_SEL bits. Used with functions \ref Cy_SysClk_ClkBakSetSource, and 8252 * \ref Cy_SysClk_ClkBakGetSource. 8253 */ 8254 typedef enum 8255 { 8256 CY_SYSCLK_BAK_IN_WCO, /**< Backup domain clock input is WCO */ 8257 CY_SYSCLK_BAK_IN_CLKLF, /**< Backup domain clock input is clkLf */ 8258 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) || defined (CY_IP_MXS22SRSS) 8259 /** 8260 * \note 8261 * This parameter is available for CAT1A (TVIIBE only), CAT1B and CAT1C devices. 8262 **/ 8263 CY_SYSCLK_BAK_IN_ILO, /**< Backup domain clock input is ILO */ 8264 #if defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) 8265 /** 8266 * \note 8267 * This parameter is available for CAT1B and CAT1C devices. 8268 **/ 8269 CY_SYSCLK_BAK_IN_LPECO_PRESCALER, /**< Backup domain clock input is LPECO_PRESCALER */ 8270 #endif 8271 /** 8272 * \note 8273 * This parameter is available for CAT1B and CAT1D devices. 8274 **/ 8275 CY_SYSCLK_BAK_IN_PILO /**< Backup domain clock input is PILO */ 8276 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3), CY_IP_MXS22SRSS */ 8277 8278 } cy_en_clkbak_in_sources_t; 8279 /** \} group_sysclk_clk_bak_enums */ 8280 8281 8282 /** 8283 * \addtogroup group_sysclk_clk_bak_funcs 8284 * \{ 8285 */ 8286 /******************************************************************************* 8287 * Function Name: Cy_SysClk_ClkBakSetSource 8288 ****************************************************************************//** 8289 * 8290 * Sets the source for the backup domain clock (clk_bak). 8291 * 8292 * \param source \ref cy_en_clkbak_in_sources_t 8293 * 8294 * \note 8295 * clkLf is not available in all power modes. For this reason, WCO is the 8296 * preferred source. If the WCO is routed through the clkLf multiplexer 8297 * (see \ref Cy_SysClk_ClkLfSetSource), select WCO directly - do not select clkLf. 8298 * 8299 * \funcusage 8300 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource 8301 * 8302 *******************************************************************************/ 8303 void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source); 8304 8305 8306 /******************************************************************************* 8307 * Function Name: Cy_SysClk_ClkBakGetSource 8308 ****************************************************************************//** 8309 * 8310 * Reports the source for the backup domain clock (clk_bak). 8311 * 8312 * \return \ref cy_en_clkbak_in_sources_t 8313 * 8314 * \funcusage 8315 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource 8316 * 8317 *******************************************************************************/ 8318 cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void); 8319 /** \} group_sysclk_clk_bak_funcs */ 8320 8321 8322 /** \cond */ 8323 /* Deprecated macros */ 8324 #define CY_SYSCLK_DIV_ROUND(a, b) (CY_SYSLIB_DIV_ROUND((a),(b))) 8325 #define CY_SYSCLK_DIV_ROUNDUP(a, b) (CY_SYSLIB_DIV_ROUNDUP((a),(b))) 8326 /** \endcond */ 8327 8328 /* ========================================================================== */ 8329 /* ========================== Clock Power SECTION =============================*/ 8330 /* ========================================================================== */ 8331 /** 8332 * \addtogroup group_sysclk_clk_pwr_enums 8333 * \{ 8334 */ 8335 #if (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) || defined(CY_DOXYGEN) 8336 /** 8337 * \note 8338 * This Enumeration is only available for CAT1B(B2) devices. 8339 **/ 8340 /** 8341 * Clock power input sources. See PWRMODE_CLK_SELECT register, PWR_MUX bits. 8342 * Used with functions \ref Cy_SysClk_ClkPwrSetSource, and \ref Cy_SysClk_ClkPwrGetSource. 8343 */ 8344 8345 typedef enum 8346 { 8347 CY_SYSCLK_CLKPWR_IN_IMO = 0U, /**< clkPwr is sourced by the internal main oscillator (IMO) */ 8348 CY_SYSCLK_CLKPWR_IN_IHO = 1U, /**< clkPwr is sourced by the internal high speed oscillator (IHO) */ 8349 } cy_en_clkpwr_in_sources_t; 8350 8351 /** \} group_sysclk_clk_pwr_enums */ 8352 8353 /** \cond internal */ 8354 #define CY_SYSCLK_CLKPWR_DIVIDER_MIN (1U) 8355 #define CY_SYSCLK_CLKPWR_DIVIDER_MAX (256U) 8356 #define CY_SYSCLK_IS_CLKPWR_DIVIDER_VALID(locDiv) ((CY_SYSCLK_CLKPWR_DIVIDER_MIN <= (locDiv)) && ((locDiv) <= CY_SYSCLK_CLKPWR_DIVIDER_MAX)) 8357 8358 #define CY_SYSCLK_IF_CLKPWR_SOURCE_VALID(pwrClkSrc) (((pwrClkSrc) == CY_SYSCLK_CLKPWR_IN_IMO) || \ 8359 ((pwrClkSrc) == CY_SYSCLK_CLKPWR_IN_IHO)) 8360 /** \endcond */ 8361 8362 /** 8363 * \addtogroup group_sysclk_clk_pwr_funcs 8364 * \{ 8365 */ 8366 /******************************************************************************* 8367 * Function Name: Cy_SysClk_ClkPwrSetDivider 8368 ****************************************************************************//** 8369 * 8370 * Sets the clock divider for Power clock. 8371 * 8372 * \param divider divider value between 1 and 256. 8373 * 8374 * \funcusage 8375 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetDivider 8376 * 8377 *******************************************************************************/ 8378 void Cy_SysClk_ClkPwrSetDivider(uint32_t divider); 8379 8380 /******************************************************************************* 8381 * Function Name: Cy_SysClk_ClkPwrGetDivider 8382 ****************************************************************************//** 8383 * 8384 * Returns the clock divider of Power clock. 8385 * 8386 * \return divider value in range 1..256. 8387 * 8388 * \funcusage 8389 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetDivider 8390 * 8391 *******************************************************************************/ 8392 uint32_t Cy_SysClk_ClkPwrGetDivider(void); 8393 8394 8395 /******************************************************************************* 8396 * Function Name: Cy_SysClk_ClkPwrGetFrequency 8397 ****************************************************************************//** 8398 * 8399 * Reports the output clock signal frequency of Power clock. 8400 * 8401 * \return The frequency, in Hz. 8402 * 8403 * \funcusage 8404 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetDivider 8405 * 8406 *******************************************************************************/ 8407 uint32_t Cy_SysClk_ClkPwrGetFrequency(void); 8408 8409 8410 /******************************************************************************* 8411 * Function Name: Cy_SysClk_ClkPwrSetSource 8412 ****************************************************************************//** 8413 * 8414 * Sets the source for the Power clock. 8415 * 8416 * \param source \ref cy_en_clkpwr_in_sources_t 8417 * 8418 * \funcusage 8419 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetSource 8420 * 8421 *******************************************************************************/ 8422 void Cy_SysClk_ClkPwrSetSource(cy_en_clkpwr_in_sources_t source); 8423 8424 8425 /******************************************************************************* 8426 * Function Name: Cy_SysClk_ClkPwrGetSource 8427 ****************************************************************************//** 8428 * 8429 * Reports the source for the Power clock. 8430 * 8431 * \return \ref cy_en_clkpwr_in_sources_t 8432 * 8433 * \funcusage 8434 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetSource 8435 * 8436 *******************************************************************************/ 8437 cy_en_clkpwr_in_sources_t Cy_SysClk_ClkPwrGetSource(void); 8438 /** \} group_sysclk_clk_pwr_funcs */ 8439 #endif 8440 8441 8442 #if defined(__cplusplus) 8443 } 8444 #endif /* __cplusplus */ 8445 8446 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) */ 8447 8448 #endif /* CY_SYSCLK_H */ 8449 8450 /** \} group_sysclk */ 8451 8452 8453 /* [] END OF FILE */ 8454
