Searched refs:ctrl (Results 1 – 5 of 5) sorted by relevance
| /hal_infineon-latest/mtb-pdl-cat1/drivers/include/ |
| D | cy_sar.h | 856 #define CY_SAR_SQCTRL(ctrl) (((ctrl) == CY_SAR_SWITCH_SEQ_CTRL_ENABLE) || ((ctrl) == CY… argument
1469 …uint32_t ctrl; /**< Control register settings (applies to all… member
1634 …SAR_SetSwitchSarSeqCtrl(SAR_Type *base, uint32_t switchMask, cy_en_sar_switch_sar_seq_ctrl_t ctrl);
1635 __STATIC_INLINE void Cy_SAR_SetVssaSarSeqCtrl(SAR_Type *base, cy_en_sar_switch_sar_seq_ctrl_t ctrl);
2398 __STATIC_INLINE void Cy_SAR_SetVssaSarSeqCtrl(SAR_Type *base, cy_en_sar_switch_sar_seq_ctrl_t ctrl) in Cy_SAR_SetVssaSarSeqCtrl() argument
2400 Cy_SAR_SetSwitchSarSeqCtrl(base, SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk, ctrl); in Cy_SAR_SetVssaSarSeqCtrl()
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| /hal_infineon-latest/mtb-hal-cat1/COMPONENT_CAT1B/include/ |
| D | cyhal_missing_pdl.h | 304 uint32_t ctrl; member
335 #define Cy_SAR_SetVssaSarSeqCtrl(base, ctrl) argument
347 #define Cy_SAR_SetSwitchSarSeqCtrl(base, switchMask, ctrl) argument
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| /hal_infineon-latest/mtb-pdl-cat1/drivers/source/ |
| D | cy_sar.c | 223 CY_ASSERT_L2(CY_SAR_CTRL(config->ctrl)); in Cy_SAR_Init()
234 SAR_CTRL(base) = (config->ctrl | SAR_CTRL_REFBUF_EN_Msk) & ~SAR_CTRL_ENABLED_Msk; in Cy_SAR_Init()
243 …vrefNegSelect = ((uint32_t)CY_SAR_NEG_SEL_VREF == (config->ctrl & SAR_CTRL_NEG_SEL_Msk))? true : f… in Cy_SAR_Init()
1506 …_SAR_SetSwitchSarSeqCtrl(SAR_Type *base, uint32_t switchMask, cy_en_sar_switch_sar_seq_ctrl_t ctrl) in Cy_SAR_SetSwitchSarSeqCtrl() argument
1509 CY_ASSERT_L3(CY_SAR_SQCTRL(ctrl)); in Cy_SAR_SetSwitchSarSeqCtrl()
1511 switch(ctrl) in Cy_SAR_SetSwitchSarSeqCtrl()
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| /hal_infineon-latest/XMCLib/drivers/src/ |
| D | xmc_eth_mac.c | 391 uint32_t ctrl; in XMC_ETH_MAC_SendFrame() local
435 ctrl = eth_mac->tx_desc[eth_mac->tx_index].status | ETH_MAC_DMA_TDES0_CIC; in XMC_ETH_MAC_SendFrame()
436 ctrl &= ~(ETH_MAC_DMA_TDES0_IC | ETH_MAC_DMA_TDES0_TTSE); in XMC_ETH_MAC_SendFrame()
440 ctrl |= ETH_MAC_DMA_TDES0_IC; in XMC_ETH_MAC_SendFrame()
445 ctrl |= ETH_MAC_DMA_TDES0_TTSE; in XMC_ETH_MAC_SendFrame()
449 eth_mac->tx_desc[eth_mac->tx_index].status = ctrl | ETH_MAC_DMA_TDES0_OWN; in XMC_ETH_MAC_SendFrame()
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| /hal_infineon-latest/mtb-hal-cat1/source/ |
| D | cyhal_adc_sar.c | 919 uint32_t ctrl = _CYHAL_ADC_DEFAULT_CTRL; in _cyhal_adc_populate_pdl_config() local
920 ctrl |= (uint32_t)_cyhal_adc_convert_vref(hal_config->vref); in _cyhal_adc_populate_pdl_config()
921 ctrl |= (hal_config->is_bypassed) ? CY_SAR_BYPASS_CAP_ENABLE : CY_SAR_BYPASS_CAP_DISABLE; in _cyhal_adc_populate_pdl_config()
922 …ctrl |= (hal_config->vneg == CYHAL_ADC_VNEG_VSSA) ? CY_SAR_NEG_SEL_VSSA_KELVIN : CY_SAR_NEG_SEL_VR… in _cyhal_adc_populate_pdl_config()
932 pdl_config->ctrl = ctrl; in _cyhal_adc_populate_pdl_config()
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