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Searched refs:cpuss_interrupts_dmac_1_IRQn (Results 1 – 25 of 265) sorted by relevance

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/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy8c4588azi_h676.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c4588azi_h685.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6244azq_s4d92.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6244fmi_s4d73.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6244fmi_s4d93.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6244fmq_s4d93.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245lqi_s3d72.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6244lqq_s4d92.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245azi_s3d02.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245azi_s3d12.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245azi_s3d42.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245azi_s3d62.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245fni_s3d11.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245fni_s3d41.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245fni_s3d71.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245lqi_s3d02.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245lqi_s3d12.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245lqi_s3d42.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6245lqi_s3d62.h132 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
281 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c4588azi_h675.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c4588azi_h686.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c4588azq_h686.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6244azi_s4d12.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6244azi_s4d62.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator
Dcy8c6244azi_s4d82.h136 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */
288 cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ enumerator

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