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Searched refs:clockDiv (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_tdm.c104 uint16_t clockDiv = config->clkDiv -1U; in Cy_AudioTDM_TX_Init() local
109 CY_ASSERT_L2(CY_TDM_IS_CLK_DIV_VALID(clockDiv)); in Cy_AudioTDM_TX_Init()
123 _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_DIV, clockDiv) | in Cy_AudioTDM_TX_Init()
156 uint16_t clockDiv = config->clkDiv - 1U; in Cy_AudioTDM_RX_Init() local
161 CY_ASSERT_L2(CY_TDM_IS_CLK_DIV_VALID(clockDiv)); in Cy_AudioTDM_RX_Init()
168 _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_DIV, clockDiv) | in Cy_AudioTDM_RX_Init()
Dcy_i2s.c60 uint32_t clockDiv = (uint32_t)config->clkDiv - 1U; in Cy_I2S_Init() local
62 CY_ASSERT_L2(CY_I2S_IS_CLK_DIV_VALID(clockDiv)); in Cy_I2S_Init()
72 REG_I2S_CLOCK_CTL(base) = _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, clockDiv) | in Cy_I2S_Init()
77 REG_I2S_CLOCK_CTL(base) = _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, clockDiv) | in Cy_I2S_Init()