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Searched refs:bit (Results 1 – 14 of 14) sorted by relevance

/hal_infineon-latest/core-lib/
DREADME.md14 * `CY_LO8`: Gets the lower 8 bits of a 16-bit value
15 * `CY_HI8`: Gets the upper 8 bits of a 16-bit value
16 * `CY_LO16`: Gets the lower 16 bits of a 32-bit value
17 * `CY_HI16`: Gets the upper 16 bits of a 32-bit value
18 * `CY_SWAP_ENDIAN16`: Swaps the byte ordering of a 16-bit value
19 * `CY_SWAP_ENDIAN32`: Swaps the byte ordering of a 32-bit value
20 * `CY_SWAP_ENDIAN64`: Swaps the byte ordering of a 64-bit value
21 * `CY_GET_REG8`: Reads the 8-bit value from the specified address
22 * `CY_SET_REG8`: Writes an 8-bit value to the specified address
23 * `CY_GET_REG16`: Reads the 16-bit value from the specified address
[all …]
DRELEASE.md10 * CY_LO8: Gets the lower 8 bits of a 16-bit value
11 * CY_HI8: Gets the upper 8 bits of a 16-bit value
12 * CY_LO16: Gets the lower 16 bits of a 32-bit value
13 * CY_HI16: Gets the upper 16 bits of a 32-bit value
14 * CY_SWAP_ENDIAN16: Swaps the byte ordering of a 16-bit value
15 * CY_SWAP_ENDIAN32: Swaps the byte ordering of a 32-bit value
16 * CY_SWAP_ENDIAN64: Swaps the byte ordering of a 64-bit value
17 * CY_GET_REG8: Reads the 8-bit value from the specified address
18 * CY_SET_REG8: Writes an 8-bit value to the specified address
19 * CY_GET_REG16: Reads the 16-bit value from the specified address
[all …]
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_irq_impl.c70 for(uint16_t bit = start_bit; bit < start_bit + _CYHAL_IRQ_PRIO_BITS; ++bit) in _cyhal_system_irq_lookup_priority() local
72 uint16_t byte = bit / 8u; in _cyhal_system_irq_lookup_priority()
73 uint8_t bit_in_byte = bit % 8u; in _cyhal_system_irq_lookup_priority()
74 uint8_t offset = bit - start_bit; in _cyhal_system_irq_lookup_priority()
85 for(uint16_t bit = start_bit; bit < start_bit + _CYHAL_IRQ_PRIO_BITS; ++bit) in _cyhal_system_irq_store_priority() local
87 uint16_t byte = bit / 8u; in _cyhal_system_irq_store_priority()
88 uint8_t bit_in_byte = bit % 8u; in _cyhal_system_irq_store_priority()
89 uint8_t offset = bit - start_bit; in _cyhal_system_irq_store_priority()
Dcyhal_hwmgr.c136 uint8_t bit = bitPosition & CY_BIT_NUM_MASK; in _cyhal_is_set() local
137 *isSet = (used[byte] & (1 << bit)); in _cyhal_is_set()
149 uint8_t bit = bitPosition & CY_BIT_NUM_MASK; in _cyhal_set_bit() local
150 used[byte] |= (1 << bit); in _cyhal_set_bit()
162 uint8_t bit = bitPosition & CY_BIT_NUM_MASK; in _cyhal_clear_bit() local
163 used[byte] &= ~(1 << bit); in _cyhal_clear_bit()
Dcyhal_lptimer.c343 int bit = 0; in _cyhal_lptimer_get_toggle_bit() local
346 bit++; in _cyhal_lptimer_get_toggle_bit()
349 return bit - 1; in _cyhal_lptimer_get_toggle_bit()
/hal_infineon-latest/mtb-pdl-cat1/
DRELEASE.md66 …/www.infineon.com/cms/en/product/microcontroller/32-bit-psoc-arm-cortex-microcontroller/psoc-6-32-…
68 * [TV-II-BH8/BH4](https://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-t2g-arm-cor…
69 * [TV-II-BE4/BE2/BE1/BE512K](https://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-…
70 …/www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-t2g-arm-cortex-microcontroller/32-b…
71 …infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-cortex-…
DREADME.md19 The PDL reduces the need to understand register usage and bit structures,
39 …/www.infineon.com/cms/en/product/microcontroller/32-bit-psoc-arm-cortex-microcontroller/psoc-6-32-…
41 * [TV-II-BH8/BH4/BE](https://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-t2g-arm-…
42 * [XMC7000](https://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroll…
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_mcwdt.h599 #define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit)) argument
636 __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit);
1260 __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit) in Cy_MCWDT_SetToggleBit() argument
1262 CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit)); in Cy_MCWDT_SetToggleBit()
1264 MCWDT_CTR2_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CTR2_CONFIG(base), MCWDT_CTR2_CONFIG_BITS, bit); in Cy_MCWDT_SetToggleBit()
1266 …MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit); in Cy_MCWDT_SetToggleBit()
Dcy_smif.h1427 uint8_t Cy_SMIF_GetTapNumCapturedCorrectDLP(SMIF_Type *base, uint8_t bit);
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/
Dstartup_cm0plus.s106 …; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 co…
109 … or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/
Dstartup_cm0plus.s169 ; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
172 ; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/
Dcy_syslib_ext.s66 ; enable bit with interrupts still enabled. The test and set of the interrupt
/hal_infineon-latest/btstack-integration/COMPONENT_BTSS-IPC/
DREADME.md27 …et the BLE controller the Porting layer will assert and desserts the reset bit in the group 3 IP(B…
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_smif.c2617 uint8_t Cy_SMIF_GetTapNumCapturedCorrectDLP(SMIF_Type *base, uint8_t bit) in Cy_SMIF_GetTapNumCapturedCorrectDLP() argument
2621 switch(bit) in Cy_SMIF_GetTapNumCapturedCorrectDLP()