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Searched refs:_cyhal_utils_peri_pclk_set_divider (Results 1 – 7 of 7) sorted by relevance

/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_pwm.c201 result = _cyhal_utils_peri_pclk_set_divider(pclk, &(obj->tcpwm.clock), div - 1); in _cyhal_pwm_update_clock_freq()
255 … CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_set_divider(pclk, &(obj->tcpwm.clock), div - 1) || in _cyhal_pwm_init_clock()
Dcyhal_timer.c311 …if(CY_RSLT_SUCCESS == _cyhal_utils_peri_pclk_set_divider(clk_dst, &obj->tcpwm.clock, (divider - 1)… in cyhal_timer_set_frequency()
Dcyhal_quaddec.c117 … if (_cyhal_utils_peri_pclk_set_divider(clk_dst, &tcpwm->clock, (divider - 1)) == CY_RSLT_SUCCESS) in _cyhal_quaddec_configure_clock()
Dcyhal_usb_dev.c357 … status = _cyhal_utils_peri_pclk_set_divider(PCLK_USB_CLOCK_DEV_BRS, &(obj->clock), div_value); in _cyhal_usb_dev_peri_clock_setup()
Dcyhal_clock.c3017 … ? _cyhal_utils_peri_pclk_set_divider(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock, (div - 1)) in _cyhal_clock_set_frequency_peripheral()
3051 …? _cyhal_utils_peri_pclk_set_divider(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock, divider - … in _cyhal_clock_set_divider_peripheral()
Dcyhal_adc_sar.c1186 … (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_set_divider(pclk, &(obj->clock), div - 1)) || in _cyhal_adc_config_hw()
/hal_infineon-latest/mtb-hal-cat1/include_pvt/
Dcyhal_utils_impl.h253 static inline cy_rslt_t _cyhal_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest, const cyhal_clock… in _cyhal_utils_peri_pclk_set_divider() function