1 /** 2 * @file xmc_eth_mac_map.h 3 * @date 2015-06-20 4 * 5 * @cond 6 ********************************************************************************************************************* 7 * XMClib v2.1.24 - XMC Peripheral Driver Library 8 * 9 * Copyright (c) 2015-2019, Infineon Technologies AG 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 13 * following conditions are met: 14 * 15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials provided with the distribution. 20 * 21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 22 * products derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 33 * Infineon Technologies AG dave@infineon.com). 34 ********************************************************************************************************************* 35 * 36 * Change History 37 * -------------- 38 * 39 * 2015-06-20: 40 * - Initial <br> 41 * 42 * @endcond 43 */ 44 45 #ifndef XMC_ETH_MAC_MAP_H 46 #define XMC_ETH_MAC_MAP_H 47 48 /** 49 * ETH MAC interface mode 50 */ 51 typedef enum XMC_ETH_MAC_PORT_CTRL_MODE 52 { 53 XMC_ETH_MAC_PORT_CTRL_MODE_MII = 0x0U, /**< MII mode */ 54 XMC_ETH_MAC_PORT_CTRL_MODE_RMII = 0x1U /**< RMII mode */ 55 } XMC_ETH_MAC_PORT_CTRL_MODE_t; 56 57 /** 58 * ETH MAC receive data 0 line 59 */ 60 typedef enum XMC_ETH_MAC_PORT_CTRL_RXD0 61 { 62 XMC_ETH_MAC_PORT_CTRL_RXD0_P2_2 = 0U, /**< RXD0A receive data line */ 63 XMC_ETH_MAC_PORT_CTRL_RXD0_P0_2 = 1U, /**< RXD0B receive data line */ 64 XMC_ETH_MAC_PORT_CTRL_RXD0_P14_8 = 2U, /**< RXD0C receive data line */ 65 XMC_ETH_MAC_PORT_CTRL_RXD0_P5_0 = 3U /**< RXD0D receive data line */ 66 } XMC_ETH_MAC_PORT_CTRL_RXD0_t; 67 68 /** 69 * ETH MAC receive data 1 line 70 */ 71 typedef enum XMC_ETH_MAC_PORT_CTRL_RXD1 72 { 73 XMC_ETH_MAC_PORT_CTRL_RXD1_P2_3 = 0U, /**< RXD1A receive data line */ 74 XMC_ETH_MAC_PORT_CTRL_RXD1_P0_3 = 1U, /**< RXD1B receive data line */ 75 XMC_ETH_MAC_PORT_CTRL_RXD1_P14_9 = 2U, /**< RXD1C receive data line */ 76 XMC_ETH_MAC_PORT_CTRL_RXD1_P5_1 = 3U /**< RXD1D receive data line */ 77 } XMC_ETH_MAC_PORT_CTRL_RXD1_t; 78 79 /** 80 * ETH MAC receive data 2 line 81 */ 82 typedef enum XMC_ETH_MAC_PORT_CTRL_RXD2 83 { 84 XMC_ETH_MAC_PORT_CTRL_RXD2_P5_8 = 0U, /**< RXD2A receive data line */ 85 XMC_ETH_MAC_PORT_CTRL_RXD2_P6_4 = 1U /**< RXD2B receive data line */ 86 } XMC_ETH_MAC_PORT_CTRL_RXD2_t; 87 88 /** 89 * ETH MAC receive data 3 line 90 */ 91 typedef enum XMC_ETH_MAC_PORT_CTRL_RXD3 92 { 93 XMC_ETH_MAC_PORT_CTRL_RXD3_P5_9 = 0U, /**< RXD3A Receive data line */ 94 XMC_ETH_MAC_PORT_CTRL_RXD3_P6_3 = 1U /**< RXD3B Receive data line */ 95 } XMC_ETH_MAC_PORT_CTRL_RXD3_t; 96 97 /** 98 * ETH MAC PHY clock 99 */ 100 typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_RMII 101 { 102 XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P2_1 = 0U, /**< XMC_ETH_RMIIA PHY clock */ 103 XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P0_0 = 1U, /**< XMC_ETH_RMIIB PHY clock */ 104 XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P15_8 = 2U, /**< XMC_ETH_RMIIC PHY clock */ 105 XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P6_5 = 3U /**< XMC_ETH_RMIID PHY clock */ 106 } XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t; 107 108 /** 109 * ETH MAC carrier sense data valid 110 */ 111 typedef enum XMC_ETH_MAC_PORT_CTRL_CRS_DV 112 { 113 XMC_ETH_MAC_PORT_CTRL_CRS_DV_P2_5 = 0U, /**< XMC_ETH_CRS_DVA carrier sense data valid */ 114 XMC_ETH_MAC_PORT_CTRL_CRS_DV_P0_1 = 1U, /**< XMC_ETH_CRS_DVB carrier sense data valid */ 115 XMC_ETH_MAC_PORT_CTRL_CRS_DV_P15_9 = 2U, /**< XMC_ETH_CRS_DVC carrier sense data valid */ 116 XMC_ETH_MAC_PORT_CTRL_CRS_DV_P5_2 = 3U /**< XMC_ETH_CRS_DVD carrier sense data valid */ 117 } XMC_ETH_MAC_PORT_CTRL_CRS_DV_t; 118 119 /** 120 * ETH MAC carrier sense 121 */ 122 typedef enum XMC_ETH_MAC_PORT_CTRL_CRS 123 { 124 XMC_ETH_MAC_PORT_CTRL_CRS_P5_11 = 0U, /**< XMC_ETH_CRSA carrier sense */ 125 XMC_ETH_MAC_PORT_CTRL_CRS_P5_4 = 3U /**< XMC_ETH_CRSD carrier sense */ 126 } XMC_ETH_MAC_PORT_CTRL_CRS_t; 127 128 /** 129 * ETH MAC receive error 130 */ 131 typedef enum XMC_ETH_MAC_PORT_CTRL_RXER 132 { 133 XMC_ETH_MAC_PORT_CTRL_RXER_P2_4 = 0U, /**< XMC_ETH_RXERA carrier sense */ 134 XMC_ETH_MAC_PORT_CTRL_RXER_P0_11 = 1U, /**< XMC_ETH_RXERB carrier sense */ 135 XMC_ETH_MAC_PORT_CTRL_RXER_P5_3 = 3U /**< XMC_ETH_RXERD carrier sense */ 136 } XMC_ETH_MAC_PORT_CTRL_RXER_t; 137 138 /** 139 * ETH MAC collision detection 140 */ 141 typedef enum XMC_ETH_MAC_PORT_CTRL_COL 142 { 143 XMC_ETH_MAC_PORT_CTRL_COL_P2_15 = 0U, /**< XMC_ETH_COLA collision detection */ 144 XMC_ETH_MAC_PORT_CTRL_COL_P5_5 = 3U /**< XMC_ETH_COLD collision detection */ 145 } XMC_ETH_MAC_PORT_CTRL_COL_t; 146 147 /** 148 * ETH PHY transmit clock 149 */ 150 typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_TX 151 { 152 XMC_ETH_MAC_PORT_CTRL_CLK_TX_P5_10 = 0U, /**< XMC_ETH_CLK_TXA PHY transmit clock */ 153 XMC_ETH_MAC_PORT_CTRL_CLK_TX_P6_6 = 1U /**< XMC_ETH_CLK_TXB PHY transmit clock */ 154 } XMC_ETH_MAC_PORT_CTRL_CLK_TX_t; 155 156 /** 157 * ETH management data I/O 158 */ 159 typedef enum XMC_ETH_MAC_PORT_CTRL_MDIO 160 { 161 XMC_ETH_MAC_PORT_CTRL_MDIO_P0_9 = 0U, /**< XMC_ETH_MDIOA management data I/O */ 162 XMC_ETH_MAC_PORT_CTRL_MDIO_P2_0 = 1U, /**< XMC_ETH_MDIOB management data I/O */ 163 XMC_ETH_MAC_PORT_CTRL_MDIO_P1_11 = 2U /**< XMC_ETH_MDIOC management data I/O */ 164 } XMC_ETH_MAC_PORT_CTRL_MDIO_t; 165 166 #endif 167
