1 /***************************************************************************//** 2 * \file cyip_mxs40usbhsdev.h 3 * 4 * \brief 5 * MXS40USBHSDEV IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_MXS40USBHSDEV_H_ 28 #define _CYIP_MXS40USBHSDEV_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * MXS40USBHSDEV 34 *******************************************************************************/ 35 36 #define USBHSDEV_SECTION_SIZE 0x00009400UL 37 #define USBHSPHY_SECTION_SIZE 0x00000100UL 38 #define MXS40USBHSDEV_SECTION_SIZE 0x0000A000UL 39 40 /** 41 * \brief USB 2.0 Device Controller Registers (MXS40USBHSDEV_USBHSDEV) 42 */ 43 typedef struct { 44 __IOM uint32_t MMIO_EPM_EGRS_SRAM[4096]; /*!< 0x00000000 EPM MMIO Egress SRAM */ 45 __IOM uint32_t MMIO_EPM_IGRS_SRAM[4096]; /*!< 0x00004000 EPM MMIO Ingress SRAM */ 46 __IM uint32_t RESERVED[1024]; 47 __IOM uint32_t DEV_CS; /*!< 0x00009000 Device controller Master Control and Status */ 48 __IM uint32_t DEV_FRAMECNT; /*!< 0x00009004 FRAMECNT register */ 49 __IOM uint32_t DEV_PWR_CS; /*!< 0x00009008 Power management control and status */ 50 __IM uint32_t DEV_SETUPDAT_0; /*!< 0x0000900C SETUPDAT0 register */ 51 __IM uint32_t DEV_SETUPDAT_1; /*!< 0x00009010 SETUPDAT1 register */ 52 __IOM uint32_t DEV_TOGGLE; /*!< 0x00009014 Data toggle for endpoints */ 53 __IOM uint32_t DEV_EPI_CS[16]; /*!< 0x00009018 IN Endpoint Control and Status register */ 54 __IOM uint32_t DEV_EPI_XFER_CNT[16]; /*!< 0x00009058 IN Endpoint remaining transfer length register */ 55 __IOM uint32_t DEV_EPO_CS[16]; /*!< 0x00009098 OUT Endpoint Control and Status */ 56 __IOM uint32_t DEV_EPO_XFER_CNT[16]; /*!< 0x000090D8 OUT Endpoint remaining transfer length register */ 57 __IOM uint32_t DEV_CTL_INTR_MASK; /*!< 0x00009118 CONTROL interrupt mask register */ 58 __IOM uint32_t DEV_CTL_INTR; /*!< 0x0000911C CONTROL interrupt request register */ 59 __IM uint32_t DEV_CTL_INTR_MASKED; /*!< 0x00009120 CONTROL interrupt masked register */ 60 __IOM uint32_t DEV_CTL_INTR_SET; /*!< 0x00009124 CONTROL interrupt set register */ 61 __IOM uint32_t DEV_EP_INTR_MASK; /*!< 0x00009128 USB EP interrupt mask register */ 62 __IOM uint32_t DEV_EP_INTR; /*!< 0x0000912C USB EP interrupt request register */ 63 __IM uint32_t DEV_EP_INTR_MASKED; /*!< 0x00009130 USB EP interrupt masked register */ 64 __IOM uint32_t DEV_EP_INTR_SET; /*!< 0x00009134 USB EP interrupt set register */ 65 __IOM uint32_t DEV_EP_INGRS_INTR_MASK; /*!< 0x00009138 USB EP INGRS interrupt mask register */ 66 __IOM uint32_t DEV_EP_INGRS_INTR; /*!< 0x0000913C USB EP INGRS interrupt request register */ 67 __IM uint32_t DEV_EP_INGRS_INTR_MASKED; /*!< 0x00009140 USB EP INGRS interrupt masked register */ 68 __IOM uint32_t DEV_EP_INGRS_INTR_SET; /*!< 0x00009144 USB EP INGRS interrupt set register */ 69 __IOM uint32_t DEV_EP_EGRS_REQ; /*!< 0x00009148 USB EP Egress Request register */ 70 __IOM uint32_t DEV_EP_EGRS_INTR_MASK; /*!< 0x0000914C USB EP EGRS interrupt mask register */ 71 __IOM uint32_t DEV_EP_EGRS_INTR; /*!< 0x00009150 USB EP EGRS interrupt request register */ 72 __IM uint32_t DEV_EP_EGRS_INTR_MASKED; /*!< 0x00009154 USB EP EGRS interrupt masked register */ 73 __IOM uint32_t DEV_EP_EGRS_INTR_SET; /*!< 0x00009158 USB EP EGRS interrupt set register */ 74 __IOM uint32_t POWER; /*!< 0x0000915C USB 2.0 Device Power, Clock & Reset Control Register */ 75 __IOM uint32_t DEV_LPM_ATTR; /*!< 0x00009160 USB 2.0 Device LPM Register */ 76 __IOM uint32_t DEV_LPM_TIM_1; /*!< 0x00009164 USB 2.0 Device LPM Timer Parameter Register */ 77 __IOM uint32_t DEV_CHIRP_OVERRIDE; /*!< 0x00009168 USB 2.0 Device Chirp Override Register */ 78 __IOM uint32_t DEV_TIM_T_DCHSE0; /*!< 0x0000916C USB 2.0 Device Init Timing 0 Register */ 79 __IOM uint32_t DEV_TIM_T_DETRST_FILT; /*!< 0x00009170 USB 2.0 Device Init Timing 1 Register */ 80 __IOM uint32_t DEV_TIM_T_WTFS; /*!< 0x00009174 USB 2.0 Device Init Timing 2 Register */ 81 __IOM uint32_t DEV_TIM_T_SUSP; /*!< 0x00009178 USB 2.0 Device Init Timing 3 Register */ 82 __IOM uint32_t DEV_TIM_T_WTRSTHS; /*!< 0x0000917C USB 2.0 Device Init Timing 4 Register */ 83 __IOM uint32_t DEV_TIM_T_UCH; /*!< 0x00009180 USB 2.0 Device Init Timing 5 Register */ 84 __IOM uint32_t DEV_TIM_T_WTREV_WTRSTFS; /*!< 0x00009184 USB 2.0 Device Init Timing 6 Register */ 85 __IOM uint32_t DDFT_CONFIG; /*!< 0x00009188 USB 2.0 DDFT Configuration Register */ 86 __IM uint32_t RESERVED1; 87 __IOM uint32_t DEV_LOOPBACK_CTRL; /*!< 0x00009190 USB 2.0 UTMI Loopback Control Register */ 88 __IOM uint32_t DEV_LOOPBACK_IN_REQ; /*!< 0x00009194 USB 2.0 UTMI Loopback IN Token Request Register */ 89 __IOM uint32_t DEV_LOOPBACK_OUT_REQ; /*!< 0x00009198 USB 2.0 UTMI Loopback OUT Token Request Register */ 90 __IM uint32_t RESERVED2[25]; 91 __IOM uint32_t EPM_CS; /*!< 0x00009200 EPM Control and Status Register */ 92 __IM uint32_t RESERVED3; 93 __IM uint32_t EEPM_DEBUG; /*!< 0x00009208 Egress EPM Debug Register */ 94 __IM uint32_t IEPM_DEBUG; /*!< 0x0000920C Ingress EPM Debug Register */ 95 __IM uint32_t IEPM_DEBUG_1; /*!< 0x00009210 Ingress EPM Debug 1 Register */ 96 __IM uint32_t IEPM_DEBUG_2; /*!< 0x00009214 Ingress EPM Debug 2 Register */ 97 __IM uint32_t RESERVED4[2]; 98 __IOM uint32_t EEPM_ENDPOINT[16]; /*!< 0x00009220 Egress EPM per Endpoint Control and Status */ 99 __IOM uint32_t IEPM_ENDPOINT[16]; /*!< 0x00009260 Ingress EPM Per Endpoint Control and Status */ 100 __IM uint32_t EEPM_DEBUG_ENDPOINT[16]; /*!< 0x000092A0 Egress EPM Per Endpoint Debug */ 101 __IM uint32_t IEPM_DEBUG_ENDPOINT[16]; /*!< 0x000092E0 Ingress EPM Per Endpoint Debug */ 102 __IOM uint32_t MMIO_EEPM_ENDPOINT[16]; /*!< 0x00009320 MMIO Egress EPM per Endpoint Control and Status */ 103 __IOM uint32_t MMIO_IEPM_ENDPOINT[16]; /*!< 0x00009360 MMIO Ingress EPM Per Endpoint Control and Status */ 104 __IOM uint32_t DEV_SPARE_1; /*!< 0x000093A0 DEV SPARE 1 Register */ 105 __IOM uint32_t DEV_SPARE_2; /*!< 0x000093A4 DEV SPARE 2 Register */ 106 __IOM uint32_t LEGACY_FEATURE_ENABLE; /*!< 0x000093A8 Legacy Feature Enable Register */ 107 __IM uint32_t DFT_OBSERVE; /*!< 0x000093AC DFT Observable Register */ 108 __IM uint32_t RESERVED5[20]; 109 } USBHSDEV_V1_Type; /*!< Size = 37888 (0x9400) */ 110 111 /** 112 * \brief USB 2.0 PHY Registers (MXS40USBHSDEV_USBHSPHY) 113 */ 114 typedef struct { 115 __IOM uint32_t AFE_CONTROL_1; /*!< 0x00000000 AFE Control register #1 */ 116 __IOM uint32_t AFE_CONTROL_2; /*!< 0x00000004 AFE Control register #2 */ 117 __IOM uint32_t UTMI_CONTROL; /*!< 0x00000008 UTMI Control register */ 118 __IOM uint32_t CDR_CONTROL; /*!< 0x0000000C CDR registers */ 119 __IOM uint32_t BC_CONTROL; /*!< 0x00000010 UHC Battery Charging CSR Bank */ 120 __IOM uint32_t PLL_CONTROL_1; /*!< 0x00000014 Primary PLL control register#1 */ 121 __IOM uint32_t PLL_CONTROL_2; /*!< 0x00000018 Primary PLL control register#2 */ 122 __IOM uint32_t TEST_PLL_CONTROL; /*!< 0x0000001C Test PLL control register */ 123 __IOM uint32_t TEST_CONTROL; /*!< 0x00000020 Test control register */ 124 __IOM uint32_t DDFT_CFG; /*!< 0x00000024 DDFT configuration */ 125 __IOM uint32_t DIGITAL_CONTROL; /*!< 0x00000028 Provides control and configuration to digital blocks */ 126 __IOM uint32_t VREFGEN_CONTROL; /*!< 0x0000002C VREFGEN control */ 127 __IOM uint32_t REG_SW_1P2_CONTROL; /*!< 0x00000030 REG_SW_1P2 control */ 128 __IOM uint32_t REG_1P1_CONTROL; /*!< 0x00000034 REG_1P1 control */ 129 __IOM uint32_t REG_2P5_CONTROL; /*!< 0x00000038 REG_2P5_ control */ 130 __IOM uint32_t IREFGEN_CONTROL; /*!< 0x0000003C IREFGEN_ control */ 131 __IM uint32_t STATUS; /*!< 0x00000040 Status */ 132 __IOM uint32_t INTR0; /*!< 0x00000044 INTR0 Cause. These are the wakeup interrupts get reflected on 133 interrupt_wakeup pin. */ 134 __IOM uint32_t INTR0_SET; /*!< 0x00000048 INTR0 Set */ 135 __IOM uint32_t INTR0_MASK; /*!< 0x0000004C INTR0 Mask */ 136 __IM uint32_t INTR0_MASKED; /*!< 0x00000050 INTR0 Masked */ 137 __IOM uint32_t SPARE; /*!< 0x00000054 Spare */ 138 __IOM uint32_t AFE_CONTROL_3; /*!< 0x00000058 AFE Control register #3 */ 139 __IOM uint32_t AFE_CONTROL_4; /*!< 0x0000005C AFE Control register #4 */ 140 __IOM uint32_t UTMI_CONTROL_2; /*!< 0x00000060 UTMI Configurtation Registers */ 141 __IM uint32_t RESERVED[35]; 142 __IOM uint32_t PLL_TRIMS; /*!< 0x000000F0 Trim register for the PLL */ 143 __IOM uint32_t AFE_TRIMS; /*!< 0x000000F4 Trim register for the AFE */ 144 __IM uint32_t RESERVED1[2]; 145 } USBHSPHY_V1_Type; /*!< Size = 256 (0x100) */ 146 147 /** 148 * \brief USB 2 Device Controller Memory Register Map (MXS40USBHSDEV) 149 */ 150 typedef struct { 151 USBHSDEV_V1_Type USBHSDEV; /*!< 0x00000000 USB 2.0 Device Controller Registers */ 152 __IM uint32_t RESERVED[256]; 153 USBHSPHY_V1_Type USBHSPHY; /*!< 0x00009800 USB 2.0 PHY Registers */ 154 } MXS40USBHSDEV_V1_Type; /*!< Size = 39168 (0x9900) */ 155 156 157 /* MXS40USBHSDEV_USBHSDEV.MMIO_EPM_EGRS_SRAM */ 158 #define USBHSDEV_MMIO_EPM_EGRS_SRAM_DATA_Pos 0UL 159 #define USBHSDEV_MMIO_EPM_EGRS_SRAM_DATA_Msk 0xFFFFFFFFUL 160 /* MXS40USBHSDEV_USBHSDEV.MMIO_EPM_IGRS_SRAM */ 161 #define USBHSDEV_MMIO_EPM_IGRS_SRAM_DATA_Pos 0UL 162 #define USBHSDEV_MMIO_EPM_IGRS_SRAM_DATA_Msk 0xFFFFFFFFUL 163 /* MXS40USBHSDEV_USBHSDEV.DEV_CS */ 164 #define USBHSDEV_DEV_CS_ERR_LIMIT_Pos 0UL 165 #define USBHSDEV_DEV_CS_ERR_LIMIT_Msk 0xFFUL 166 #define USBHSDEV_DEV_CS_COUNT_Pos 8UL 167 #define USBHSDEV_DEV_CS_COUNT_Msk 0xFF00UL 168 #define USBHSDEV_DEV_CS_DEVICEADDR_Pos 16UL 169 #define USBHSDEV_DEV_CS_DEVICEADDR_Msk 0x7F0000UL 170 #define USBHSDEV_DEV_CS_TEST_MODE_Pos 23UL 171 #define USBHSDEV_DEV_CS_TEST_MODE_Msk 0x3800000UL 172 #define USBHSDEV_DEV_CS_SETUP_CLR_BUSY_Pos 26UL 173 #define USBHSDEV_DEV_CS_SETUP_CLR_BUSY_Msk 0x4000000UL 174 #define USBHSDEV_DEV_CS_CONT_TO_DATA_Pos 27UL 175 #define USBHSDEV_DEV_CS_CONT_TO_DATA_Msk 0x8000000UL 176 #define USBHSDEV_DEV_CS_NAKALL_Pos 31UL 177 #define USBHSDEV_DEV_CS_NAKALL_Msk 0x80000000UL 178 /* MXS40USBHSDEV_USBHSDEV.DEV_FRAMECNT */ 179 #define USBHSDEV_DEV_FRAMECNT_MICROFRAME_Pos 0UL 180 #define USBHSDEV_DEV_FRAMECNT_MICROFRAME_Msk 0x7UL 181 #define USBHSDEV_DEV_FRAMECNT_FRAMECNT_Pos 3UL 182 #define USBHSDEV_DEV_FRAMECNT_FRAMECNT_Msk 0x3FF8UL 183 /* MXS40USBHSDEV_USBHSDEV.DEV_PWR_CS */ 184 #define USBHSDEV_DEV_PWR_CS_SIGRSUME_Pos 0UL 185 #define USBHSDEV_DEV_PWR_CS_SIGRSUME_Msk 0x1UL 186 #define USBHSDEV_DEV_PWR_CS_NOSYNSOF_Pos 2UL 187 #define USBHSDEV_DEV_PWR_CS_NOSYNSOF_Msk 0x4UL 188 #define USBHSDEV_DEV_PWR_CS_DISCON_Pos 3UL 189 #define USBHSDEV_DEV_PWR_CS_DISCON_Msk 0x8UL 190 #define USBHSDEV_DEV_PWR_CS_DEV_SUSPEND_Pos 4UL 191 #define USBHSDEV_DEV_PWR_CS_DEV_SUSPEND_Msk 0x10UL 192 #define USBHSDEV_DEV_PWR_CS_FORCE_FS_Pos 6UL 193 #define USBHSDEV_DEV_PWR_CS_FORCE_FS_Msk 0x40UL 194 #define USBHSDEV_DEV_PWR_CS_HSM_Pos 7UL 195 #define USBHSDEV_DEV_PWR_CS_HSM_Msk 0x80UL 196 #define USBHSDEV_DEV_PWR_CS_L0_ACTIVE_Pos 8UL 197 #define USBHSDEV_DEV_PWR_CS_L0_ACTIVE_Msk 0x100UL 198 #define USBHSDEV_DEV_PWR_CS_L2_SUSPEND_Pos 9UL 199 #define USBHSDEV_DEV_PWR_CS_L2_SUSPEND_Msk 0x200UL 200 #define USBHSDEV_DEV_PWR_CS_L1_SLEEP_Pos 10UL 201 #define USBHSDEV_DEV_PWR_CS_L1_SLEEP_Msk 0x400UL 202 /* MXS40USBHSDEV_USBHSDEV.DEV_SETUPDAT_0 */ 203 #define USBHSDEV_DEV_SETUPDAT_0_SETUP_REQUEST_TYPE_Pos 0UL 204 #define USBHSDEV_DEV_SETUPDAT_0_SETUP_REQUEST_TYPE_Msk 0xFFUL 205 #define USBHSDEV_DEV_SETUPDAT_0_SETUP_REQUEST_Pos 8UL 206 #define USBHSDEV_DEV_SETUPDAT_0_SETUP_REQUEST_Msk 0xFF00UL 207 #define USBHSDEV_DEV_SETUPDAT_0_SETUP_VALUE_Pos 16UL 208 #define USBHSDEV_DEV_SETUPDAT_0_SETUP_VALUE_Msk 0xFFFF0000UL 209 /* MXS40USBHSDEV_USBHSDEV.DEV_SETUPDAT_1 */ 210 #define USBHSDEV_DEV_SETUPDAT_1_SETUP_INDEX_Pos 0UL 211 #define USBHSDEV_DEV_SETUPDAT_1_SETUP_INDEX_Msk 0xFFFFUL 212 #define USBHSDEV_DEV_SETUPDAT_1_SETUP_LENGTH_Pos 16UL 213 #define USBHSDEV_DEV_SETUPDAT_1_SETUP_LENGTH_Msk 0xFFFF0000UL 214 /* MXS40USBHSDEV_USBHSDEV.DEV_TOGGLE */ 215 #define USBHSDEV_DEV_TOGGLE_ENDPOINT_Pos 0UL 216 #define USBHSDEV_DEV_TOGGLE_ENDPOINT_Msk 0xFUL 217 #define USBHSDEV_DEV_TOGGLE_IO_Pos 4UL 218 #define USBHSDEV_DEV_TOGGLE_IO_Msk 0x10UL 219 #define USBHSDEV_DEV_TOGGLE_R_Pos 5UL 220 #define USBHSDEV_DEV_TOGGLE_R_Msk 0x20UL 221 #define USBHSDEV_DEV_TOGGLE_S_Pos 6UL 222 #define USBHSDEV_DEV_TOGGLE_S_Msk 0x40UL 223 #define USBHSDEV_DEV_TOGGLE_Q_Pos 7UL 224 #define USBHSDEV_DEV_TOGGLE_Q_Msk 0x80UL 225 #define USBHSDEV_DEV_TOGGLE_TOGGLE_VALID_Pos 8UL 226 #define USBHSDEV_DEV_TOGGLE_TOGGLE_VALID_Msk 0x100UL 227 /* MXS40USBHSDEV_USBHSDEV.DEV_EPI_CS */ 228 #define USBHSDEV_DEV_EPI_CS_PAYLOAD_Pos 0UL 229 #define USBHSDEV_DEV_EPI_CS_PAYLOAD_Msk 0x3FFUL 230 #define USBHSDEV_DEV_EPI_CS_TYPE_Pos 10UL 231 #define USBHSDEV_DEV_EPI_CS_TYPE_Msk 0xC00UL 232 #define USBHSDEV_DEV_EPI_CS_ISOINPKS_Pos 12UL 233 #define USBHSDEV_DEV_EPI_CS_ISOINPKS_Msk 0x3000UL 234 #define USBHSDEV_DEV_EPI_CS_VALID_Pos 14UL 235 #define USBHSDEV_DEV_EPI_CS_VALID_Msk 0x4000UL 236 #define USBHSDEV_DEV_EPI_CS_NAK_Pos 15UL 237 #define USBHSDEV_DEV_EPI_CS_NAK_Msk 0x8000UL 238 #define USBHSDEV_DEV_EPI_CS_STALL_Pos 16UL 239 #define USBHSDEV_DEV_EPI_CS_STALL_Msk 0x10000UL 240 #define USBHSDEV_DEV_EPI_CS_COMMIT_Pos 18UL 241 #define USBHSDEV_DEV_EPI_CS_COMMIT_Msk 0x40000UL 242 #define USBHSDEV_DEV_EPI_CS_BNAK_Pos 19UL 243 #define USBHSDEV_DEV_EPI_CS_BNAK_Msk 0x80000UL 244 #define USBHSDEV_DEV_EPI_CS_DONE_Pos 20UL 245 #define USBHSDEV_DEV_EPI_CS_DONE_Msk 0x100000UL 246 #define USBHSDEV_DEV_EPI_CS_ZERO_Pos 21UL 247 #define USBHSDEV_DEV_EPI_CS_ZERO_Msk 0x200000UL 248 #define USBHSDEV_DEV_EPI_CS_SHORT_Pos 22UL 249 #define USBHSDEV_DEV_EPI_CS_SHORT_Msk 0x400000UL 250 #define USBHSDEV_DEV_EPI_CS_ISOERR_Pos 23UL 251 #define USBHSDEV_DEV_EPI_CS_ISOERR_Msk 0x800000UL 252 #define USBHSDEV_DEV_EPI_CS_COMMIT_MASK_Pos 26UL 253 #define USBHSDEV_DEV_EPI_CS_COMMIT_MASK_Msk 0x4000000UL 254 #define USBHSDEV_DEV_EPI_CS_BNAK_MASK_Pos 27UL 255 #define USBHSDEV_DEV_EPI_CS_BNAK_MASK_Msk 0x8000000UL 256 #define USBHSDEV_DEV_EPI_CS_DONE_MASK_Pos 28UL 257 #define USBHSDEV_DEV_EPI_CS_DONE_MASK_Msk 0x10000000UL 258 #define USBHSDEV_DEV_EPI_CS_ZERO_MASK_Pos 29UL 259 #define USBHSDEV_DEV_EPI_CS_ZERO_MASK_Msk 0x20000000UL 260 #define USBHSDEV_DEV_EPI_CS_SHORT_MASK_Pos 30UL 261 #define USBHSDEV_DEV_EPI_CS_SHORT_MASK_Msk 0x40000000UL 262 #define USBHSDEV_DEV_EPI_CS_ISOERR_MASK_Pos 31UL 263 #define USBHSDEV_DEV_EPI_CS_ISOERR_MASK_Msk 0x80000000UL 264 /* MXS40USBHSDEV_USBHSDEV.DEV_EPI_XFER_CNT */ 265 #define USBHSDEV_DEV_EPI_XFER_CNT_BYTES_REMAINING_Pos 0UL 266 #define USBHSDEV_DEV_EPI_XFER_CNT_BYTES_REMAINING_Msk 0xFFFFFFFFUL 267 /* MXS40USBHSDEV_USBHSDEV.DEV_EPO_CS */ 268 #define USBHSDEV_DEV_EPO_CS_PAYLOAD_Pos 0UL 269 #define USBHSDEV_DEV_EPO_CS_PAYLOAD_Msk 0x3FFUL 270 #define USBHSDEV_DEV_EPO_CS_TYPE_Pos 10UL 271 #define USBHSDEV_DEV_EPO_CS_TYPE_Msk 0xC00UL 272 #define USBHSDEV_DEV_EPO_CS_ISOINPKS_Pos 12UL 273 #define USBHSDEV_DEV_EPO_CS_ISOINPKS_Msk 0x3000UL 274 #define USBHSDEV_DEV_EPO_CS_VALID_Pos 14UL 275 #define USBHSDEV_DEV_EPO_CS_VALID_Msk 0x4000UL 276 #define USBHSDEV_DEV_EPO_CS_NAK_Pos 15UL 277 #define USBHSDEV_DEV_EPO_CS_NAK_Msk 0x8000UL 278 #define USBHSDEV_DEV_EPO_CS_STALL_Pos 16UL 279 #define USBHSDEV_DEV_EPO_CS_STALL_Msk 0x10000UL 280 #define USBHSDEV_DEV_EPO_CS_OVF_Pos 17UL 281 #define USBHSDEV_DEV_EPO_CS_OVF_Msk 0x20000UL 282 #define USBHSDEV_DEV_EPO_CS_COMMIT_Pos 18UL 283 #define USBHSDEV_DEV_EPO_CS_COMMIT_Msk 0x40000UL 284 #define USBHSDEV_DEV_EPO_CS_BNAK_Pos 19UL 285 #define USBHSDEV_DEV_EPO_CS_BNAK_Msk 0x80000UL 286 #define USBHSDEV_DEV_EPO_CS_DONE_Pos 20UL 287 #define USBHSDEV_DEV_EPO_CS_DONE_Msk 0x100000UL 288 #define USBHSDEV_DEV_EPO_CS_ZERO_Pos 21UL 289 #define USBHSDEV_DEV_EPO_CS_ZERO_Msk 0x200000UL 290 #define USBHSDEV_DEV_EPO_CS_SHORT_Pos 22UL 291 #define USBHSDEV_DEV_EPO_CS_SHORT_Msk 0x400000UL 292 #define USBHSDEV_DEV_EPO_CS_ISOERR_Pos 23UL 293 #define USBHSDEV_DEV_EPO_CS_ISOERR_Msk 0x800000UL 294 #define USBHSDEV_DEV_EPO_CS_OVF_MASK_Pos 25UL 295 #define USBHSDEV_DEV_EPO_CS_OVF_MASK_Msk 0x2000000UL 296 #define USBHSDEV_DEV_EPO_CS_COMMIT_MASK_Pos 26UL 297 #define USBHSDEV_DEV_EPO_CS_COMMIT_MASK_Msk 0x4000000UL 298 #define USBHSDEV_DEV_EPO_CS_BNAK_MASK_Pos 27UL 299 #define USBHSDEV_DEV_EPO_CS_BNAK_MASK_Msk 0x8000000UL 300 #define USBHSDEV_DEV_EPO_CS_DONE_MASK_Pos 28UL 301 #define USBHSDEV_DEV_EPO_CS_DONE_MASK_Msk 0x10000000UL 302 #define USBHSDEV_DEV_EPO_CS_ZERO_MASK_Pos 29UL 303 #define USBHSDEV_DEV_EPO_CS_ZERO_MASK_Msk 0x20000000UL 304 #define USBHSDEV_DEV_EPO_CS_SHORT_MASK_Pos 30UL 305 #define USBHSDEV_DEV_EPO_CS_SHORT_MASK_Msk 0x40000000UL 306 #define USBHSDEV_DEV_EPO_CS_ISOERR_MASK_Pos 31UL 307 #define USBHSDEV_DEV_EPO_CS_ISOERR_MASK_Msk 0x80000000UL 308 /* MXS40USBHSDEV_USBHSDEV.DEV_EPO_XFER_CNT */ 309 #define USBHSDEV_DEV_EPO_XFER_CNT_BYTES_REMAINING_Pos 0UL 310 #define USBHSDEV_DEV_EPO_XFER_CNT_BYTES_REMAINING_Msk 0xFFFFFFFFUL 311 /* MXS40USBHSDEV_USBHSDEV.DEV_CTL_INTR_MASK */ 312 #define USBHSDEV_DEV_CTL_INTR_MASK_SETADDR_Pos 0UL 313 #define USBHSDEV_DEV_CTL_INTR_MASK_SETADDR_Msk 0x1UL 314 #define USBHSDEV_DEV_CTL_INTR_MASK_SOF_Pos 1UL 315 #define USBHSDEV_DEV_CTL_INTR_MASK_SOF_Msk 0x2UL 316 #define USBHSDEV_DEV_CTL_INTR_MASK_SUSP_Pos 2UL 317 #define USBHSDEV_DEV_CTL_INTR_MASK_SUSP_Msk 0x4UL 318 #define USBHSDEV_DEV_CTL_INTR_MASK_URESET_Pos 3UL 319 #define USBHSDEV_DEV_CTL_INTR_MASK_URESET_Msk 0x8UL 320 #define USBHSDEV_DEV_CTL_INTR_MASK_HSGRANT_Pos 4UL 321 #define USBHSDEV_DEV_CTL_INTR_MASK_HSGRANT_Msk 0x10UL 322 #define USBHSDEV_DEV_CTL_INTR_MASK_SUTOK_Pos 5UL 323 #define USBHSDEV_DEV_CTL_INTR_MASK_SUTOK_Msk 0x20UL 324 #define USBHSDEV_DEV_CTL_INTR_MASK_SUDAV_Pos 6UL 325 #define USBHSDEV_DEV_CTL_INTR_MASK_SUDAV_Msk 0x40UL 326 #define USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT_Pos 7UL 327 #define USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT_Msk 0x80UL 328 #define USBHSDEV_DEV_CTL_INTR_MASK_URESUME_Pos 8UL 329 #define USBHSDEV_DEV_CTL_INTR_MASK_URESUME_Msk 0x100UL 330 #define USBHSDEV_DEV_CTL_INTR_MASK_STATUS_STAGE_Pos 9UL 331 #define USBHSDEV_DEV_CTL_INTR_MASK_STATUS_STAGE_Msk 0x200UL 332 #define USBHSDEV_DEV_CTL_INTR_MASK_L1_SLEEP_REQ_Pos 10UL 333 #define USBHSDEV_DEV_CTL_INTR_MASK_L1_SLEEP_REQ_Msk 0x400UL 334 #define USBHSDEV_DEV_CTL_INTR_MASK_L1_URESUME_Pos 11UL 335 #define USBHSDEV_DEV_CTL_INTR_MASK_L1_URESUME_Msk 0x800UL 336 #define USBHSDEV_DEV_CTL_INTR_MASK_RESETDONE_Pos 12UL 337 #define USBHSDEV_DEV_CTL_INTR_MASK_RESETDONE_Msk 0x1000UL 338 #define USBHSDEV_DEV_CTL_INTR_MASK_HOST_URSUME_ARRIVED_Pos 13UL 339 #define USBHSDEV_DEV_CTL_INTR_MASK_HOST_URSUME_ARRIVED_Msk 0x2000UL 340 #define USBHSDEV_DEV_CTL_INTR_MASK_DPSLP_Pos 14UL 341 #define USBHSDEV_DEV_CTL_INTR_MASK_DPSLP_Msk 0x4000UL 342 #define USBHSDEV_DEV_CTL_INTR_MASK_PID_MISMATCH_ON_NAK_Pos 15UL 343 #define USBHSDEV_DEV_CTL_INTR_MASK_PID_MISMATCH_ON_NAK_Msk 0x8000UL 344 /* MXS40USBHSDEV_USBHSDEV.DEV_CTL_INTR */ 345 #define USBHSDEV_DEV_CTL_INTR_SETADDR_Pos 0UL 346 #define USBHSDEV_DEV_CTL_INTR_SETADDR_Msk 0x1UL 347 #define USBHSDEV_DEV_CTL_INTR_SOF_Pos 1UL 348 #define USBHSDEV_DEV_CTL_INTR_SOF_Msk 0x2UL 349 #define USBHSDEV_DEV_CTL_INTR_SUSP_Pos 2UL 350 #define USBHSDEV_DEV_CTL_INTR_SUSP_Msk 0x4UL 351 #define USBHSDEV_DEV_CTL_INTR_URESET_Pos 3UL 352 #define USBHSDEV_DEV_CTL_INTR_URESET_Msk 0x8UL 353 #define USBHSDEV_DEV_CTL_INTR_HSGRANT_Pos 4UL 354 #define USBHSDEV_DEV_CTL_INTR_HSGRANT_Msk 0x10UL 355 #define USBHSDEV_DEV_CTL_INTR_SUTOK_Pos 5UL 356 #define USBHSDEV_DEV_CTL_INTR_SUTOK_Msk 0x20UL 357 #define USBHSDEV_DEV_CTL_INTR_SUDAV_Pos 6UL 358 #define USBHSDEV_DEV_CTL_INTR_SUDAV_Msk 0x40UL 359 #define USBHSDEV_DEV_CTL_INTR_ERRLIMIT_Pos 7UL 360 #define USBHSDEV_DEV_CTL_INTR_ERRLIMIT_Msk 0x80UL 361 #define USBHSDEV_DEV_CTL_INTR_URESUME_Pos 8UL 362 #define USBHSDEV_DEV_CTL_INTR_URESUME_Msk 0x100UL 363 #define USBHSDEV_DEV_CTL_INTR_STATUS_STAGE_Pos 9UL 364 #define USBHSDEV_DEV_CTL_INTR_STATUS_STAGE_Msk 0x200UL 365 #define USBHSDEV_DEV_CTL_INTR_L1_SLEEP_REQ_Pos 10UL 366 #define USBHSDEV_DEV_CTL_INTR_L1_SLEEP_REQ_Msk 0x400UL 367 #define USBHSDEV_DEV_CTL_INTR_L1_URESUME_Pos 11UL 368 #define USBHSDEV_DEV_CTL_INTR_L1_URESUME_Msk 0x800UL 369 #define USBHSDEV_DEV_CTL_INTR_RESETDONE_Pos 12UL 370 #define USBHSDEV_DEV_CTL_INTR_RESETDONE_Msk 0x1000UL 371 #define USBHSDEV_DEV_CTL_INTR_HOST_URSUME_ARRIVED_Pos 13UL 372 #define USBHSDEV_DEV_CTL_INTR_HOST_URSUME_ARRIVED_Msk 0x2000UL 373 #define USBHSDEV_DEV_CTL_INTR_DPSLP_Pos 14UL 374 #define USBHSDEV_DEV_CTL_INTR_DPSLP_Msk 0x4000UL 375 #define USBHSDEV_DEV_CTL_INTR_PID_MISMATCH_ON_NAK_Pos 15UL 376 #define USBHSDEV_DEV_CTL_INTR_PID_MISMATCH_ON_NAK_Msk 0x8000UL 377 /* MXS40USBHSDEV_USBHSDEV.DEV_CTL_INTR_MASKED */ 378 #define USBHSDEV_DEV_CTL_INTR_MASKED_SETADDR_MASKED_Pos 0UL 379 #define USBHSDEV_DEV_CTL_INTR_MASKED_SETADDR_MASKED_Msk 0x1UL 380 #define USBHSDEV_DEV_CTL_INTR_MASKED_SOF_MASKED_Pos 1UL 381 #define USBHSDEV_DEV_CTL_INTR_MASKED_SOF_MASKED_Msk 0x2UL 382 #define USBHSDEV_DEV_CTL_INTR_MASKED_SUSP_MASKED_Pos 2UL 383 #define USBHSDEV_DEV_CTL_INTR_MASKED_SUSP_MASKED_Msk 0x4UL 384 #define USBHSDEV_DEV_CTL_INTR_MASKED_URESET_MASKED_Pos 3UL 385 #define USBHSDEV_DEV_CTL_INTR_MASKED_URESET_MASKED_Msk 0x8UL 386 #define USBHSDEV_DEV_CTL_INTR_MASKED_HSGRANT_MASKED_Pos 4UL 387 #define USBHSDEV_DEV_CTL_INTR_MASKED_HSGRANT_MASKED_Msk 0x10UL 388 #define USBHSDEV_DEV_CTL_INTR_MASKED_SUTOK_MASKED_Pos 5UL 389 #define USBHSDEV_DEV_CTL_INTR_MASKED_SUTOK_MASKED_Msk 0x20UL 390 #define USBHSDEV_DEV_CTL_INTR_MASKED_SUDAV_MASKED_Pos 6UL 391 #define USBHSDEV_DEV_CTL_INTR_MASKED_SUDAV_MASKED_Msk 0x40UL 392 #define USBHSDEV_DEV_CTL_INTR_MASKED_ERRLIMIT_MASKED_Pos 7UL 393 #define USBHSDEV_DEV_CTL_INTR_MASKED_ERRLIMIT_MASKED_Msk 0x80UL 394 #define USBHSDEV_DEV_CTL_INTR_MASKED_URESUME_MASKED_Pos 8UL 395 #define USBHSDEV_DEV_CTL_INTR_MASKED_URESUME_MASKED_Msk 0x100UL 396 #define USBHSDEV_DEV_CTL_INTR_MASKED_STATUS_STAGE_MASKED_Pos 9UL 397 #define USBHSDEV_DEV_CTL_INTR_MASKED_STATUS_STAGE_MASKED_Msk 0x200UL 398 #define USBHSDEV_DEV_CTL_INTR_MASKED_L1_SLEEP_REQ_MASKED_Pos 10UL 399 #define USBHSDEV_DEV_CTL_INTR_MASKED_L1_SLEEP_REQ_MASKED_Msk 0x400UL 400 #define USBHSDEV_DEV_CTL_INTR_MASKED_L1_URESUME_MASKED_Pos 11UL 401 #define USBHSDEV_DEV_CTL_INTR_MASKED_L1_URESUME_MASKED_Msk 0x800UL 402 #define USBHSDEV_DEV_CTL_INTR_MASKED_RESETDONE_MASKED_Pos 12UL 403 #define USBHSDEV_DEV_CTL_INTR_MASKED_RESETDONE_MASKED_Msk 0x1000UL 404 #define USBHSDEV_DEV_CTL_INTR_MASKED_HOST_URSUME_ARRIVED_MASKED_Pos 13UL 405 #define USBHSDEV_DEV_CTL_INTR_MASKED_HOST_URSUME_ARRIVED_MASKED_Msk 0x2000UL 406 #define USBHSDEV_DEV_CTL_INTR_MASKED_DPSLP_MASKED_Pos 14UL 407 #define USBHSDEV_DEV_CTL_INTR_MASKED_DPSLP_MASKED_Msk 0x4000UL 408 #define USBHSDEV_DEV_CTL_INTR_MASKED_PID_MISMATCH_ON_NAK_MASKED_Pos 15UL 409 #define USBHSDEV_DEV_CTL_INTR_MASKED_PID_MISMATCH_ON_NAK_MASKED_Msk 0x8000UL 410 /* MXS40USBHSDEV_USBHSDEV.DEV_CTL_INTR_SET */ 411 #define USBHSDEV_DEV_CTL_INTR_SET_SETADDR_MASKED_Pos 0UL 412 #define USBHSDEV_DEV_CTL_INTR_SET_SETADDR_MASKED_Msk 0x1UL 413 #define USBHSDEV_DEV_CTL_INTR_SET_SOF_MASKED_Pos 1UL 414 #define USBHSDEV_DEV_CTL_INTR_SET_SOF_MASKED_Msk 0x2UL 415 #define USBHSDEV_DEV_CTL_INTR_SET_SUSP_MASKED_Pos 2UL 416 #define USBHSDEV_DEV_CTL_INTR_SET_SUSP_MASKED_Msk 0x4UL 417 #define USBHSDEV_DEV_CTL_INTR_SET_URESET_MASKED_Pos 3UL 418 #define USBHSDEV_DEV_CTL_INTR_SET_URESET_MASKED_Msk 0x8UL 419 #define USBHSDEV_DEV_CTL_INTR_SET_HSGRANT_MASKED_Pos 4UL 420 #define USBHSDEV_DEV_CTL_INTR_SET_HSGRANT_MASKED_Msk 0x10UL 421 #define USBHSDEV_DEV_CTL_INTR_SET_SUTOK_MASKED_Pos 5UL 422 #define USBHSDEV_DEV_CTL_INTR_SET_SUTOK_MASKED_Msk 0x20UL 423 #define USBHSDEV_DEV_CTL_INTR_SET_SUDAV_MASKED_Pos 6UL 424 #define USBHSDEV_DEV_CTL_INTR_SET_SUDAV_MASKED_Msk 0x40UL 425 #define USBHSDEV_DEV_CTL_INTR_SET_ERRLIMIT_MASKED_Pos 7UL 426 #define USBHSDEV_DEV_CTL_INTR_SET_ERRLIMIT_MASKED_Msk 0x80UL 427 #define USBHSDEV_DEV_CTL_INTR_SET_URESUME_MASKED_Pos 8UL 428 #define USBHSDEV_DEV_CTL_INTR_SET_URESUME_MASKED_Msk 0x100UL 429 #define USBHSDEV_DEV_CTL_INTR_SET_STATUS_STAGE_MASKED_Pos 9UL 430 #define USBHSDEV_DEV_CTL_INTR_SET_STATUS_STAGE_MASKED_Msk 0x200UL 431 #define USBHSDEV_DEV_CTL_INTR_SET_L1_SLEEP_REQ_MASKED_Pos 10UL 432 #define USBHSDEV_DEV_CTL_INTR_SET_L1_SLEEP_REQ_MASKED_Msk 0x400UL 433 #define USBHSDEV_DEV_CTL_INTR_SET_L1_URESUME_MASKED_Pos 11UL 434 #define USBHSDEV_DEV_CTL_INTR_SET_L1_URESUME_MASKED_Msk 0x800UL 435 #define USBHSDEV_DEV_CTL_INTR_SET_RESETDONE_MASKED_Pos 12UL 436 #define USBHSDEV_DEV_CTL_INTR_SET_RESETDONE_MASKED_Msk 0x1000UL 437 #define USBHSDEV_DEV_CTL_INTR_SET_HOST_URSUME_ARRIVED_MASKED_Pos 13UL 438 #define USBHSDEV_DEV_CTL_INTR_SET_HOST_URSUME_ARRIVED_MASKED_Msk 0x2000UL 439 #define USBHSDEV_DEV_CTL_INTR_SET_DPSLP_MASKED_Pos 14UL 440 #define USBHSDEV_DEV_CTL_INTR_SET_DPSLP_MASKED_Msk 0x4000UL 441 #define USBHSDEV_DEV_CTL_INTR_SET_PID_MISMATCH_ON_NAK_MASKED_Pos 15UL 442 #define USBHSDEV_DEV_CTL_INTR_SET_PID_MISMATCH_ON_NAK_MASKED_Msk 0x8000UL 443 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_INTR_MASK */ 444 #define USBHSDEV_DEV_EP_INTR_MASK_EP_IN_Pos 0UL 445 #define USBHSDEV_DEV_EP_INTR_MASK_EP_IN_Msk 0xFFFFUL 446 #define USBHSDEV_DEV_EP_INTR_MASK_EP_OUT_Pos 16UL 447 #define USBHSDEV_DEV_EP_INTR_MASK_EP_OUT_Msk 0xFFFF0000UL 448 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_INTR */ 449 #define USBHSDEV_DEV_EP_INTR_EP_IN_Pos 0UL 450 #define USBHSDEV_DEV_EP_INTR_EP_IN_Msk 0xFFFFUL 451 #define USBHSDEV_DEV_EP_INTR_EP_OUT_Pos 16UL 452 #define USBHSDEV_DEV_EP_INTR_EP_OUT_Msk 0xFFFF0000UL 453 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_INTR_MASKED */ 454 #define USBHSDEV_DEV_EP_INTR_MASKED_EP_IN_Pos 0UL 455 #define USBHSDEV_DEV_EP_INTR_MASKED_EP_IN_Msk 0xFFFFUL 456 #define USBHSDEV_DEV_EP_INTR_MASKED_EP_OUT_Pos 16UL 457 #define USBHSDEV_DEV_EP_INTR_MASKED_EP_OUT_Msk 0xFFFF0000UL 458 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_INTR_SET */ 459 #define USBHSDEV_DEV_EP_INTR_SET_EP_IN_Pos 0UL 460 #define USBHSDEV_DEV_EP_INTR_SET_EP_IN_Msk 0xFFFFUL 461 #define USBHSDEV_DEV_EP_INTR_SET_EP_OUT_Pos 16UL 462 #define USBHSDEV_DEV_EP_INTR_SET_EP_OUT_Msk 0xFFFF0000UL 463 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_INGRS_INTR_MASK */ 464 #define USBHSDEV_DEV_EP_INGRS_INTR_MASK_EP_INGRS_ZLP_RCVD_Pos 0UL 465 #define USBHSDEV_DEV_EP_INGRS_INTR_MASK_EP_INGRS_ZLP_RCVD_Msk 0xFFFFUL 466 #define USBHSDEV_DEV_EP_INGRS_INTR_MASK_EP_INGRS_SLP_RCVD_Pos 16UL 467 #define USBHSDEV_DEV_EP_INGRS_INTR_MASK_EP_INGRS_SLP_RCVD_Msk 0xFFFF0000UL 468 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_INGRS_INTR */ 469 #define USBHSDEV_DEV_EP_INGRS_INTR_EP_INGRS_ZLP_RCVD_Pos 0UL 470 #define USBHSDEV_DEV_EP_INGRS_INTR_EP_INGRS_ZLP_RCVD_Msk 0xFFFFUL 471 #define USBHSDEV_DEV_EP_INGRS_INTR_EP_INGRS_SLP_RCVD_Pos 16UL 472 #define USBHSDEV_DEV_EP_INGRS_INTR_EP_INGRS_SLP_RCVD_Msk 0xFFFF0000UL 473 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_INGRS_INTR_MASKED */ 474 #define USBHSDEV_DEV_EP_INGRS_INTR_MASKED_EP_INGRS_ZLP_RCVD_Pos 0UL 475 #define USBHSDEV_DEV_EP_INGRS_INTR_MASKED_EP_INGRS_ZLP_RCVD_Msk 0xFFFFUL 476 #define USBHSDEV_DEV_EP_INGRS_INTR_MASKED_EP_INGRS_SLP_RCVD_Pos 16UL 477 #define USBHSDEV_DEV_EP_INGRS_INTR_MASKED_EP_INGRS_SLP_RCVD_Msk 0xFFFF0000UL 478 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_INGRS_INTR_SET */ 479 #define USBHSDEV_DEV_EP_INGRS_INTR_SET_EP_INGRS_ZLP_RCVD_Pos 0UL 480 #define USBHSDEV_DEV_EP_INGRS_INTR_SET_EP_INGRS_ZLP_RCVD_Msk 0xFFFFUL 481 #define USBHSDEV_DEV_EP_INGRS_INTR_SET_EP_INGRS_SLP_RCVD_Pos 16UL 482 #define USBHSDEV_DEV_EP_INGRS_INTR_SET_EP_INGRS_SLP_RCVD_Msk 0xFFFF0000UL 483 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_REQ */ 484 #define USBHSDEV_DEV_EP_EGRS_REQ_EP_EGRS_ZLP_SENT_Pos 0UL 485 #define USBHSDEV_DEV_EP_EGRS_REQ_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL 486 #define USBHSDEV_DEV_EP_EGRS_REQ_EP_EGRS_SLP_SENT_Pos 16UL 487 #define USBHSDEV_DEV_EP_EGRS_REQ_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL 488 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_INTR_MASK */ 489 #define USBHSDEV_DEV_EP_EGRS_INTR_MASK_EP_EGRS_ZLP_SENT_Pos 0UL 490 #define USBHSDEV_DEV_EP_EGRS_INTR_MASK_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL 491 #define USBHSDEV_DEV_EP_EGRS_INTR_MASK_EP_EGRS_SLP_SENT_Pos 16UL 492 #define USBHSDEV_DEV_EP_EGRS_INTR_MASK_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL 493 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_INTR */ 494 #define USBHSDEV_DEV_EP_EGRS_INTR_EP_EGRS_ZLP_SENT_Pos 0UL 495 #define USBHSDEV_DEV_EP_EGRS_INTR_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL 496 #define USBHSDEV_DEV_EP_EGRS_INTR_EP_EGRS_SLP_SENT_Pos 16UL 497 #define USBHSDEV_DEV_EP_EGRS_INTR_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL 498 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_INTR_MASKED */ 499 #define USBHSDEV_DEV_EP_EGRS_INTR_MASKED_EP_EGRS_ZLP_SENT_Pos 0UL 500 #define USBHSDEV_DEV_EP_EGRS_INTR_MASKED_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL 501 #define USBHSDEV_DEV_EP_EGRS_INTR_MASKED_EP_EGRS_SLP_SENT_Pos 16UL 502 #define USBHSDEV_DEV_EP_EGRS_INTR_MASKED_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL 503 /* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_INTR_SET */ 504 #define USBHSDEV_DEV_EP_EGRS_INTR_SET_EP_EGRS_ZLP_SENT_Pos 0UL 505 #define USBHSDEV_DEV_EP_EGRS_INTR_SET_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL 506 #define USBHSDEV_DEV_EP_EGRS_INTR_SET_EP_EGRS_SLP_SENT_Pos 16UL 507 #define USBHSDEV_DEV_EP_EGRS_INTR_SET_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL 508 /* MXS40USBHSDEV_USBHSDEV.POWER */ 509 #define USBHSDEV_POWER_RESETN_Pos 0UL 510 #define USBHSDEV_POWER_RESETN_Msk 0x1UL 511 #define USBHSDEV_POWER_EPM_DCG_ENABLE_Pos 1UL 512 #define USBHSDEV_POWER_EPM_DCG_ENABLE_Msk 0x2UL 513 #define USBHSDEV_POWER_AHB2AHB_SCALING_EN_Pos 2UL 514 #define USBHSDEV_POWER_AHB2AHB_SCALING_EN_Msk 0x4UL 515 #define USBHSDEV_POWER_LPM_ENABLE_Pos 3UL 516 #define USBHSDEV_POWER_LPM_ENABLE_Msk 0x8UL 517 #define USBHSDEV_POWER_VBUS_VALID_Pos 4UL 518 #define USBHSDEV_POWER_VBUS_VALID_Msk 0x10UL 519 #define USBHSDEV_POWER_REFCLK_SEL_Pos 5UL 520 #define USBHSDEV_POWER_REFCLK_SEL_Msk 0x20UL 521 /* MXS40USBHSDEV_USBHSDEV.DEV_LPM_ATTR */ 522 #define USBHSDEV_DEV_LPM_ATTR_RMT_WAKEUP_ENABLE_Pos 0UL 523 #define USBHSDEV_DEV_LPM_ATTR_RMT_WAKEUP_ENABLE_Msk 0x1UL 524 #define USBHSDEV_DEV_LPM_ATTR_HIRD_Pos 1UL 525 #define USBHSDEV_DEV_LPM_ATTR_HIRD_Msk 0x1EUL 526 #define USBHSDEV_DEV_LPM_ATTR_NYET_Pos 5UL 527 #define USBHSDEV_DEV_LPM_ATTR_NYET_Msk 0x20UL 528 #define USBHSDEV_DEV_LPM_ATTR_T_L1_TOKEN_RETRY_Pos 8UL 529 #define USBHSDEV_DEV_LPM_ATTR_T_L1_TOKEN_RETRY_Msk 0xFFFF00UL 530 #define USBHSDEV_DEV_LPM_ATTR_L2_SUSP_RMT_WAKEUP_EN_Pos 31UL 531 #define USBHSDEV_DEV_LPM_ATTR_L2_SUSP_RMT_WAKEUP_EN_Msk 0x80000000UL 532 /* MXS40USBHSDEV_USBHSDEV.DEV_LPM_TIM_1 */ 533 #define USBHSDEV_DEV_LPM_TIM_1_T_L1_DEV_DRV_RESUME_Pos 0UL 534 #define USBHSDEV_DEV_LPM_TIM_1_T_L1_DEV_DRV_RESUME_Msk 0xFFFFFUL 535 /* MXS40USBHSDEV_USBHSDEV.DEV_CHIRP_OVERRIDE */ 536 #define USBHSDEV_DEV_CHIRP_OVERRIDE_OVERRIDE_FSM_Pos 0UL 537 #define USBHSDEV_DEV_CHIRP_OVERRIDE_OVERRIDE_FSM_Msk 0x1UL 538 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_CHIRP_K_Pos 1UL 539 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_CHIRP_K_Msk 0x2UL 540 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_CHIRP_J_Pos 2UL 541 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_CHIRP_J_Msk 0x4UL 542 #define USBHSDEV_DEV_CHIRP_OVERRIDE_STATE_Pos 3UL 543 #define USBHSDEV_DEV_CHIRP_OVERRIDE_STATE_Msk 0xF8UL 544 #define USBHSDEV_DEV_CHIRP_OVERRIDE_SEND_TEST_PACKET_Pos 15UL 545 #define USBHSDEV_DEV_CHIRP_OVERRIDE_SEND_TEST_PACKET_Msk 0x8000UL 546 #define USBHSDEV_DEV_CHIRP_OVERRIDE_RCV_TEST_PACKET_Pos 16UL 547 #define USBHSDEV_DEV_CHIRP_OVERRIDE_RCV_TEST_PACKET_Msk 0x10000UL 548 #define USBHSDEV_DEV_CHIRP_OVERRIDE_TEST_PACKET_SPEED_Pos 17UL 549 #define USBHSDEV_DEV_CHIRP_OVERRIDE_TEST_PACKET_SPEED_Msk 0x20000UL 550 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_FS_Pos 18UL 551 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_FS_Msk 0x40000UL 552 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_FS_Pos 19UL 553 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_FS_Msk 0x80000UL 554 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_HS_Pos 20UL 555 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_HS_Msk 0x100000UL 556 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_HS_Pos 21UL 557 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_HS_Msk 0x200000UL 558 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_NO45_Pos 22UL 559 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_NO45_Msk 0x400000UL 560 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_NO45_Pos 23UL 561 #define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_NO45_Msk 0x800000UL 562 /* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_DCHSE0 */ 563 #define USBHSDEV_DEV_TIM_T_DCHSE0_T_DCHSE0_Pos 0UL 564 #define USBHSDEV_DEV_TIM_T_DCHSE0_T_DCHSE0_Msk 0x3FFFUL 565 #define USBHSDEV_DEV_TIM_T_DCHSE0_T_IPG_Pos 16UL 566 #define USBHSDEV_DEV_TIM_T_DCHSE0_T_IPG_Msk 0x1F0000UL 567 #define USBHSDEV_DEV_TIM_T_DCHSE0_T_HST_DBOUNCE_Pos 22UL 568 #define USBHSDEV_DEV_TIM_T_DCHSE0_T_HST_DBOUNCE_Msk 0x7FC00000UL 569 /* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_DETRST_FILT */ 570 #define USBHSDEV_DEV_TIM_T_DETRST_FILT_T_DETRST_Pos 0UL 571 #define USBHSDEV_DEV_TIM_T_DETRST_FILT_T_DETRST_Msk 0xFFFFFUL 572 #define USBHSDEV_DEV_TIM_T_DETRST_FILT_T_FILT_Pos 20UL 573 #define USBHSDEV_DEV_TIM_T_DETRST_FILT_T_FILT_Msk 0xFFF00000UL 574 /* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_WTFS */ 575 #define USBHSDEV_DEV_TIM_T_WTFS_T_WTFS_Pos 0UL 576 #define USBHSDEV_DEV_TIM_T_WTFS_T_WTFS_Msk 0x1FFFFUL 577 /* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_SUSP */ 578 #define USBHSDEV_DEV_TIM_T_SUSP_T_SUSP_Pos 0UL 579 #define USBHSDEV_DEV_TIM_T_SUSP_T_SUSP_Msk 0x1FFFFUL 580 /* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_WTRSTHS */ 581 #define USBHSDEV_DEV_TIM_T_WTRSTHS_T_WTRSTHS_Pos 0UL 582 #define USBHSDEV_DEV_TIM_T_WTRSTHS_T_WTRSTHS_Msk 0xFFFFUL 583 /* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_UCH */ 584 #define USBHSDEV_DEV_TIM_T_UCH_T_UCH_Pos 0UL 585 #define USBHSDEV_DEV_TIM_T_UCH_T_UCH_Msk 0x1FFFFUL 586 /* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_WTREV_WTRSTFS */ 587 #define USBHSDEV_DEV_TIM_T_WTREV_WTRSTFS_T_WTREV_WTRSTFS_Pos 0UL 588 #define USBHSDEV_DEV_TIM_T_WTREV_WTRSTFS_T_WTREV_WTRSTFS_Msk 0x1FFFFUL 589 /* MXS40USBHSDEV_USBHSDEV.DDFT_CONFIG */ 590 #define USBHSDEV_DDFT_CONFIG_DDFT0_SEL_Pos 0UL 591 #define USBHSDEV_DDFT_CONFIG_DDFT0_SEL_Msk 0x7FUL 592 #define USBHSDEV_DDFT_CONFIG_DDFT0_POLARITY_Pos 15UL 593 #define USBHSDEV_DDFT_CONFIG_DDFT0_POLARITY_Msk 0x8000UL 594 #define USBHSDEV_DDFT_CONFIG_DDFT1_SEL_Pos 16UL 595 #define USBHSDEV_DDFT_CONFIG_DDFT1_SEL_Msk 0x7F0000UL 596 #define USBHSDEV_DDFT_CONFIG_DDFT1_POLARITY_Pos 31UL 597 #define USBHSDEV_DDFT_CONFIG_DDFT1_POLARITY_Msk 0x80000000UL 598 /* MXS40USBHSDEV_USBHSDEV.DEV_LOOPBACK_CTRL */ 599 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_EN_Pos 0UL 600 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_EN_Msk 0x1UL 601 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_Pos 1UL 602 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_Msk 0x2UL 603 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_INTR_Pos 2UL 604 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_INTR_Msk 0x4UL 605 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_MASK_Pos 3UL 606 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_MASK_Msk 0x8UL 607 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_MASKED_Pos 4UL 608 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_MASKED_Msk 0x10UL 609 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_SW_SET_Pos 5UL 610 #define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_SW_SET_Msk 0x20UL 611 /* MXS40USBHSDEV_USBHSDEV.DEV_LOOPBACK_IN_REQ */ 612 #define USBHSDEV_DEV_LOOPBACK_IN_REQ_IN_TOKEN_Pos 0UL 613 #define USBHSDEV_DEV_LOOPBACK_IN_REQ_IN_TOKEN_Msk 0xFFFFFFUL 614 /* MXS40USBHSDEV_USBHSDEV.DEV_LOOPBACK_OUT_REQ */ 615 #define USBHSDEV_DEV_LOOPBACK_OUT_REQ_OUT_TOKEN_Pos 0UL 616 #define USBHSDEV_DEV_LOOPBACK_OUT_REQ_OUT_TOKEN_Msk 0xFFFFFFUL 617 /* MXS40USBHSDEV_USBHSDEV.EPM_CS */ 618 #define USBHSDEV_EPM_CS_EGRS_FORCE_FLUSH_ALL_Pos 0UL 619 #define USBHSDEV_EPM_CS_EGRS_FORCE_FLUSH_ALL_Msk 0x1UL 620 #define USBHSDEV_EPM_CS_IGRS_FORCE_FLUSH_ALL_Pos 1UL 621 #define USBHSDEV_EPM_CS_IGRS_FORCE_FLUSH_ALL_Msk 0x2UL 622 #define USBHSDEV_EPM_CS_ALLOW_TRIG_ON_SLP_Pos 2UL 623 #define USBHSDEV_EPM_CS_ALLOW_TRIG_ON_SLP_Msk 0x4UL 624 /* MXS40USBHSDEV_USBHSDEV.EEPM_DEBUG */ 625 #define USBHSDEV_EEPM_DEBUG_C_EPNUM_Pos 0UL 626 #define USBHSDEV_EEPM_DEBUG_C_EPNUM_Msk 0xFUL 627 #define USBHSDEV_EEPM_DEBUG_C_REQUEST_Pos 4UL 628 #define USBHSDEV_EEPM_DEBUG_C_REQUEST_Msk 0x30UL 629 #define USBHSDEV_EEPM_DEBUG_USB_RD_ADDR_Pos 6UL 630 #define USBHSDEV_EEPM_DEBUG_USB_RD_ADDR_Msk 0x7FFC0UL 631 #define USBHSDEV_EEPM_DEBUG_AHB_WR_ADDR_Pos 19UL 632 #define USBHSDEV_EEPM_DEBUG_AHB_WR_ADDR_Msk 0xFFF80000UL 633 /* MXS40USBHSDEV_USBHSDEV.IEPM_DEBUG */ 634 #define USBHSDEV_IEPM_DEBUG_ACTIVE_EP_NUM_Pos 0UL 635 #define USBHSDEV_IEPM_DEBUG_ACTIVE_EP_NUM_Msk 0xFUL 636 #define USBHSDEV_IEPM_DEBUG_P_REQUESTS_Pos 4UL 637 #define USBHSDEV_IEPM_DEBUG_P_REQUESTS_Msk 0x3F0UL 638 #define USBHSDEV_IEPM_DEBUG_P_REQ_EP_NUM_Pos 16UL 639 #define USBHSDEV_IEPM_DEBUG_P_REQ_EP_NUM_Msk 0xFFFF0000UL 640 /* MXS40USBHSDEV_USBHSDEV.IEPM_DEBUG_1 */ 641 #define USBHSDEV_IEPM_DEBUG_1_IGRS_USB_WADDR_Pos 0UL 642 #define USBHSDEV_IEPM_DEBUG_1_IGRS_USB_WADDR_Msk 0x1FFUL 643 #define USBHSDEV_IEPM_DEBUG_1_IGRS_AHB_RADDR_Pos 16UL 644 #define USBHSDEV_IEPM_DEBUG_1_IGRS_AHB_RADDR_Msk 0x1FF0000UL 645 /* MXS40USBHSDEV_USBHSDEV.IEPM_DEBUG_2 */ 646 #define USBHSDEV_IEPM_DEBUG_2_IGRS_LAST_WADDR_Pos 0UL 647 #define USBHSDEV_IEPM_DEBUG_2_IGRS_LAST_WADDR_Msk 0x1FFUL 648 #define USBHSDEV_IEPM_DEBUG_2_IGRS_LAST_RADDR_Pos 16UL 649 #define USBHSDEV_IEPM_DEBUG_2_IGRS_LAST_RADDR_Msk 0x1FF0000UL 650 /* MXS40USBHSDEV_USBHSDEV.EEPM_ENDPOINT */ 651 #define USBHSDEV_EEPM_ENDPOINT_EGRS_SLP_BYTE_COUNT_Pos 0UL 652 #define USBHSDEV_EEPM_ENDPOINT_EGRS_SLP_BYTE_COUNT_Msk 0x3FFUL 653 #define USBHSDEV_EEPM_ENDPOINT_EGRS_FLUSH_EP_Pos 11UL 654 #define USBHSDEV_EEPM_ENDPOINT_EGRS_FLUSH_EP_Msk 0x800UL 655 /* MXS40USBHSDEV_USBHSDEV.IEPM_ENDPOINT */ 656 #define USBHSDEV_IEPM_ENDPOINT_INGRS_SLP_BYTE_COUNT_Pos 0UL 657 #define USBHSDEV_IEPM_ENDPOINT_INGRS_SLP_BYTE_COUNT_Msk 0x3FFUL 658 #define USBHSDEV_IEPM_ENDPOINT_ALLOW_NAK_TILL_DMA_RDY_Pos 11UL 659 #define USBHSDEV_IEPM_ENDPOINT_ALLOW_NAK_TILL_DMA_RDY_Msk 0x800UL 660 /* MXS40USBHSDEV_USBHSDEV.EEPM_DEBUG_ENDPOINT */ 661 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EGRS_P_REQUESTS_Pos 0UL 662 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EGRS_P_REQUESTS_Msk 0x3UL 663 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EGRS_DMA_TRIGGERED_Pos 2UL 664 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EGRS_DMA_TRIGGERED_Msk 0x4UL 665 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_NEXT_ADDR_Pos 3UL 666 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_NEXT_ADDR_Msk 0xFFF8UL 667 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_CURR_ADDR_Pos 16UL 668 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_CURR_ADDR_Msk 0x1FFF0000UL 669 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_NEXT_SLP_Pos 29UL 670 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_NEXT_SLP_Msk 0x20000000UL 671 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_CURR_SLP_Pos 30UL 672 #define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_CURR_SLP_Msk 0x40000000UL 673 /* MXS40USBHSDEV_USBHSDEV.IEPM_DEBUG_ENDPOINT */ 674 #define USBHSDEV_IEPM_DEBUG_ENDPOINT_INGRS_DMA_TRIGGERED_Pos 0UL 675 #define USBHSDEV_IEPM_DEBUG_ENDPOINT_INGRS_DMA_TRIGGERED_Msk 0x1UL 676 /* MXS40USBHSDEV_USBHSDEV.MMIO_EEPM_ENDPOINT */ 677 #define USBHSDEV_MMIO_EEPM_ENDPOINT_EGRS_IF_SELECT_Pos 0UL 678 #define USBHSDEV_MMIO_EEPM_ENDPOINT_EGRS_IF_SELECT_Msk 0x1UL 679 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_SEND_Pos 1UL 680 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_SEND_Msk 0x2UL 681 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_Pos 2UL 682 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_Msk 0x4UL 683 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_MASK_Pos 3UL 684 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_MASK_Msk 0x8UL 685 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_MASKED_Pos 4UL 686 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_MASKED_Msk 0x10UL 687 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_SW_SET_Pos 5UL 688 #define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_SW_SET_Msk 0x20UL 689 /* MXS40USBHSDEV_USBHSDEV.MMIO_IEPM_ENDPOINT */ 690 #define USBHSDEV_MMIO_IEPM_ENDPOINT_INGRS_IF_SELECT_Pos 0UL 691 #define USBHSDEV_MMIO_IEPM_ENDPOINT_INGRS_IF_SELECT_Msk 0x1UL 692 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_SEND_Pos 1UL 693 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_SEND_Msk 0x2UL 694 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_Pos 2UL 695 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_Msk 0x4UL 696 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_MASK_Pos 3UL 697 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_MASK_Msk 0x8UL 698 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_MASKED_Pos 4UL 699 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_MASKED_Msk 0x10UL 700 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_SW_SET_Pos 5UL 701 #define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_SW_SET_Msk 0x20UL 702 /* MXS40USBHSDEV_USBHSDEV.DEV_SPARE_1 */ 703 #define USBHSDEV_DEV_SPARE_1_SPARE_1_1_Pos 0UL 704 #define USBHSDEV_DEV_SPARE_1_SPARE_1_1_Msk 0xFFFFUL 705 #define USBHSDEV_DEV_SPARE_1_SPARE_1_2_Pos 16UL 706 #define USBHSDEV_DEV_SPARE_1_SPARE_1_2_Msk 0xFFFF0000UL 707 /* MXS40USBHSDEV_USBHSDEV.DEV_SPARE_2 */ 708 #define USBHSDEV_DEV_SPARE_2_SPARE_2_1_Pos 0UL 709 #define USBHSDEV_DEV_SPARE_2_SPARE_2_1_Msk 0xFFFFUL 710 #define USBHSDEV_DEV_SPARE_2_SPARE_2_2_Pos 16UL 711 #define USBHSDEV_DEV_SPARE_2_SPARE_2_2_Msk 0xFFFF0000UL 712 /* MXS40USBHSDEV_USBHSDEV.LEGACY_FEATURE_ENABLE */ 713 #define USBHSDEV_LEGACY_FEATURE_ENABLE_DATA0_TOG_UPON_STALL_Pos 0UL 714 #define USBHSDEV_LEGACY_FEATURE_ENABLE_DATA0_TOG_UPON_STALL_Msk 0x1UL 715 #define USBHSDEV_LEGACY_FEATURE_ENABLE_CONT_LP_UPON_NO_HOST_RSUME_Pos 1UL 716 #define USBHSDEV_LEGACY_FEATURE_ENABLE_CONT_LP_UPON_NO_HOST_RSUME_Msk 0x2UL 717 #define USBHSDEV_LEGACY_FEATURE_ENABLE_NO_PID_UPDATE_ON_NAK_Pos 2UL 718 #define USBHSDEV_LEGACY_FEATURE_ENABLE_NO_PID_UPDATE_ON_NAK_Msk 0x4UL 719 #define USBHSDEV_LEGACY_FEATURE_ENABLE_RESERVED_Pos 3UL 720 #define USBHSDEV_LEGACY_FEATURE_ENABLE_RESERVED_Msk 0xFFFFFFF8UL 721 /* MXS40USBHSDEV_USBHSDEV.DFT_OBSERVE */ 722 #define USBHSDEV_DFT_OBSERVE_DFT_OBSERVE_Pos 0UL 723 #define USBHSDEV_DFT_OBSERVE_DFT_OBSERVE_Msk 0xFFFFFFFFUL 724 725 726 /* MXS40USBHSDEV_USBHSPHY.AFE_CONTROL_1 */ 727 #define USBHSPHY_AFE_CONTROL_1_HS_PRED_DP_SEL_Pos 0UL 728 #define USBHSPHY_AFE_CONTROL_1_HS_PRED_DP_SEL_Msk 0x3UL 729 #define USBHSPHY_AFE_CONTROL_1_HS_PRED_DN_SEL_Pos 2UL 730 #define USBHSPHY_AFE_CONTROL_1_HS_PRED_DN_SEL_Msk 0xCUL 731 #define USBHSPHY_AFE_CONTROL_1_HS_AMP_SEL_Pos 4UL 732 #define USBHSPHY_AFE_CONTROL_1_HS_AMP_SEL_Msk 0xF0UL 733 #define USBHSPHY_AFE_CONTROL_1_HS_PREE_SEL_Pos 8UL 734 #define USBHSPHY_AFE_CONTROL_1_HS_PREE_SEL_Msk 0x700UL 735 #define USBHSPHY_AFE_CONTROL_1_HS_SR_FINE_SEL_Pos 11UL 736 #define USBHSPHY_AFE_CONTROL_1_HS_SR_FINE_SEL_Msk 0x3800UL 737 #define USBHSPHY_AFE_CONTROL_1_HS_TED_LP_MODE_Pos 14UL 738 #define USBHSPHY_AFE_CONTROL_1_HS_TED_LP_MODE_Msk 0x4000UL 739 #define USBHSPHY_AFE_CONTROL_1_EN_LANE_SWAP_Pos 15UL 740 #define USBHSPHY_AFE_CONTROL_1_EN_LANE_SWAP_Msk 0x8000UL 741 #define USBHSPHY_AFE_CONTROL_1_HS_CTLE_SEL_Pos 16UL 742 #define USBHSPHY_AFE_CONTROL_1_HS_CTLE_SEL_Msk 0x70000UL 743 #define USBHSPHY_AFE_CONTROL_1_FS_VTRIG_SEL_Pos 19UL 744 #define USBHSPHY_AFE_CONTROL_1_FS_VTRIG_SEL_Msk 0x380000UL 745 #define USBHSPHY_AFE_CONTROL_1_FS_SR_SEL_Pos 22UL 746 #define USBHSPHY_AFE_CONTROL_1_FS_SR_SEL_Msk 0x3C00000UL 747 #define USBHSPHY_AFE_CONTROL_1_LS_SR_SEL_Pos 26UL 748 #define USBHSPHY_AFE_CONTROL_1_LS_SR_SEL_Msk 0xC000000UL 749 #define USBHSPHY_AFE_CONTROL_1_HS_LB_EN_Pos 28UL 750 #define USBHSPHY_AFE_CONTROL_1_HS_LB_EN_Msk 0x10000000UL 751 #define USBHSPHY_AFE_CONTROL_1_HS_TED_25_MODE_Pos 29UL 752 #define USBHSPHY_AFE_CONTROL_1_HS_TED_25_MODE_Msk 0x20000000UL 753 #define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_VCCD_Pos 30UL 754 #define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_VCCD_Msk 0x40000000UL 755 #define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_HS_VCCD_Pos 31UL 756 #define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_HS_VCCD_Msk 0x80000000UL 757 /* MXS40USBHSDEV_USBHSPHY.AFE_CONTROL_2 */ 758 #define USBHSPHY_AFE_CONTROL_2_AFE_DFT_SEL_Pos 0UL 759 #define USBHSPHY_AFE_CONTROL_2_AFE_DFT_SEL_Msk 0x3FFUL 760 #define USBHSPHY_AFE_CONTROL_2_EUSB_RX_CRUDE_EN_Pos 10UL 761 #define USBHSPHY_AFE_CONTROL_2_EUSB_RX_CRUDE_EN_Msk 0x400UL 762 #define USBHSPHY_AFE_CONTROL_2_EUSB_RX_MUX_SEL_Pos 11UL 763 #define USBHSPHY_AFE_CONTROL_2_EUSB_RX_MUX_SEL_Msk 0x800UL 764 #define USBHSPHY_AFE_CONTROL_2_EUSB_RX_OVERRIDE_Pos 12UL 765 #define USBHSPHY_AFE_CONTROL_2_EUSB_RX_OVERRIDE_Msk 0x1000UL 766 #define USBHSPHY_AFE_CONTROL_2_EUSB_RX_MISSION_EN_Pos 13UL 767 #define USBHSPHY_AFE_CONTROL_2_EUSB_RX_MISSION_EN_Msk 0x2000UL 768 #define USBHSPHY_AFE_CONTROL_2_SE_RX_SE1_FILTER_EN_N_Pos 14UL 769 #define USBHSPHY_AFE_CONTROL_2_SE_RX_SE1_FILTER_EN_N_Msk 0x4000UL 770 #define USBHSPHY_AFE_CONTROL_2_ENABLE_EUSB_RX_Pos 17UL 771 #define USBHSPHY_AFE_CONTROL_2_ENABLE_EUSB_RX_Msk 0x20000UL 772 /* MXS40USBHSDEV_USBHSPHY.UTMI_CONTROL */ 773 #define USBHSPHY_UTMI_CONTROL_SOFT_DISCONNECT_N_Pos 0UL 774 #define USBHSPHY_UTMI_CONTROL_SOFT_DISCONNECT_N_Msk 0x1UL 775 #define USBHSPHY_UTMI_CONTROL_VLOAD_Pos 1UL 776 #define USBHSPHY_UTMI_CONTROL_VLOAD_Msk 0x2UL 777 #define USBHSPHY_UTMI_CONTROL_VCONTROL_TESTCODE_Pos 2UL 778 #define USBHSPHY_UTMI_CONTROL_VCONTROL_TESTCODE_Msk 0x3CUL 779 #define USBHSPHY_UTMI_CONTROL_VCONTROL_TESTDATA_Pos 6UL 780 #define USBHSPHY_UTMI_CONTROL_VCONTROL_TESTDATA_Msk 0x3C0UL 781 #define USBHSPHY_UTMI_CONTROL_BIST_EN_Pos 10UL 782 #define USBHSPHY_UTMI_CONTROL_BIST_EN_Msk 0x400UL 783 #define USBHSPHY_UTMI_CONTROL_TUNE_BYPASS_EN_Pos 11UL 784 #define USBHSPHY_UTMI_CONTROL_TUNE_BYPASS_EN_Msk 0x800UL 785 #define USBHSPHY_UTMI_CONTROL_EXT_CAL_VALUE_Pos 12UL 786 #define USBHSPHY_UTMI_CONTROL_EXT_CAL_VALUE_Msk 0x1F000UL 787 #define USBHSPHY_UTMI_CONTROL_OTG_IN_SUSPEND_Pos 17UL 788 #define USBHSPHY_UTMI_CONTROL_OTG_IN_SUSPEND_Msk 0x20000UL 789 #define USBHSPHY_UTMI_CONTROL_BIST_CONTINOUS_EN_Pos 18UL 790 #define USBHSPHY_UTMI_CONTROL_BIST_CONTINOUS_EN_Msk 0x40000UL 791 #define USBHSPHY_UTMI_CONTROL_LINESTATE_COMBO_SEQ_Pos 19UL 792 #define USBHSPHY_UTMI_CONTROL_LINESTATE_COMBO_SEQ_Msk 0x80000UL 793 #define USBHSPHY_UTMI_CONTROL_LINESTATE_EXT_SEL_Pos 20UL 794 #define USBHSPHY_UTMI_CONTROL_LINESTATE_EXT_SEL_Msk 0x100000UL 795 #define USBHSPHY_UTMI_CONTROL_LINESTATE_CLK_SEL_Pos 21UL 796 #define USBHSPHY_UTMI_CONTROL_LINESTATE_CLK_SEL_Msk 0x200000UL 797 #define USBHSPHY_UTMI_CONTROL_CAL_BIG_LITTLE_ENDIAN_Pos 22UL 798 #define USBHSPHY_UTMI_CONTROL_CAL_BIG_LITTLE_ENDIAN_Msk 0x400000UL 799 #define USBHSPHY_UTMI_CONTROL_BIST_CONTINOUS_PATTERN_Pos 23UL 800 #define USBHSPHY_UTMI_CONTROL_BIST_CONTINOUS_PATTERN_Msk 0x7F800000UL 801 #define USBHSPHY_UTMI_CONTROL_REVERT_RPU_CTRL_Pos 31UL 802 #define USBHSPHY_UTMI_CONTROL_REVERT_RPU_CTRL_Msk 0x80000000UL 803 /* MXS40USBHSDEV_USBHSPHY.CDR_CONTROL */ 804 #define USBHSPHY_CDR_CONTROL_CONF_EOI_VEC_Pos 0UL 805 #define USBHSPHY_CDR_CONTROL_CONF_EOI_VEC_Msk 0x7UL 806 #define USBHSPHY_CDR_CONTROL_CONF_HS_6_SYNC_Pos 3UL 807 #define USBHSPHY_CDR_CONTROL_CONF_HS_6_SYNC_Msk 0x8UL 808 #define USBHSPHY_CDR_CONTROL_EBUF_DEPTH_Pos 4UL 809 #define USBHSPHY_CDR_CONTROL_EBUF_DEPTH_Msk 0x30UL 810 #define USBHSPHY_CDR_CONTROL_CDR_CONFIG_1_Pos 6UL 811 #define USBHSPHY_CDR_CONTROL_CDR_CONFIG_1_Msk 0x40UL 812 #define USBHSPHY_CDR_CONTROL_CDR_ENABLE_Pos 7UL 813 #define USBHSPHY_CDR_CONTROL_CDR_ENABLE_Msk 0x80UL 814 #define USBHSPHY_CDR_CONTROL_SQUELCH_FILTER_Pos 8UL 815 #define USBHSPHY_CDR_CONTROL_SQUELCH_FILTER_Msk 0x700UL 816 #define USBHSPHY_CDR_CONTROL_SYNC_MATCH_PATTERN_Pos 11UL 817 #define USBHSPHY_CDR_CONTROL_SYNC_MATCH_PATTERN_Msk 0x800UL 818 #define USBHSPHY_CDR_CONTROL_GATE_SERIAL_IN_TILL_SQUELCH_Pos 12UL 819 #define USBHSPHY_CDR_CONTROL_GATE_SERIAL_IN_TILL_SQUELCH_Msk 0x1000UL 820 #define USBHSPHY_CDR_CONTROL_SERIAL_IN_DELAY_Pos 13UL 821 #define USBHSPHY_CDR_CONTROL_SERIAL_IN_DELAY_Msk 0xE000UL 822 /* MXS40USBHSDEV_USBHSPHY.BC_CONTROL */ 823 #define USBHSPHY_BC_CONTROL_CHRGR_DET_ON_Pos 0UL 824 #define USBHSPHY_BC_CONTROL_CHRGR_DET_ON_Msk 0x1UL 825 #define USBHSPHY_BC_CONTROL_VDM_SRC_EN_Pos 1UL 826 #define USBHSPHY_BC_CONTROL_VDM_SRC_EN_Msk 0x2UL 827 #define USBHSPHY_BC_CONTROL_VDP_SRC_EN_Pos 2UL 828 #define USBHSPHY_BC_CONTROL_VDP_SRC_EN_Msk 0x4UL 829 /* MXS40USBHSDEV_USBHSPHY.PLL_CONTROL_1 */ 830 #define USBHSPHY_PLL_CONTROL_1_RUN_AWAY_DEL_Pos 0UL 831 #define USBHSPHY_PLL_CONTROL_1_RUN_AWAY_DEL_Msk 0x3UL 832 #define USBHSPHY_PLL_CONTROL_1_RUN_AWAY_DIS_Pos 2UL 833 #define USBHSPHY_PLL_CONTROL_1_RUN_AWAY_DIS_Msk 0x4UL 834 #define USBHSPHY_PLL_CONTROL_1_VCO_GAIN_Pos 3UL 835 #define USBHSPHY_PLL_CONTROL_1_VCO_GAIN_Msk 0x78UL 836 #define USBHSPHY_PLL_CONTROL_1_PLL_EN_Pos 8UL 837 #define USBHSPHY_PLL_CONTROL_1_PLL_EN_Msk 0x100UL 838 #define USBHSPHY_PLL_CONTROL_1_SUPPLY_EN_Pos 9UL 839 #define USBHSPHY_PLL_CONTROL_1_SUPPLY_EN_Msk 0x200UL 840 #define USBHSPHY_PLL_CONTROL_1_LD_DELAY_Pos 10UL 841 #define USBHSPHY_PLL_CONTROL_1_LD_DELAY_Msk 0xC00UL 842 #define USBHSPHY_PLL_CONTROL_1_LDO_VCO_BYPASS_Pos 13UL 843 #define USBHSPHY_PLL_CONTROL_1_LDO_VCO_BYPASS_Msk 0x2000UL 844 #define USBHSPHY_PLL_CONTROL_1_P_DIV_Pos 14UL 845 #define USBHSPHY_PLL_CONTROL_1_P_DIV_Msk 0xC000UL 846 #define USBHSPHY_PLL_CONTROL_1_Q_DIV_Pos 16UL 847 #define USBHSPHY_PLL_CONTROL_1_Q_DIV_Msk 0x30000UL 848 #define USBHSPHY_PLL_CONTROL_1_PLL_SPARE_Pos 18UL 849 #define USBHSPHY_PLL_CONTROL_1_PLL_SPARE_Msk 0x40000UL 850 #define USBHSPHY_PLL_CONTROL_1_VCO_INIT_DIS_Pos 19UL 851 #define USBHSPHY_PLL_CONTROL_1_VCO_INIT_DIS_Msk 0x80000UL 852 #define USBHSPHY_PLL_CONTROL_1_ATST_SEL_Pos 20UL 853 #define USBHSPHY_PLL_CONTROL_1_ATST_SEL_Msk 0xF00000UL 854 #define USBHSPHY_PLL_CONTROL_1_CAL_UP_DN_Pos 24UL 855 #define USBHSPHY_PLL_CONTROL_1_CAL_UP_DN_Msk 0xF000000UL 856 #define USBHSPHY_PLL_CONTROL_1_RA_UP_TR_Pos 28UL 857 #define USBHSPHY_PLL_CONTROL_1_RA_UP_TR_Msk 0x30000000UL 858 /* MXS40USBHSDEV_USBHSPHY.PLL_CONTROL_2 */ 859 #define USBHSPHY_PLL_CONTROL_2_EN_CPU_OVERIDE_PLL_LOCK_Pos 0UL 860 #define USBHSPHY_PLL_CONTROL_2_EN_CPU_OVERIDE_PLL_LOCK_Msk 0x1UL 861 #define USBHSPHY_PLL_CONTROL_2_CPU_OVERIDE_PLL_LOCK_VALUE_Pos 1UL 862 #define USBHSPHY_PLL_CONTROL_2_CPU_OVERIDE_PLL_LOCK_VALUE_Msk 0x2UL 863 #define USBHSPHY_PLL_CONTROL_2_SOURCE_OF_PLL_LOCK_Pos 2UL 864 #define USBHSPHY_PLL_CONTROL_2_SOURCE_OF_PLL_LOCK_Msk 0x4UL 865 #define USBHSPHY_PLL_CONTROL_2_LOCK_DELAY_Pos 3UL 866 #define USBHSPHY_PLL_CONTROL_2_LOCK_DELAY_Msk 0x7F8UL 867 #define USBHSPHY_PLL_CONTROL_2_LOSS_LOCK_DELAY_Pos 11UL 868 #define USBHSPHY_PLL_CONTROL_2_LOSS_LOCK_DELAY_Msk 0xF800UL 869 #define USBHSPHY_PLL_CONTROL_2_JITTER_TEST_MODE_Pos 16UL 870 #define USBHSPHY_PLL_CONTROL_2_JITTER_TEST_MODE_Msk 0x10000UL 871 #define USBHSPHY_PLL_CONTROL_2_DIV_VALUE_Pos 25UL 872 #define USBHSPHY_PLL_CONTROL_2_DIV_VALUE_Msk 0x1E000000UL 873 #define USBHSPHY_PLL_CONTROL_2_PLL_CLKOUT_DDFT_SEL_Pos 29UL 874 #define USBHSPHY_PLL_CONTROL_2_PLL_CLKOUT_DDFT_SEL_Msk 0xE0000000UL 875 /* MXS40USBHSDEV_USBHSPHY.TEST_PLL_CONTROL */ 876 #define USBHSPHY_TEST_PLL_CONTROL_RUN_AWAY_DEL_Pos 0UL 877 #define USBHSPHY_TEST_PLL_CONTROL_RUN_AWAY_DEL_Msk 0x3UL 878 #define USBHSPHY_TEST_PLL_CONTROL_RUN_AWAY_DIS_Pos 2UL 879 #define USBHSPHY_TEST_PLL_CONTROL_RUN_AWAY_DIS_Msk 0x4UL 880 #define USBHSPHY_TEST_PLL_CONTROL_VCO_GAIN_Pos 3UL 881 #define USBHSPHY_TEST_PLL_CONTROL_VCO_GAIN_Msk 0x78UL 882 #define USBHSPHY_TEST_PLL_CONTROL_PLL_EN_Pos 8UL 883 #define USBHSPHY_TEST_PLL_CONTROL_PLL_EN_Msk 0x100UL 884 #define USBHSPHY_TEST_PLL_CONTROL_SUPPLY_EN_Pos 9UL 885 #define USBHSPHY_TEST_PLL_CONTROL_SUPPLY_EN_Msk 0x200UL 886 #define USBHSPHY_TEST_PLL_CONTROL_LD_DELAY_Pos 10UL 887 #define USBHSPHY_TEST_PLL_CONTROL_LD_DELAY_Msk 0xC00UL 888 #define USBHSPHY_TEST_PLL_CONTROL_LDO_VCO_BYPASS_Pos 13UL 889 #define USBHSPHY_TEST_PLL_CONTROL_LDO_VCO_BYPASS_Msk 0x2000UL 890 #define USBHSPHY_TEST_PLL_CONTROL_P_DIV_Pos 14UL 891 #define USBHSPHY_TEST_PLL_CONTROL_P_DIV_Msk 0xC000UL 892 #define USBHSPHY_TEST_PLL_CONTROL_Q_DIV_Pos 16UL 893 #define USBHSPHY_TEST_PLL_CONTROL_Q_DIV_Msk 0x30000UL 894 #define USBHSPHY_TEST_PLL_CONTROL_PLL_SPARE_Pos 18UL 895 #define USBHSPHY_TEST_PLL_CONTROL_PLL_SPARE_Msk 0x40000UL 896 #define USBHSPHY_TEST_PLL_CONTROL_VCO_INIT_DIS_Pos 19UL 897 #define USBHSPHY_TEST_PLL_CONTROL_VCO_INIT_DIS_Msk 0x80000UL 898 #define USBHSPHY_TEST_PLL_CONTROL_ATST_SEL_Pos 20UL 899 #define USBHSPHY_TEST_PLL_CONTROL_ATST_SEL_Msk 0xF00000UL 900 #define USBHSPHY_TEST_PLL_CONTROL_CAL_UP_DN_Pos 24UL 901 #define USBHSPHY_TEST_PLL_CONTROL_CAL_UP_DN_Msk 0xF000000UL 902 #define USBHSPHY_TEST_PLL_CONTROL_RA_UP_TR_Pos 28UL 903 #define USBHSPHY_TEST_PLL_CONTROL_RA_UP_TR_Msk 0x30000000UL 904 #define USBHSPHY_TEST_PLL_CONTROL_TEST_LOCK_DELAY_Pos 30UL 905 #define USBHSPHY_TEST_PLL_CONTROL_TEST_LOCK_DELAY_Msk 0xC0000000UL 906 /* MXS40USBHSDEV_USBHSPHY.TEST_CONTROL */ 907 #define USBHSPHY_TEST_CONTROL_RUN_CALIBRATION_Pos 0UL 908 #define USBHSPHY_TEST_CONTROL_RUN_CALIBRATION_Msk 0x1UL 909 #define USBHSPHY_TEST_CONTROL_CALIBRATED_VALUE_Pos 1UL 910 #define USBHSPHY_TEST_CONTROL_CALIBRATED_VALUE_Msk 0x3EUL 911 /* MXS40USBHSDEV_USBHSPHY.DDFT_CFG */ 912 #define USBHSPHY_DDFT_CFG_DDFT0_SEL_Pos 0UL 913 #define USBHSPHY_DDFT_CFG_DDFT0_SEL_Msk 0x7FUL 914 #define USBHSPHY_DDFT_CFG_DDFT0_POLARITY_Pos 7UL 915 #define USBHSPHY_DDFT_CFG_DDFT0_POLARITY_Msk 0x80UL 916 #define USBHSPHY_DDFT_CFG_DDFT1_SEL_Pos 8UL 917 #define USBHSPHY_DDFT_CFG_DDFT1_SEL_Msk 0x7F00UL 918 #define USBHSPHY_DDFT_CFG_DDFT1_POLARITY_Pos 15UL 919 #define USBHSPHY_DDFT_CFG_DDFT1_POLARITY_Msk 0x8000UL 920 /* MXS40USBHSDEV_USBHSPHY.DIGITAL_CONTROL */ 921 #define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_SEL_Pos 0UL 922 #define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_SEL_Msk 0x3UL 923 #define USBHSPHY_DIGITAL_CONTROL_TX_CLOCK_SOURCE_DFT_Pos 2UL 924 #define USBHSPHY_DIGITAL_CONTROL_TX_CLOCK_SOURCE_DFT_Msk 0x4UL 925 #define USBHSPHY_DIGITAL_CONTROL_CLK480_PHASE_SEL_Pos 3UL 926 #define USBHSPHY_DIGITAL_CONTROL_CLK480_PHASE_SEL_Msk 0x8UL 927 #define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_ON_DELAY_Pos 5UL 928 #define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_ON_DELAY_Msk 0xE0UL 929 #define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_OFF_DELAY_Pos 8UL 930 #define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_OFF_DELAY_Msk 0x700UL 931 #define USBHSPHY_DIGITAL_CONTROL_BURN_IN_EN_Pos 11UL 932 #define USBHSPHY_DIGITAL_CONTROL_BURN_IN_EN_Msk 0x800UL 933 #define USBHSPHY_DIGITAL_CONTROL_BURN_Pos 12UL 934 #define USBHSPHY_DIGITAL_CONTROL_BURN_Msk 0x3000UL 935 #define USBHSPHY_DIGITAL_CONTROL_DIS_PRE_EMPHASIS_HS_SOF_Pos 14UL 936 #define USBHSPHY_DIGITAL_CONTROL_DIS_PRE_EMPHASIS_HS_SOF_Msk 0x4000UL 937 #define USBHSPHY_DIGITAL_CONTROL_BIT_TIME_DIS_PRE_EMPHASIS_Pos 16UL 938 #define USBHSPHY_DIGITAL_CONTROL_BIT_TIME_DIS_PRE_EMPHASIS_Msk 0x3F0000UL 939 #define USBHSPHY_DIGITAL_CONTROL_CONTROL_HS_TX_IN_Pos 22UL 940 #define USBHSPHY_DIGITAL_CONTROL_CONTROL_HS_TX_IN_Msk 0x400000UL 941 #define USBHSPHY_DIGITAL_CONTROL_HX_TX_IN_DP_VALUE_Pos 23UL 942 #define USBHSPHY_DIGITAL_CONTROL_HX_TX_IN_DP_VALUE_Msk 0x800000UL 943 #define USBHSPHY_DIGITAL_CONTROL_HX_TX_IN_DN_VALUE_Pos 24UL 944 #define USBHSPHY_DIGITAL_CONTROL_HX_TX_IN_DN_VALUE_Msk 0x1000000UL 945 #define USBHSPHY_DIGITAL_CONTROL_CONTROL_HS_TX_PREE_Pos 25UL 946 #define USBHSPHY_DIGITAL_CONTROL_CONTROL_HS_TX_PREE_Msk 0x2000000UL 947 #define USBHSPHY_DIGITAL_CONTROL_HX_TX_PREE_DP_VALUE_Pos 26UL 948 #define USBHSPHY_DIGITAL_CONTROL_HX_TX_PREE_DP_VALUE_Msk 0x4000000UL 949 #define USBHSPHY_DIGITAL_CONTROL_HX_TX_PREE_DN_VALUE_Pos 27UL 950 #define USBHSPHY_DIGITAL_CONTROL_HX_TX_PREE_DN_VALUE_Msk 0x8000000UL 951 #define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_CDR_CLK480M_Pos 29UL 952 #define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_CDR_CLK480M_Msk 0x20000000UL 953 #define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_UTMI_HSRX_CLK480M_Pos 30UL 954 #define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_UTMI_HSRX_CLK480M_Msk 0x40000000UL 955 #define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_UTMI_HSTX_CLK480M_Pos 31UL 956 #define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_UTMI_HSTX_CLK480M_Msk 0x80000000UL 957 /* MXS40USBHSDEV_USBHSPHY.VREFGEN_CONTROL */ 958 #define USBHSPHY_VREFGEN_CONTROL_TED_SEL_0_Pos 0UL 959 #define USBHSPHY_VREFGEN_CONTROL_TED_SEL_0_Msk 0xFUL 960 #define USBHSPHY_VREFGEN_CONTROL_TED_SEL_1_Pos 4UL 961 #define USBHSPHY_VREFGEN_CONTROL_TED_SEL_1_Msk 0xF0UL 962 #define USBHSPHY_VREFGEN_CONTROL_DED_SEL_0_Pos 8UL 963 #define USBHSPHY_VREFGEN_CONTROL_DED_SEL_0_Msk 0xF00UL 964 #define USBHSPHY_VREFGEN_CONTROL_DED_SEL_1_Pos 12UL 965 #define USBHSPHY_VREFGEN_CONTROL_DED_SEL_1_Msk 0xF000UL 966 #define USBHSPHY_VREFGEN_CONTROL_VREFGEN_ADFT_CTRL_Pos 16UL 967 #define USBHSPHY_VREFGEN_CONTROL_VREFGEN_ADFT_CTRL_Msk 0xF0000UL 968 #define USBHSPHY_VREFGEN_CONTROL_VREFGEN_ADFT_EN_Pos 20UL 969 #define USBHSPHY_VREFGEN_CONTROL_VREFGEN_ADFT_EN_Msk 0x100000UL 970 #define USBHSPHY_VREFGEN_CONTROL_ENABLE_LV_Pos 31UL 971 #define USBHSPHY_VREFGEN_CONTROL_ENABLE_LV_Msk 0x80000000UL 972 /* MXS40USBHSDEV_USBHSPHY.REG_SW_1P2_CONTROL */ 973 #define USBHSPHY_REG_SW_1P2_CONTROL_SW_ADFT_CTRL_Pos 0UL 974 #define USBHSPHY_REG_SW_1P2_CONTROL_SW_ADFT_CTRL_Msk 0xFUL 975 #define USBHSPHY_REG_SW_1P2_CONTROL_SW_ADFT_EN_Pos 4UL 976 #define USBHSPHY_REG_SW_1P2_CONTROL_SW_ADFT_EN_Msk 0x10UL 977 #define USBHSPHY_REG_SW_1P2_CONTROL_USE_REG_Pos 5UL 978 #define USBHSPHY_REG_SW_1P2_CONTROL_USE_REG_Msk 0x20UL 979 #define USBHSPHY_REG_SW_1P2_CONTROL_ENABLE_LV_Pos 31UL 980 #define USBHSPHY_REG_SW_1P2_CONTROL_ENABLE_LV_Msk 0x80000000UL 981 /* MXS40USBHSDEV_USBHSPHY.REG_1P1_CONTROL */ 982 #define USBHSPHY_REG_1P1_CONTROL_ONEP1_ADFT_CTRL_Pos 0UL 983 #define USBHSPHY_REG_1P1_CONTROL_ONEP1_ADFT_CTRL_Msk 0xFUL 984 #define USBHSPHY_REG_1P1_CONTROL_ONEP1_ADFT_EN_Pos 4UL 985 #define USBHSPHY_REG_1P1_CONTROL_ONEP1_ADFT_EN_Msk 0x10UL 986 #define USBHSPHY_REG_1P1_CONTROL_SWITCH_EN_Pos 8UL 987 #define USBHSPHY_REG_1P1_CONTROL_SWITCH_EN_Msk 0x100UL 988 #define USBHSPHY_REG_1P1_CONTROL_ENABLE_LV_Pos 31UL 989 #define USBHSPHY_REG_1P1_CONTROL_ENABLE_LV_Msk 0x80000000UL 990 /* MXS40USBHSDEV_USBHSPHY.REG_2P5_CONTROL */ 991 #define USBHSPHY_REG_2P5_CONTROL_TWOP5_ADFT_CTRL_Pos 0UL 992 #define USBHSPHY_REG_2P5_CONTROL_TWOP5_ADFT_CTRL_Msk 0xFUL 993 #define USBHSPHY_REG_2P5_CONTROL_TWOP5_ADFT_EN_Pos 4UL 994 #define USBHSPHY_REG_2P5_CONTROL_TWOP5_ADFT_EN_Msk 0x10UL 995 #define USBHSPHY_REG_2P5_CONTROL_BYPASS_MODE_Pos 8UL 996 #define USBHSPHY_REG_2P5_CONTROL_BYPASS_MODE_Msk 0x100UL 997 #define USBHSPHY_REG_2P5_CONTROL_ENABLE_LV_Pos 31UL 998 #define USBHSPHY_REG_2P5_CONTROL_ENABLE_LV_Msk 0x80000000UL 999 /* MXS40USBHSDEV_USBHSPHY.IREFGEN_CONTROL */ 1000 #define USBHSPHY_IREFGEN_CONTROL_IREF_ADFT_CTRL_Pos 0UL 1001 #define USBHSPHY_IREFGEN_CONTROL_IREF_ADFT_CTRL_Msk 0xFUL 1002 #define USBHSPHY_IREFGEN_CONTROL_IREF_ADFT_EN_Pos 4UL 1003 #define USBHSPHY_IREFGEN_CONTROL_IREF_ADFT_EN_Msk 0x10UL 1004 #define USBHSPHY_IREFGEN_CONTROL_BYPASS_MODE_Pos 8UL 1005 #define USBHSPHY_IREFGEN_CONTROL_BYPASS_MODE_Msk 0x100UL 1006 #define USBHSPHY_IREFGEN_CONTROL_ENABLE_LV_Pos 31UL 1007 #define USBHSPHY_IREFGEN_CONTROL_ENABLE_LV_Msk 0x80000000UL 1008 /* MXS40USBHSDEV_USBHSPHY.STATUS */ 1009 #define USBHSPHY_STATUS_PLL_LOCK_Pos 0UL 1010 #define USBHSPHY_STATUS_PLL_LOCK_Msk 0x1UL 1011 #define USBHSPHY_STATUS_TEST_PLL_LOCK_Pos 2UL 1012 #define USBHSPHY_STATUS_TEST_PLL_LOCK_Msk 0x4UL 1013 #define USBHSPHY_STATUS_VSTATUSTESTER_Pos 3UL 1014 #define USBHSPHY_STATUS_VSTATUSTESTER_Msk 0x7F8UL 1015 #define USBHSPHY_STATUS_LBSTATUS_Pos 11UL 1016 #define USBHSPHY_STATUS_LBSTATUS_Msk 0x7F800UL 1017 #define USBHSPHY_STATUS_LINE_STATE_Pos 19UL 1018 #define USBHSPHY_STATUS_LINE_STATE_Msk 0x180000UL 1019 #define USBHSPHY_STATUS_HOST_DISCONNECT_Pos 21UL 1020 #define USBHSPHY_STATUS_HOST_DISCONNECT_Msk 0x200000UL 1021 #define USBHSPHY_STATUS_PLL_LOSS_CNT_Pos 22UL 1022 #define USBHSPHY_STATUS_PLL_LOSS_CNT_Msk 0x3C00000UL 1023 #define USBHSPHY_STATUS_BISTOK_Pos 26UL 1024 #define USBHSPHY_STATUS_BISTOK_Msk 0x4000000UL 1025 /* MXS40USBHSDEV_USBHSPHY.INTR0 */ 1026 #define USBHSPHY_INTR0_PLL_LOCK_Pos 0UL 1027 #define USBHSPHY_INTR0_PLL_LOCK_Msk 0x1UL 1028 #define USBHSPHY_INTR0_PLL_LOSS_Pos 1UL 1029 #define USBHSPHY_INTR0_PLL_LOSS_Msk 0x2UL 1030 #define USBHSPHY_INTR0_TEST_PLL_LOCK_Pos 2UL 1031 #define USBHSPHY_INTR0_TEST_PLL_LOCK_Msk 0x4UL 1032 #define USBHSPHY_INTR0_PLL_RUN_AWAY_STICKY_CHANGE_Pos 3UL 1033 #define USBHSPHY_INTR0_PLL_RUN_AWAY_STICKY_CHANGE_Msk 0x8UL 1034 #define USBHSPHY_INTR0_TEST_PLL_RUN_AWAY_STICKY_CHANGE_Pos 4UL 1035 #define USBHSPHY_INTR0_TEST_PLL_RUN_AWAY_STICKY_CHANGE_Msk 0x10UL 1036 #define USBHSPHY_INTR0_ENABLE_VCCD_Pos 5UL 1037 #define USBHSPHY_INTR0_ENABLE_VCCD_Msk 0x20UL 1038 #define USBHSPHY_INTR0_ENABLE_HS_VCCD_Pos 6UL 1039 #define USBHSPHY_INTR0_ENABLE_HS_VCCD_Msk 0x40UL 1040 #define USBHSPHY_INTR0_BISTDONE_Pos 7UL 1041 #define USBHSPHY_INTR0_BISTDONE_Msk 0x80UL 1042 #define USBHSPHY_INTR0_ERRORFLOW_Pos 8UL 1043 #define USBHSPHY_INTR0_ERRORFLOW_Msk 0x100UL 1044 #define USBHSPHY_INTR0_STRESS_OUT_Pos 9UL 1045 #define USBHSPHY_INTR0_STRESS_OUT_Msk 0x200UL 1046 #define USBHSPHY_INTR0_CAL_DONE_Pos 10UL 1047 #define USBHSPHY_INTR0_CAL_DONE_Msk 0x400UL 1048 /* MXS40USBHSDEV_USBHSPHY.INTR0_SET */ 1049 #define USBHSPHY_INTR0_SET_PLL_LOCK_Pos 0UL 1050 #define USBHSPHY_INTR0_SET_PLL_LOCK_Msk 0x1UL 1051 #define USBHSPHY_INTR0_SET_PLL_LOSS_Pos 1UL 1052 #define USBHSPHY_INTR0_SET_PLL_LOSS_Msk 0x2UL 1053 #define USBHSPHY_INTR0_SET_TEST_PLL_LOCK_Pos 2UL 1054 #define USBHSPHY_INTR0_SET_TEST_PLL_LOCK_Msk 0x4UL 1055 #define USBHSPHY_INTR0_SET_PLL_RUN_AWAY_STICKY_CHANGE_Pos 3UL 1056 #define USBHSPHY_INTR0_SET_PLL_RUN_AWAY_STICKY_CHANGE_Msk 0x8UL 1057 #define USBHSPHY_INTR0_SET_TEST_PLL_RUN_AWAY_STICKY_CHANGE_Pos 4UL 1058 #define USBHSPHY_INTR0_SET_TEST_PLL_RUN_AWAY_STICKY_CHANGE_Msk 0x10UL 1059 #define USBHSPHY_INTR0_SET_ENABLE_VCCD_Pos 5UL 1060 #define USBHSPHY_INTR0_SET_ENABLE_VCCD_Msk 0x20UL 1061 #define USBHSPHY_INTR0_SET_ENABLE_HS_VCCD_Pos 6UL 1062 #define USBHSPHY_INTR0_SET_ENABLE_HS_VCCD_Msk 0x40UL 1063 #define USBHSPHY_INTR0_SET_BISTDONE_Pos 7UL 1064 #define USBHSPHY_INTR0_SET_BISTDONE_Msk 0x80UL 1065 #define USBHSPHY_INTR0_SET_ERRORFLOW_Pos 8UL 1066 #define USBHSPHY_INTR0_SET_ERRORFLOW_Msk 0x100UL 1067 #define USBHSPHY_INTR0_SET_STRESS_OUT_Pos 9UL 1068 #define USBHSPHY_INTR0_SET_STRESS_OUT_Msk 0x200UL 1069 #define USBHSPHY_INTR0_SET_CAL_DONE_Pos 10UL 1070 #define USBHSPHY_INTR0_SET_CAL_DONE_Msk 0x400UL 1071 /* MXS40USBHSDEV_USBHSPHY.INTR0_MASK */ 1072 #define USBHSPHY_INTR0_MASK_PLL_LOCK_MASK_Pos 0UL 1073 #define USBHSPHY_INTR0_MASK_PLL_LOCK_MASK_Msk 0x1UL 1074 #define USBHSPHY_INTR0_MASK_PLL_LOSS_MASK_Pos 1UL 1075 #define USBHSPHY_INTR0_MASK_PLL_LOSS_MASK_Msk 0x2UL 1076 #define USBHSPHY_INTR0_MASK_TEST_PLL_LOCK_MASK_Pos 2UL 1077 #define USBHSPHY_INTR0_MASK_TEST_PLL_LOCK_MASK_Msk 0x4UL 1078 #define USBHSPHY_INTR0_MASK_PLL_RUN_AWAY_STICKY_CHANGE_MASK_Pos 3UL 1079 #define USBHSPHY_INTR0_MASK_PLL_RUN_AWAY_STICKY_CHANGE_MASK_Msk 0x8UL 1080 #define USBHSPHY_INTR0_MASK_TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASK_Pos 4UL 1081 #define USBHSPHY_INTR0_MASK_TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASK_Msk 0x10UL 1082 #define USBHSPHY_INTR0_MASK_ENABLE_VCCD_MASK_Pos 5UL 1083 #define USBHSPHY_INTR0_MASK_ENABLE_VCCD_MASK_Msk 0x20UL 1084 #define USBHSPHY_INTR0_MASK_ENABLE_HS_VCCD_MASK_Pos 6UL 1085 #define USBHSPHY_INTR0_MASK_ENABLE_HS_VCCD_MASK_Msk 0x40UL 1086 #define USBHSPHY_INTR0_MASK_BISTDONE_MASK_Pos 7UL 1087 #define USBHSPHY_INTR0_MASK_BISTDONE_MASK_Msk 0x80UL 1088 #define USBHSPHY_INTR0_MASK_ERRORFLOW_MASK_Pos 8UL 1089 #define USBHSPHY_INTR0_MASK_ERRORFLOW_MASK_Msk 0x100UL 1090 #define USBHSPHY_INTR0_MASK_STRESS_OUT_MASK_Pos 9UL 1091 #define USBHSPHY_INTR0_MASK_STRESS_OUT_MASK_Msk 0x200UL 1092 #define USBHSPHY_INTR0_MASK_CAL_DONE_MASK_Pos 10UL 1093 #define USBHSPHY_INTR0_MASK_CAL_DONE_MASK_Msk 0x400UL 1094 /* MXS40USBHSDEV_USBHSPHY.INTR0_MASKED */ 1095 #define USBHSPHY_INTR0_MASKED_PLL_LOCK_MASKED_Pos 0UL 1096 #define USBHSPHY_INTR0_MASKED_PLL_LOCK_MASKED_Msk 0x1UL 1097 #define USBHSPHY_INTR0_MASKED_PLL_LOSS_MASKED_Pos 1UL 1098 #define USBHSPHY_INTR0_MASKED_PLL_LOSS_MASKED_Msk 0x2UL 1099 #define USBHSPHY_INTR0_MASKED_TEST_PLL_LOCK_MASKED_Pos 2UL 1100 #define USBHSPHY_INTR0_MASKED_TEST_PLL_LOCK_MASKED_Msk 0x4UL 1101 #define USBHSPHY_INTR0_MASKED_PLL_RUN_AWAY_STICKY_CHANGE_MASKED_Pos 3UL 1102 #define USBHSPHY_INTR0_MASKED_PLL_RUN_AWAY_STICKY_CHANGE_MASKED_Msk 0x8UL 1103 #define USBHSPHY_INTR0_MASKED_TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASKED_Pos 4UL 1104 #define USBHSPHY_INTR0_MASKED_TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASKED_Msk 0x10UL 1105 #define USBHSPHY_INTR0_MASKED_ENABLE_VCCD_MASKED_Pos 5UL 1106 #define USBHSPHY_INTR0_MASKED_ENABLE_VCCD_MASKED_Msk 0x20UL 1107 #define USBHSPHY_INTR0_MASKED_ENABLE_HS_VCCD_MASKED_Pos 6UL 1108 #define USBHSPHY_INTR0_MASKED_ENABLE_HS_VCCD_MASKED_Msk 0x40UL 1109 #define USBHSPHY_INTR0_MASKED_BISTDONE_MASKED_Pos 7UL 1110 #define USBHSPHY_INTR0_MASKED_BISTDONE_MASKED_Msk 0x80UL 1111 #define USBHSPHY_INTR0_MASKED_ERRORFLOW_MASKED_Pos 8UL 1112 #define USBHSPHY_INTR0_MASKED_ERRORFLOW_MASKED_Msk 0x100UL 1113 #define USBHSPHY_INTR0_MASKED_STRESS_OUT_MASKED_Pos 9UL 1114 #define USBHSPHY_INTR0_MASKED_STRESS_OUT_MASKED_Msk 0x200UL 1115 #define USBHSPHY_INTR0_MASKED_CAL_DONE_MASKED_Pos 10UL 1116 #define USBHSPHY_INTR0_MASKED_CAL_DONE_MASKED_Msk 0x400UL 1117 /* MXS40USBHSDEV_USBHSPHY.SPARE */ 1118 #define USBHSPHY_SPARE_DFT_Pos 0UL 1119 #define USBHSPHY_SPARE_DFT_Msk 0xFFFUL 1120 #define USBHSPHY_SPARE_SPARE0_Pos 12UL 1121 #define USBHSPHY_SPARE_SPARE0_Msk 0xFFF000UL 1122 #define USBHSPHY_SPARE_SPARE1_Pos 24UL 1123 #define USBHSPHY_SPARE_SPARE1_Msk 0xFF000000UL 1124 /* MXS40USBHSDEV_USBHSPHY.AFE_CONTROL_3 */ 1125 #define USBHSPHY_AFE_CONTROL_3_CONTROL_CONN_RPD_Pos 0UL 1126 #define USBHSPHY_AFE_CONTROL_3_CONTROL_CONN_RPD_Msk 0x1UL 1127 #define USBHSPHY_AFE_CONTROL_3_CONN_RPD_DP_VALUE_Pos 1UL 1128 #define USBHSPHY_AFE_CONTROL_3_CONN_RPD_DP_VALUE_Msk 0x2UL 1129 #define USBHSPHY_AFE_CONTROL_3_CONN_RPD_DN_VALUE_Pos 2UL 1130 #define USBHSPHY_AFE_CONTROL_3_CONN_RPD_DN_VALUE_Msk 0x4UL 1131 #define USBHSPHY_AFE_CONTROL_3_CONTROL_CONN_RPU_Pos 3UL 1132 #define USBHSPHY_AFE_CONTROL_3_CONTROL_CONN_RPU_Msk 0x8UL 1133 #define USBHSPHY_AFE_CONTROL_3_CONN_RPU1_VALUE_Pos 4UL 1134 #define USBHSPHY_AFE_CONTROL_3_CONN_RPU1_VALUE_Msk 0x10UL 1135 #define USBHSPHY_AFE_CONTROL_3_CONN_RPU2_VALUE_Pos 5UL 1136 #define USBHSPHY_AFE_CONTROL_3_CONN_RPU2_VALUE_Msk 0x20UL 1137 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_DED_Pos 6UL 1138 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_DED_Msk 0x40UL 1139 #define USBHSPHY_AFE_CONTROL_3_HS_DED_EN_VALUE_Pos 7UL 1140 #define USBHSPHY_AFE_CONTROL_3_HS_DED_EN_VALUE_Msk 0x80UL 1141 #define USBHSPHY_AFE_CONTROL_3_HS_DED_RESET_VALUE_Pos 8UL 1142 #define USBHSPHY_AFE_CONTROL_3_HS_DED_RESET_VALUE_Msk 0x100UL 1143 #define USBHSPHY_AFE_CONTROL_3_HS_DED_START_VALUE_Pos 9UL 1144 #define USBHSPHY_AFE_CONTROL_3_HS_DED_START_VALUE_Msk 0x200UL 1145 #define USBHSPHY_AFE_CONTROL_3_CONTROL_IREF_EN_Pos 10UL 1146 #define USBHSPHY_AFE_CONTROL_3_CONTROL_IREF_EN_Msk 0x400UL 1147 #define USBHSPHY_AFE_CONTROL_3_IREF_EN_VALUE_Pos 11UL 1148 #define USBHSPHY_AFE_CONTROL_3_IREF_EN_VALUE_Msk 0x800UL 1149 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_RX_EN_Pos 12UL 1150 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_RX_EN_Msk 0x1000UL 1151 #define USBHSPHY_AFE_CONTROL_3_HS_RX_EN_VALUE_Pos 13UL 1152 #define USBHSPHY_AFE_CONTROL_3_HS_RX_EN_VALUE_Msk 0x2000UL 1153 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_RX_BUF_ON_Pos 14UL 1154 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_RX_BUF_ON_Msk 0x4000UL 1155 #define USBHSPHY_AFE_CONTROL_3_HS_RX_BUF_ON_VALUE_Pos 15UL 1156 #define USBHSPHY_AFE_CONTROL_3_HS_RX_BUF_ON_VALUE_Msk 0x8000UL 1157 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_TED_EN_Pos 16UL 1158 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_TED_EN_Msk 0x10000UL 1159 #define USBHSPHY_AFE_CONTROL_3_HS_TED_EN_VALUE_Pos 17UL 1160 #define USBHSPHY_AFE_CONTROL_3_HS_TED_EN_VALUE_Msk 0x20000UL 1161 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_TX_EN_SLOW_Pos 18UL 1162 #define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_TX_EN_SLOW_Msk 0x40000UL 1163 #define USBHSPHY_AFE_CONTROL_3_HS_TX_EN_SLOW_VALUE_Pos 19UL 1164 #define USBHSPHY_AFE_CONTROL_3_HS_TX_EN_SLOW_VALUE_Msk 0x80000UL 1165 #define USBHSPHY_AFE_CONTROL_3_CONTROL_RPU_SEL_Pos 20UL 1166 #define USBHSPHY_AFE_CONTROL_3_CONTROL_RPU_SEL_Msk 0x100000UL 1167 #define USBHSPHY_AFE_CONTROL_3_RPU_SEL_VALUE_Pos 21UL 1168 #define USBHSPHY_AFE_CONTROL_3_RPU_SEL_VALUE_Msk 0x200000UL 1169 #define USBHSPHY_AFE_CONTROL_3_CONTROL_SE_RX_EN_DP_Pos 22UL 1170 #define USBHSPHY_AFE_CONTROL_3_CONTROL_SE_RX_EN_DP_Msk 0x400000UL 1171 #define USBHSPHY_AFE_CONTROL_3_SE_RX_EN_DP_VALUE_Pos 23UL 1172 #define USBHSPHY_AFE_CONTROL_3_SE_RX_EN_DP_VALUE_Msk 0x800000UL 1173 #define USBHSPHY_AFE_CONTROL_3_CONTROL_SE_RX_EN_DN_Pos 24UL 1174 #define USBHSPHY_AFE_CONTROL_3_CONTROL_SE_RX_EN_DN_Msk 0x1000000UL 1175 #define USBHSPHY_AFE_CONTROL_3_SE_RX_EN_DN_VALUE_Pos 25UL 1176 #define USBHSPHY_AFE_CONTROL_3_SE_RX_EN_DN_VALUE_Msk 0x2000000UL 1177 #define USBHSPHY_AFE_CONTROL_3_CONTROL_LS_NFS_Pos 26UL 1178 #define USBHSPHY_AFE_CONTROL_3_CONTROL_LS_NFS_Msk 0x4000000UL 1179 #define USBHSPHY_AFE_CONTROL_3_LS_NFS_VALUE_Pos 27UL 1180 #define USBHSPHY_AFE_CONTROL_3_LS_NFS_VALUE_Msk 0x8000000UL 1181 #define USBHSPHY_AFE_CONTROL_3_CONTROL_LSFS_DIFF_RX_EN_Pos 28UL 1182 #define USBHSPHY_AFE_CONTROL_3_CONTROL_LSFS_DIFF_RX_EN_Msk 0x10000000UL 1183 #define USBHSPHY_AFE_CONTROL_3_LSFS_DIFF_RX_EN_VALUE_Pos 29UL 1184 #define USBHSPHY_AFE_CONTROL_3_LSFS_DIFF_RX_EN_VALUE_Msk 0x20000000UL 1185 #define USBHSPHY_AFE_CONTROL_3_CONTROL_LFS_TX_EN_Pos 30UL 1186 #define USBHSPHY_AFE_CONTROL_3_CONTROL_LFS_TX_EN_Msk 0x40000000UL 1187 #define USBHSPHY_AFE_CONTROL_3_LFS_TX_EN_VALUE_Pos 31UL 1188 #define USBHSPHY_AFE_CONTROL_3_LFS_TX_EN_VALUE_Msk 0x80000000UL 1189 /* MXS40USBHSDEV_USBHSPHY.AFE_CONTROL_4 */ 1190 #define USBHSPHY_AFE_CONTROL_4_CONTROL_LFS_TX_IN_Pos 0UL 1191 #define USBHSPHY_AFE_CONTROL_4_CONTROL_LFS_TX_IN_Msk 0x1UL 1192 #define USBHSPHY_AFE_CONTROL_4_LFS_TX_IN_VALUE_Pos 1UL 1193 #define USBHSPHY_AFE_CONTROL_4_LFS_TX_IN_VALUE_Msk 0x2UL 1194 #define USBHSPHY_AFE_CONTROL_4_CONTROL_LFS_TX_ON_Pos 2UL 1195 #define USBHSPHY_AFE_CONTROL_4_CONTROL_LFS_TX_ON_Msk 0x4UL 1196 #define USBHSPHY_AFE_CONTROL_4_LFS_TX_ON_VALUE_Pos 3UL 1197 #define USBHSPHY_AFE_CONTROL_4_LFS_TX_ON_VALUE_Msk 0x8UL 1198 #define USBHSPHY_AFE_CONTROL_4_CONTROL_ENASE0_Pos 4UL 1199 #define USBHSPHY_AFE_CONTROL_4_CONTROL_ENASE0_Msk 0x10UL 1200 #define USBHSPHY_AFE_CONTROL_4_ENASE0_VALUE_Pos 5UL 1201 #define USBHSPHY_AFE_CONTROL_4_ENASE0_VALUE_Msk 0x20UL 1202 #define USBHSPHY_AFE_CONTROL_4_CONTROL_ENASE1_Pos 6UL 1203 #define USBHSPHY_AFE_CONTROL_4_CONTROL_ENASE1_Msk 0x40UL 1204 #define USBHSPHY_AFE_CONTROL_4_ENASE1_VALUE_Pos 7UL 1205 #define USBHSPHY_AFE_CONTROL_4_ENASE1_VALUE_Msk 0x80UL 1206 #define USBHSPHY_AFE_CONTROL_4_CONTROL_CAL_Pos 8UL 1207 #define USBHSPHY_AFE_CONTROL_4_CONTROL_CAL_Msk 0x100UL 1208 #define USBHSPHY_AFE_CONTROL_4_CAL_VALUE_Pos 9UL 1209 #define USBHSPHY_AFE_CONTROL_4_CAL_VALUE_Msk 0x3E00UL 1210 #define USBHSPHY_AFE_CONTROL_4_ONCAL_VALUE_Pos 14UL 1211 #define USBHSPHY_AFE_CONTROL_4_ONCAL_VALUE_Msk 0x4000UL 1212 #define USBHSPHY_AFE_CONTROL_4_CAL_F1_VALUE_Pos 15UL 1213 #define USBHSPHY_AFE_CONTROL_4_CAL_F1_VALUE_Msk 0x8000UL 1214 #define USBHSPHY_AFE_CONTROL_4_CAL_F2_VALUE_Pos 16UL 1215 #define USBHSPHY_AFE_CONTROL_4_CAL_F2_VALUE_Msk 0x10000UL 1216 #define USBHSPHY_AFE_CONTROL_4_CONTROL_SE_TX_IN_EDN_Pos 17UL 1217 #define USBHSPHY_AFE_CONTROL_4_CONTROL_SE_TX_IN_EDN_Msk 0x20000UL 1218 #define USBHSPHY_AFE_CONTROL_4_SE_TX_IN_EDN_VALUE_Pos 18UL 1219 #define USBHSPHY_AFE_CONTROL_4_SE_TX_IN_EDN_VALUE_Msk 0x40000UL 1220 #define USBHSPHY_AFE_CONTROL_4_CONTROL_SE_TX_EN_EDN_Pos 19UL 1221 #define USBHSPHY_AFE_CONTROL_4_CONTROL_SE_TX_EN_EDN_Msk 0x80000UL 1222 #define USBHSPHY_AFE_CONTROL_4_SE_TX_EN_EDN_VALUE_Pos 20UL 1223 #define USBHSPHY_AFE_CONTROL_4_SE_TX_EN_EDN_VALUE_Msk 0x100000UL 1224 #define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_PREE_EN_Pos 21UL 1225 #define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_PREE_EN_Msk 0x200000UL 1226 #define USBHSPHY_AFE_CONTROL_4_HS_PREE_EN_VALUE_Pos 22UL 1227 #define USBHSPHY_AFE_CONTROL_4_HS_PREE_EN_VALUE_Msk 0x400000UL 1228 #define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_TERM_EN_Pos 23UL 1229 #define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_TERM_EN_Msk 0x800000UL 1230 #define USBHSPHY_AFE_CONTROL_4_HS_TERM_EN_VALUE_Pos 24UL 1231 #define USBHSPHY_AFE_CONTROL_4_HS_TERM_EN_VALUE_Msk 0x1000000UL 1232 #define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_TX_EN_Pos 25UL 1233 #define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_TX_EN_Msk 0x2000000UL 1234 #define USBHSPHY_AFE_CONTROL_4_HS_TX_EN_VALUE_Pos 26UL 1235 #define USBHSPHY_AFE_CONTROL_4_HS_TX_EN_VALUE_Msk 0x4000000UL 1236 #define USBHSPHY_AFE_CONTROL_4_HS_TX_EN_FAST_VALUE_Pos 27UL 1237 #define USBHSPHY_AFE_CONTROL_4_HS_TX_EN_FAST_VALUE_Msk 0x8000000UL 1238 /* MXS40USBHSDEV_USBHSPHY.UTMI_CONTROL_2 */ 1239 #define USBHSPHY_UTMI_CONTROL_2_DED_RESET_ASSERT_X6_BIT_Pos 0UL 1240 #define USBHSPHY_UTMI_CONTROL_2_DED_RESET_ASSERT_X6_BIT_Msk 0x7UL 1241 #define USBHSPHY_UTMI_CONTROL_2_DED_RESET_ASSERT_BIT_Pos 3UL 1242 #define USBHSPHY_UTMI_CONTROL_2_DED_RESET_ASSERT_BIT_Msk 0x38UL 1243 #define USBHSPHY_UTMI_CONTROL_2_DED_RESET_DEASSERT_X6_BIT_Pos 6UL 1244 #define USBHSPHY_UTMI_CONTROL_2_DED_RESET_DEASSERT_X6_BIT_Msk 0x1C0UL 1245 #define USBHSPHY_UTMI_CONTROL_2_DED_RESET_DEASSERT_BIT_Pos 9UL 1246 #define USBHSPHY_UTMI_CONTROL_2_DED_RESET_DEASSERT_BIT_Msk 0xE00UL 1247 #define USBHSPHY_UTMI_CONTROL_2_DED_START_ASSERT_X6_BIT_Pos 12UL 1248 #define USBHSPHY_UTMI_CONTROL_2_DED_START_ASSERT_X6_BIT_Msk 0x7000UL 1249 #define USBHSPHY_UTMI_CONTROL_2_DED_START_ASSERT_BIT_Pos 15UL 1250 #define USBHSPHY_UTMI_CONTROL_2_DED_START_ASSERT_BIT_Msk 0x38000UL 1251 #define USBHSPHY_UTMI_CONTROL_2_DED_START_DEASSERT_X6_BIT_Pos 18UL 1252 #define USBHSPHY_UTMI_CONTROL_2_DED_START_DEASSERT_X6_BIT_Msk 0x1C0000UL 1253 #define USBHSPHY_UTMI_CONTROL_2_DED_START_DEASSERT_BIT_Pos 21UL 1254 #define USBHSPHY_UTMI_CONTROL_2_DED_START_DEASSERT_BIT_Msk 0xE00000UL 1255 /* MXS40USBHSDEV_USBHSPHY.PLL_TRIMS */ 1256 #define USBHSPHY_PLL_TRIMS_RUN_AWAY_Pos 0UL 1257 #define USBHSPHY_PLL_TRIMS_RUN_AWAY_Msk 0x3UL 1258 #define USBHSPHY_PLL_TRIMS_CP_CUR_Pos 2UL 1259 #define USBHSPHY_PLL_TRIMS_CP_CUR_Msk 0xCUL 1260 #define USBHSPHY_PLL_TRIMS_LDO_VCO_Pos 4UL 1261 #define USBHSPHY_PLL_TRIMS_LDO_VCO_Msk 0x70UL 1262 #define USBHSPHY_PLL_TRIMS_LDO_CORE_Pos 7UL 1263 #define USBHSPHY_PLL_TRIMS_LDO_CORE_Msk 0x380UL 1264 #define USBHSPHY_PLL_TRIMS_TEST_RUN_AWAY_Pos 10UL 1265 #define USBHSPHY_PLL_TRIMS_TEST_RUN_AWAY_Msk 0xC00UL 1266 #define USBHSPHY_PLL_TRIMS_TEST_CP_CUR_Pos 12UL 1267 #define USBHSPHY_PLL_TRIMS_TEST_CP_CUR_Msk 0x3000UL 1268 #define USBHSPHY_PLL_TRIMS_TEST_LDO_VCO_Pos 14UL 1269 #define USBHSPHY_PLL_TRIMS_TEST_LDO_VCO_Msk 0x1C000UL 1270 #define USBHSPHY_PLL_TRIMS_TEST_LDO_CORE_Pos 17UL 1271 #define USBHSPHY_PLL_TRIMS_TEST_LDO_CORE_Msk 0xE0000UL 1272 /* MXS40USBHSDEV_USBHSPHY.AFE_TRIMS */ 1273 #define USBHSPHY_AFE_TRIMS_TRIM_VREF_Pos 0UL 1274 #define USBHSPHY_AFE_TRIMS_TRIM_VREF_Msk 0xFUL 1275 #define USBHSPHY_AFE_TRIMS_TRIM_IREF_Pos 4UL 1276 #define USBHSPHY_AFE_TRIMS_TRIM_IREF_Msk 0xF0UL 1277 #define USBHSPHY_AFE_TRIMS_TRIM_VREG_2P5_Pos 8UL 1278 #define USBHSPHY_AFE_TRIMS_TRIM_VREG_2P5_Msk 0xF00UL 1279 #define USBHSPHY_AFE_TRIMS_TRIM_VREG_1P1_Pos 12UL 1280 #define USBHSPHY_AFE_TRIMS_TRIM_VREG_1P1_Msk 0xF000UL 1281 #define USBHSPHY_AFE_TRIMS_TRIM_REG_SW_1P2_Pos 16UL 1282 #define USBHSPHY_AFE_TRIMS_TRIM_REG_SW_1P2_Msk 0xF0000UL 1283 #define USBHSPHY_AFE_TRIMS_TRIM_AFE_HS_IREF_Pos 20UL 1284 #define USBHSPHY_AFE_TRIMS_TRIM_AFE_HS_IREF_Msk 0x700000UL 1285 #define USBHSPHY_AFE_TRIMS_TRIM_VREF_600M_0_Pos 23UL 1286 #define USBHSPHY_AFE_TRIMS_TRIM_VREF_600M_0_Msk 0x7800000UL 1287 #define USBHSPHY_AFE_TRIMS_TRIM_VREF_600M_1_Pos 27UL 1288 #define USBHSPHY_AFE_TRIMS_TRIM_VREF_600M_1_Msk 0x78000000UL 1289 1290 1291 #endif /* _CYIP_MXS40USBHSDEV_H_ */ 1292 1293 1294 /* [] END OF FILE */ 1295
