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Searched refs:USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT_Pos (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_mxs40usbhsdev.h326 #define USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT_Pos 7UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h2126 #define USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT (1U << USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT_Pos)