1 /***************************************************************************//** 2 * \file cyip_usb32dev.h 3 * 4 * \brief 5 * USB32DEV IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_USB32DEV_H_ 28 #define _CYIP_USB32DEV_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * USB32DEV 34 *******************************************************************************/ 35 36 #define USB32DEV_MAIN_SECTION_SIZE 0x00001000UL 37 #define USB32DEV_EPM_SECTION_SIZE 0x00001000UL 38 #define USB32DEV_LNK_SECTION_SIZE 0x00001000UL 39 #define USB32DEV_PROT_SECTION_SIZE 0x00001000UL 40 #define USB32DEV_PHYSS_USB40PHY_TOP_SECTION_SIZE 0x00000800UL 41 #define USB32DEV_PHYSS_USB40PHY_RX_SECTION_SIZE 0x00000100UL 42 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_SECTION_SIZE 0x00000100UL 43 #define USB32DEV_PHYSS_USB40PHY_SECTION_SIZE 0x00001000UL 44 #define USB32DEV_PHYSS_SECTION_SIZE 0x00002000UL 45 #define USB32DEV_ADAPTER_DMA_SCK_SECTION_SIZE 0x00000080UL 46 #define USB32DEV_ADAPTER_DMA_SCK_GBL_SECTION_SIZE 0x00000100UL 47 #define USB32DEV_ADAPTER_DMA_SECTION_SIZE 0x00010000UL 48 #define USB32DEV_SECTION_SIZE 0x00030000UL 49 50 /** 51 * \brief USB32 Main Register (USB32DEV_MAIN) 52 */ 53 typedef struct { 54 __IOM uint32_t CTRL; /*!< 0x00000000 Main Control Register */ 55 __IOM uint32_t INTR; /*!< 0x00000004 Main Active Interrupt Register */ 56 __IOM uint32_t INTR_SET; /*!< 0x00000008 Main Active Interrupt Set Register */ 57 __IOM uint32_t INTR_MASK; /*!< 0x0000000C Main Active Interrupt Mask Register */ 58 __IM uint32_t INTR_MASKED; /*!< 0x00000010 Main Active Interrupt Masked Register */ 59 __IOM uint32_t DDFT_MUX; /*!< 0x00000014 DDFT0/1 mux selection Register */ 60 __IOM uint32_t GPIO_DDFT_MUX; /*!< 0x00000018 GPIO DDFT0/1 mux selection Register */ 61 __IOM uint32_t DEBUG_CONFIG; /*!< 0x0000001C Debug Configuration Register */ 62 __IOM uint32_t DEBUG_MUX_SEL; /*!< 0x00000020 Debug MUX selection Configuration Register */ 63 __IOM uint32_t LOOPBACK; /*!< 0x00000024 LOOPBACK Configuration Register */ 64 __IM uint32_t RESERVED; 65 __IOM uint32_t BUG_FIX; /*!< 0x0000002C BUG Fix Configuration Register */ 66 __IM uint32_t RESERVED1[1012]; 67 } USB32DEV_MAIN_V1_Type; /*!< Size = 4096 (0x1000) */ 68 69 /** 70 * \brief USB32 Controller End Point Manager Registers (USB32DEV_EPM) 71 */ 72 typedef struct { 73 __IOM uint32_t EEPM_CS; /*!< 0x00000000 Egress EPM Retry Buffer Status */ 74 __IOM uint32_t IEPM_CS; /*!< 0x00000004 Ingress EPM Control and Status */ 75 __IOM uint32_t IEPM_MULT; /*!< 0x00000008 Ingress EPM MULT function Control */ 76 __IM uint32_t RESERVED[13]; 77 __IOM uint32_t EEPM_ENDPOINT[16]; /*!< 0x00000040 Egress EPM per Endpoint Control and Status */ 78 __IOM uint32_t IEPM_ENDPOINT[16]; /*!< 0x00000080 Ingress EPM Per Endpoint Control and Status */ 79 __IM uint32_t IEPM_FIFO; /*!< 0x000000C0 Ingress EPM FIFO Entry */ 80 __IOM uint32_t EEPM_VALID; /*!< 0x000000C4 Egress EPM Retry Buffer Valid packet */ 81 __IM uint32_t RESERVED1[15]; 82 __IOM uint32_t EEPM_RETRY_OFFSET[16]; /*!< 0x00000104 Egress EPM Retry Buffer EndPoint offset */ 83 __IOM uint32_t EEPM_INJECT_CRC32_ERROR[16]; /*!< 0x00000144 Egress EPM CRC32 Error injection control */ 84 __IM uint32_t RESERVED2[927]; 85 } USB32DEV_EPM_V1_Type; /*!< Size = 4096 (0x1000) */ 86 87 /** 88 * \brief USB32 SuperSpeedPlus Device Controller Link Layer Registers (USB32DEV_LNK) 89 */ 90 typedef struct { 91 __IOM uint32_t LNK_CONF; /*!< 0x00000000 Link Configuration Register */ 92 __IOM uint32_t LNK_INTR; /*!< 0x00000004 Link Interrupts */ 93 __IOM uint32_t LNK_INTR_SET; /*!< 0x00000008 Link Interrupts Set */ 94 __IOM uint32_t LNK_INTR_MASK; /*!< 0x0000000C Link Interrupts Mask */ 95 __IM uint32_t LNK_INTR_MASKED; /*!< 0x00000010 Link Interrupts Masked */ 96 __IOM uint32_t LNK_ERROR_CONF; /*!< 0x00000014 Link Error Counter Configuration */ 97 __IOM uint32_t LNK_ERROR_STATUS; /*!< 0x00000018 Link Error Status Register */ 98 __IM uint32_t LNK_ERROR_COUNT; /*!< 0x0000001C Error Counter Register */ 99 __IOM uint32_t LNK_ERROR_COUNT_THRESHOLD; /*!< 0x00000020 Error Count Thresholds */ 100 __IOM uint32_t LNK_PHY_CONF; /*!< 0x00000024 USB 3.0 PHY Configuration */ 101 __IM uint32_t LNK_PHY_STATUS; /*!< 0x00000028 USB 3.0 PHY Status */ 102 __IM uint32_t RESERVED[7]; 103 __IOM uint32_t LNK_PHY_ERROR_CONF; /*!< 0x00000048 PHY Error Counter Configuration */ 104 __IOM uint32_t LNK_PHY_ERROR_STATUS; /*!< 0x0000004C PHY Error Status Register */ 105 __IOM uint32_t LNK_PHY_TRAINING_HOLDOFF; /*!< 0x00000050 PHY Training Hold Off */ 106 __IM uint32_t LNK_COMMAND_WORD; /*!< 0x00000054 Link Command Word (received) */ 107 __IOM uint32_t LNK_DEVICE_POWER_CONTROL; /*!< 0x00000058 USB 3.0 Device Power State Control */ 108 __IOM uint32_t LNK_LTSSM_STATE; /*!< 0x0000005C Link Training Status State Machine (LTSSM) State */ 109 __IOM uint32_t LNK_LOOPBACK_INIT; /*!< 0x00000060 Loopback LFSR Initial Value */ 110 __IOM uint32_t LNK_LOOPBACK_GENERATOR; /*!< 0x00000064 Loopback LFSR Transmitter Generator Polynomial */ 111 __IOM uint32_t LNK_LTSSM_OBSERVE; /*!< 0x00000068 Link Training Status State Machine (LTSSM) Observation */ 112 __IOM uint32_t LNK_LFPS_OBSERVE; /*!< 0x0000006C LFPS Receiver Observability */ 113 __IOM uint32_t LNK_LFPS_TX_POLLING_BURST; /*!< 0x00000070 LFPS Polling Transmit Configuration */ 114 __IOM uint32_t LNK_LFPS_TX_POLLING_REPEAT; /*!< 0x00000074 LFPS Polling Transmit Configuration */ 115 __IOM uint32_t LNK_LFPS_TX_PING_BURST; /*!< 0x00000078 LFPS Ping Transmit Configuration */ 116 __IOM uint32_t LNK_LFPS_TX_PING_REPEAT; /*!< 0x0000007C LFPS Ping Transmit Configuration */ 117 __IOM uint32_t LNK_LFPS_TX_U1_EXIT; /*!< 0x00000080 LFPS U1_EXIT Transmit Configuration */ 118 __IOM uint32_t LNK_LFPS_TX_U2_EXIT; /*!< 0x00000084 LFPS U2_EXIT Transmit Configuration */ 119 __IOM uint32_t LNK_LFPS_TX_U3_EXIT; /*!< 0x00000088 LFPS U3 Exit Transmit Configuration */ 120 __IOM uint32_t LNK_LFPS_RX_POLLING_BURST; /*!< 0x0000008C LFPS Polling Detect Configuration */ 121 __IOM uint32_t LNK_LFPS_RX_POLLING_REPEAT; /*!< 0x00000090 LFPS Polling Detect Configuration */ 122 __IOM uint32_t LNK_LFPS_RX_PING; /*!< 0x00000094 LFPS Ping Detect Configuration */ 123 __IOM uint32_t LNK_LFPS_RX_RESET; /*!< 0x00000098 LFPS Reset Detect Configuration */ 124 __IOM uint32_t LNK_LFPS_RX_U1_EXIT; /*!< 0x0000009C LFPS U1 Exit Detect Configuration */ 125 __IOM uint32_t LNK_LFPS_RX_U2_EXIT; /*!< 0x000000A0 LFPS U2 Exit Detect Configuration */ 126 __IOM uint32_t LNK_LFPS_RX_U3_EXIT; /*!< 0x000000A4 LFPS U3 Exit Detect Configuration */ 127 __IOM uint32_t LNK_LFPS_RX_U1_HANDSHAKE; /*!< 0x000000A8 LFPS U1 Exit Handshake Configuration */ 128 __IOM uint32_t LNK_LFPS_RX_U2_HANDSHAKE; /*!< 0x000000AC LFPS U2 Exit Handshake Configuration */ 129 __IOM uint32_t LNK_LFPS_RX_U3_HANDSHAKE; /*!< 0x000000B0 LFPS U3 Exit Handshake Configuration */ 130 __IOM uint32_t LNK_LFPS_RX_LOOPBACK_EXIT; /*!< 0x000000B4 LFPS Loopback Exit Detect Configuration */ 131 __IOM uint32_t LNK_LFPS_RX_LOOPBACK_HANDSHAKE; /*!< 0x000000B8 LFPS Loopback Exit Handshake Configuration */ 132 __IM uint32_t LNK_LFPS_RX_IDLE; /*!< 0x000000BC LFPS Idle Time */ 133 __IM uint32_t LNK_LFPS_RX_BURST; /*!< 0x000000C0 LFPS Burst Length */ 134 __IM uint32_t LNK_LFPS_RX_TIME; /*!< 0x000000C4 LFPS Idle Counter */ 135 __IM uint32_t LNK_PENDING_HP_TIMER; /*!< 0x000000C8 Header Packet LGOOD/LBAD Timer */ 136 __IOM uint32_t LNK_PENDING_HP_TIMEOUT; /*!< 0x000000CC Header Packet LGOOD/LBAD Timeout */ 137 __IM uint32_t LNK_CREDIT_HP_TIMER; /*!< 0x000000D0 Header Packet LCRDx Timer */ 138 __IOM uint32_t LNK_CREDIT_HP_TIMEOUT; /*!< 0x000000D4 Header Packet LCRDx Timeout */ 139 __IM uint32_t LNK_PM_TIMER; /*!< 0x000000D8 Power Mode Timer */ 140 __IOM uint32_t LNK_PM_LC_TIMEOUT; /*!< 0x000000DC Power Mode PM_LC_TIMER Timeout */ 141 __IOM uint32_t LNK_PM_ENTRY_TIMEOUT; /*!< 0x000000E0 Power Mode PM_ENTRY_TIMER Timeout */ 142 __IOM uint32_t LNK_PM_UX_EXIT_TIMEOUT; /*!< 0x000000E4 Power Mode Ux_EXIT_TIMER Timeout */ 143 __IM uint32_t LNK_LTSSM_TIMER; /*!< 0x000000E8 LTSSM Timer Register */ 144 __IOM uint32_t LNK_LTSSM_TIMEOUT; /*!< 0x000000EC LTSSM Timeout Observability Register */ 145 __IM uint32_t RESERVED1[2]; 146 __IOM uint32_t LNK_LTSSM_RX_DETECT_PERIOD; /*!< 0x000000F8 LTSSM RxDetect Period */ 147 __IOM uint32_t LNK_LTSSM_LUP_PERIOD; /*!< 0x000000FC LTSSM LUP Period */ 148 __IOM uint32_t LNK_LTSSM_SS_INACTIVE_PERIOD; /*!< 0x00000100 LTSSM SS.Inactive Timeout */ 149 __IOM uint32_t LNK_LTSSM_POLLING_LFPS_TIMEOUT; /*!< 0x00000104 LTSSM Polling LFPS Timeout */ 150 __IOM uint32_t LNK_LTSSM_POLLING_ACTIVE_TIMEOUT; /*!< 0x00000108 LTSSM Polling Active Timeout */ 151 __IOM uint32_t LNK_LTSSM_POLLING_CONFIG_TIMEOUT; /*!< 0x0000010C LTSSM Polling Configuration Timeout */ 152 __IOM uint32_t LNK_LTSSM_POLLING_IDLE_TIMEOUT; /*!< 0x00000110 LTSSM Polling Idle Timeout */ 153 __IOM uint32_t LNK_LTSSM_U1_EXIT_TIMEOUT; /*!< 0x00000114 LTSSM U1 Exit Timeout */ 154 __IOM uint32_t LNK_LTSSM_U2_EXIT_TIMEOUT; /*!< 0x00000118 LTSSM U2 Exit Timeout */ 155 __IOM uint32_t LNK_LTSSM_U3_EXIT_TIMEOUT; /*!< 0x0000011C LTSSM U3 Exit Timeout */ 156 __IOM uint32_t LNK_LTSSM_HOT_RESET_ACTIVE_TIMEOUT; /*!< 0x00000120 LTSSM Hot Reset Active Timeout */ 157 __IOM uint32_t LNK_LTSSM_HOT_RESET_EXIT_TIMEOUT; /*!< 0x00000124 LTSSM Hot Reset Exit Timeout */ 158 __IOM uint32_t LNK_LTSSM_LOOPBACK_EXIT_TIMEOUT; /*!< 0x00000128 LTSSM Loopback Exit Timeout */ 159 __IOM uint32_t LNK_LTSSM_RECOVERY_IDLE_TIMEOUT; /*!< 0x0000012C LTSSM Recovery Idle Timeout */ 160 __IOM uint32_t LNK_LTSSM_RECOVERY_ACTIVE_TIMEOUT; /*!< 0x00000130 LTSSM Recovery Active Timeout */ 161 __IOM uint32_t LNK_LTSSM_RECOVERY_CONFIG_TIMEOUT; /*!< 0x00000134 LTSSM Recovery.Configuration Timeout */ 162 __IOM uint32_t LNK_LTSSM_LDN_TIMEOUT; /*!< 0x00000138 LTSSM LDN Received Timeout */ 163 __IM uint32_t LNK_LTSSM_LDN_TIMER; /*!< 0x0000013C LTSSM LDN Received Timer */ 164 __IOM uint32_t LNK_COMPLIANCE_PATTERN_0; /*!< 0x00000140 Compliance Pattern CP0 */ 165 __IOM uint32_t LNK_COMPLIANCE_PATTERN_1; /*!< 0x00000144 Compliance Pattern CP1 */ 166 __IOM uint32_t LNK_COMPLIANCE_PATTERN_2; /*!< 0x00000148 Compliance Pattern CP2 */ 167 __IOM uint32_t LNK_COMPLIANCE_PATTERN_3; /*!< 0x0000014C Compliance Pattern CP3 */ 168 __IOM uint32_t LNK_COMPLIANCE_PATTERN_4; /*!< 0x00000150 Compliance Pattern CP4 */ 169 __IOM uint32_t LNK_COMPLIANCE_PATTERN_5; /*!< 0x00000154 Compliance Pattern CP5 */ 170 __IOM uint32_t LNK_COMPLIANCE_PATTERN_6; /*!< 0x00000158 Compliance Pattern CP6 */ 171 __IOM uint32_t LNK_COMPLIANCE_PATTERN_7; /*!< 0x0000015C Compliance Pattern CP7 */ 172 __IOM uint32_t LNK_COMPLIANCE_PATTERN_8; /*!< 0x00000160 Compliance Pattern CP8 */ 173 __IOM uint32_t LNK_DEBUG_BUFFER_CTRL; /*!< 0x00000164 Buffer direct access control */ 174 __IM uint32_t LNK_DATARATE_CHG_OBSERVE; /*!< 0x00000168 Dtat Rate Observability */ 175 __IOM uint32_t LNK_LFPS_TX_POLLING_BURST_GEN2; /*!< 0x0000016C LFPS Polling Transmit Gen2 Configuration */ 176 __IOM uint32_t LNK_LFPS_TX_POLLING_REPEAT_GEN2; /*!< 0x00000170 LFPS Polling Transmit Gen2 Configuration */ 177 __IOM uint32_t LNK_LFPS_TX_PING_BURST_GEN2; /*!< 0x00000174 LFPS Ping Transmit Gen2 Configuration */ 178 __IOM uint32_t LNK_LFPS_TX_PING_REPEAT_GEN2; /*!< 0x00000178 LFPS Ping Transmit Gen2 Configuration */ 179 __IOM uint32_t LNK_LFPS_TX_U1_EXIT_GEN2; /*!< 0x0000017C LFPS U1_EXIT Transmit Gen2 Configuration */ 180 __IOM uint32_t LNK_LFPS_TX_U2_EXIT_GEN2; /*!< 0x00000180 LFPS U2_EXIT Transmit Gen2 Configuration */ 181 __IOM uint32_t LNK_LFPS_TX_U3_EXIT_GEN2; /*!< 0x00000184 LFPS U3 Exit Transmit Gen2 Configuration */ 182 __IOM uint32_t LNK_LFPS_RX_POLLING_BURST_GEN2; /*!< 0x00000188 LFPS Polling Detect Gen2 Configuration */ 183 __IOM uint32_t LNK_LFPS_RX_POLLING_REPEAT_GEN2; /*!< 0x0000018C LFPS Polling Detect Gen2 Configuration */ 184 __IOM uint32_t LNK_LFPS_RX_PING_GEN2; /*!< 0x00000190 LFPS Ping Detect Gen2 Configuration */ 185 __IOM uint32_t LNK_LFPS_RX_RESET_GEN2; /*!< 0x00000194 LFPS Reset Detect Gen2 Configuration */ 186 __IOM uint32_t LNK_LFPS_RX_U1_EXIT_GEN2; /*!< 0x00000198 LFPS U1 Exit Detect Gen2 Configuration */ 187 __IOM uint32_t LNK_LFPS_RX_U2_EXIT_GEN2; /*!< 0x0000019C LFPS U2 Exit Detect Gen2 Configuration */ 188 __IOM uint32_t LNK_LFPS_RX_U1_HANDSHAKE_GEN2; /*!< 0x000001A0 LFPS U1 Exit Handshake Gen2 Configuration */ 189 __IOM uint32_t LNK_LFPS_RX_U2_HANDSHAKE_GEN2; /*!< 0x000001A4 LFPS U2 Exit Handshake Gen 2 Configuration */ 190 __IOM uint32_t LNK_LFPS_RX_U3_HANDSHAKE_GEN2; /*!< 0x000001A8 LFPS U3 Exit Handshake Gen 2 Configuration */ 191 __IOM uint32_t LNK_LFPS_RX_LOOPBACK_EXIT_GEN2; /*!< 0x000001AC LFPS Loopback Exit Detect Gen2 Configuration */ 192 __IOM uint32_t LNK_LFPS_RX_LOOPBACK_HANDSHAKE_GEN2; /*!< 0x000001B0 LFPS Loopback Exit Handshake Gen2 Configuration */ 193 __IOM uint32_t LNK_PENDING_HP_TIMEOUT_GEN2; /*!< 0x000001B4 Header Packet LGOOD/LBAD Gen2 Timeout */ 194 __IM uint32_t RESERVED2[3]; 195 __IOM uint32_t LNK_CREDIT_HP_TIMEOUT_GEN2; /*!< 0x000001C4 Header Packet LCRD_x Gen2 Timeout */ 196 __IOM uint32_t LNK_PM_LC_X2_TIMEOUT_GEN1; /*!< 0x000001C8 Power Mode PM_LC_X2_TIMER Gen1 Timeout */ 197 __IOM uint32_t LNK_PM_LC_X1_TIMEOUT_GEN2; /*!< 0x000001CC Power Mode PM_LC_X1_TIMER Gen2 Timeout */ 198 __IOM uint32_t LNK_PM_LC_X2_TIMEOUT_GEN2; /*!< 0x000001D0 Power Mode PM_LC_X2_TIMER Gen2 Timeout */ 199 __IOM uint32_t LNK_PM_ENTRY_X2_TIMEOUT_GEN1; /*!< 0x000001D4 Power Mode PM_ENTRY_X2_TIMER Gen1 Timeout */ 200 __IOM uint32_t LNK_PM_ENTRY_X1_TIMEOUT_GEN2; /*!< 0x000001D8 Power Mode PM_ENTRY_X1_TIMER Gen2 Timeout */ 201 __IOM uint32_t LNK_PM_ENTRY_X2_TIMEOUT_GEN2; /*!< 0x000001DC Power Mode PM_ENTRY_X2_TIMER Gen2 Timeout */ 202 __IOM uint32_t LNK_PM_UX_EXIT_TIMEOUT_GEN2; /*!< 0x000001E0 Power Mode Ux_EXIT_TIMER Gen2 Timeout */ 203 __IOM uint32_t LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN1; /*!< 0x000001E4 Power Mode U1_MIN_RESIDENCY_TIMER Gen1 Timeout */ 204 __IOM uint32_t LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN2; /*!< 0x000001E8 Power Mode U1_MIN_RESIDENCY_TIMER Gen2 Timeout */ 205 __IOM uint32_t LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN1; /*!< 0x000001EC LFPS SCD Transmit Logic 0 Gen1 Configuration */ 206 __IOM uint32_t LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN1; /*!< 0x000001F0 LFPS SCD Transmit Logic 1 Gen1 Configuration */ 207 __IOM uint32_t LNK_LFPS_TX_SCD_END_REPEAT_GEN1; /*!< 0x000001F4 LFPS SCD Transmit End Gen1 Configuration */ 208 __IOM uint32_t LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN1; /*!< 0x000001F8 LFPS SCD Receive Logic 0 Gen1 Gen1 Configuration */ 209 __IOM uint32_t LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN1; /*!< 0x000001FC LFPS SCD Receive Logic 1 Gen1 Configuration */ 210 __IOM uint32_t LNK_LFPS_RX_SCD_END_REPEAT_GEN1; /*!< 0x00000200 LFPS SCD Receive End Gen1 Configuration */ 211 __IOM uint32_t LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN2; /*!< 0x00000204 LFPS SCD Transmit Logic 0 Gen2 Configuration */ 212 __IOM uint32_t LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN2; /*!< 0x00000208 LFPS SCD Transmit Logic 1 Gen2 Configuration */ 213 __IOM uint32_t LNK_LFPS_TX_SCD_END_REPEAT_GEN2; /*!< 0x0000020C LFPS SCD Transmit End Gen2 Configuration */ 214 __IOM uint32_t LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN2; /*!< 0x00000210 LFPS SCD Receive Logic 0 Gen2 Configuration */ 215 __IM uint32_t RESERVED3[3]; 216 __IOM uint32_t LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN2; /*!< 0x00000220 LFPS SCD Receive Logic 1 Gen2 Configuration */ 217 __IOM uint32_t LNK_LFPS_RX_SCD_END_REPEAT_GEN2; /*!< 0x00000224 LFPS SCD Receive End Gen2 Configuration */ 218 __IOM uint32_t LNK_LFPS_TX_LBPS_TPWM_GEN1; /*!< 0x00000228 LFPS LBPS Transmit tPWM Gen1 Configuration */ 219 __IM uint32_t RESERVED4[3]; 220 __IOM uint32_t LNK_LFPS_TX_LBPS_TLFPS0_GEN1; /*!< 0x00000238 LFPS LBPS Transmit tLFPS-0 Gen1 Configuration */ 221 __IOM uint32_t LNK_LFPS_TX_LBPS_TLFPS1_GEN1; /*!< 0x0000023C LFPS LBPS Transmit tLFPS-1 Gen1 Configuration */ 222 __IOM uint32_t LNK_LFPS_RX_LBPS_TPWM_GEN1; /*!< 0x00000240 LFPS LBPS Receive tPWM Gen1 Configuration */ 223 __IOM uint32_t LNK_LFPS_RX_LBPS_TLFPS0_GEN1; /*!< 0x00000244 LFPS LBPS Receive tLFPS-0 Gen1 Configuration */ 224 __IOM uint32_t LNK_LFPS_RX_LBPS_TLFPS1_GEN1; /*!< 0x00000248 LFPS LBPS Receive tLFPS-1 Gen1 Configuration */ 225 __IOM uint32_t LNK_LFPS_TX_LBPS_TPWM_GEN2; /*!< 0x0000024C LFPS LBPS Transmit tPWM Gen2 Configuration */ 226 __IOM uint32_t LNK_LFPS_TX_LBPS_TLFPS0_GEN2; /*!< 0x00000250 LFPS LBPS Transmit tLFPS-0 Gen2 Configuration */ 227 __IOM uint32_t LNK_LFPS_TX_LBPS_TLFPS1_GEN2; /*!< 0x00000254 LFPS LBPS Transmit tLFPS-1 Gen2 Configuration */ 228 __IOM uint32_t LNK_LFPS_RX_LBPS_TPWM_GEN2; /*!< 0x00000258 LFPS LBPS Receive tPWM Gen2 Configuration */ 229 __IOM uint32_t LNK_LFPS_RX_LBPS_TLFPS0_GEN2; /*!< 0x0000025C LFPS LBPS Receive tLFPS-0 Gen2 Configuration */ 230 __IOM uint32_t LNK_LFPS_RX_LBPS_TLFPS1_GEN2; /*!< 0x00000260 LFPS LBPS Receive tLFPS-1 Gen2 Configuration */ 231 __IOM uint32_t LNK_LFPS_SCD_PATTERN; /*!< 0x00000264 LFPS SCD Pattern Configuration */ 232 __IOM uint32_t LNK_TSEQ_COUNT_GEN1; /*!< 0x00000268 TSEQ Count Gen1 Configuration */ 233 __IOM uint32_t LNK_TSEQ_COUNT_GEN2; /*!< 0x0000026C TSEQ Count Gen2 Configuration */ 234 __IOM uint32_t LNK_SCD1_GEN2_HSK; /*!< 0x00000270 SCD1 Handshake Gen2 Configuration */ 235 __IOM uint32_t LNK_SCD1_GEN2_TO_GEN1_HSK; /*!< 0x00000274 SCD1 Handshake Gen2_to_Gen1 Configuration */ 236 __IOM uint32_t LNK_SCD1_OBSERVE; /*!< 0x00000278 Polling.LFPS SCD1 Observability */ 237 __IOM uint32_t LNK_SCD2_GEN2_HSK; /*!< 0x0000027C SCD2 Handshake Gen2 Configuration */ 238 __IOM uint32_t LNK_SCD2_GEN2_TO_GEN1_HSK; /*!< 0x00000280 SCD2 Handshake Gen2_to_Gen1 Configuration */ 239 __IOM uint32_t LNK_SCD2_OBSERVE; /*!< 0x00000284 Polling.LFPSPlus SCD2 Observability */ 240 __IOM uint32_t LNK_CAP_LBPM_HSK; /*!< 0x00000288 Polling.PortMatch LBPM Handshake Configuration */ 241 __IOM uint32_t LNK_CAP_LBPM_OBSERVE; /*!< 0x0000028C Polling.PortMatch LBPM Observability */ 242 __IOM uint32_t LNK_READY_LBPM_HSK; /*!< 0x00000290 Polling.PortConfig LBPM Handshake Configuration */ 243 __IOM uint32_t LNK_READY_LBPM_OBSERVE; /*!< 0x00000294 Polling.PortConfig LBPM Observability */ 244 __IM uint32_t LNK_RCVD_LBPM_OBSERVE; /*!< 0x00000298 Received LBPM Observability */ 245 __IOM uint32_t LNK_LTSSM_SCD_LFPS_TIMEOUT; /*!< 0x0000029C LTSSM SCD LFPS Timeout (SuperSpeedPlus Only) */ 246 __IOM uint32_t LNK_LTSSM_LBPM_LFPS_TIMEOUT; /*!< 0x000002A0 LTSSM LBPM LFPS Timeout (SuperSpeedPlus Only) */ 247 __IOM uint32_t LNK_COMPLIANCE_PATTERN_9_TO_12; /*!< 0x000002A4 Compliance Pattern CP9 to CP12 */ 248 __IOM uint32_t LNK_COMPLIANCE_PATTERN_13; /*!< 0x000002A8 Compliance Pattern CP13 */ 249 __IOM uint32_t LNK_COMPLIANCE_PATTERN_14; /*!< 0x000002AC Compliance Pattern CP14 */ 250 __IOM uint32_t LNK_COMPLIANCE_PATTERN_15; /*!< 0x000002B0 Compliance Pattern CP15 */ 251 __IOM uint32_t LNK_COMPLIANCE_PATTERN_16; /*!< 0x000002B4 Compliance Pattern CP16 */ 252 __IM uint32_t LNK_COMPLIANCE_PATTERN_OBSERVE; /*!< 0x000002B8 Compliance Pattern Observability */ 253 __IOM uint32_t LNK_SOFT_ERR_CNT_CONF; /*!< 0x000002BC Soft Error Counter Configuration */ 254 __IM uint32_t LNK_SOFT_ERR_CNT_OBSERVE; /*!< 0x000002C0 Soft Error Counter Observability */ 255 __IOM uint32_t LNK_LTSSM_STATE_CHG_INTR_CONF; /*!< 0x000002C4 LTSSM State Change Interrupt Configuration */ 256 __IOM uint32_t LNK_DEBUG_RSVD; /*!< 0x000002C8 Debugging and Reserved (Internal Use Only) */ 257 __IOM uint32_t LNK_TX_TS1_HOLDOFF_TIMEOUT; /*!< 0x000002CC Transmitting TS1 Holdoff */ 258 __IOM uint32_t LNK_MISC_CONF; /*!< 0x000002D0 Miscellaneous Configuration */ 259 __IM uint32_t LNK_MISC_OBSERVE; /*!< 0x000002D4 Miscellaneous Observability */ 260 __IM uint32_t LNK_LTSSM_SUBSTATE_OBSERVE; /*!< 0x000002D8 LTSSM Substate Observability */ 261 __IM uint32_t RESERVED5[9]; 262 __IM uint32_t LNK_RX_TYPE1_HEADER_BUFFER[21]; /*!< 0x00000300 Receive Type1 Packet Header Buffer */ 263 __IM uint32_t RESERVED6[11]; 264 __IM uint32_t LNK_RX_TYPE1_HEADER_BUFFER_STATE_0; /*!< 0x00000380 Receive Type1 Packet Header Buffer Status 0 */ 265 __IM uint32_t LNK_RX_TYPE1_HEADER_BUFFER_STATE_1; /*!< 0x00000384 Receive Type1 Packet Header Buffer Status 1 */ 266 __IM uint32_t RESERVED7[30]; 267 __IM uint32_t LNK_RX_TYPE2_HEADER_BUFFER[21]; /*!< 0x00000400 Receive Type2 Packet Header Buffer */ 268 __IM uint32_t RESERVED8[11]; 269 __IM uint32_t LNK_RX_TYPE2_HEADER_BUFFER_STATE_0; /*!< 0x00000480 Receive Type2 Packet Header Buffer Status 0 */ 270 __IM uint32_t LNK_RX_TYPE2_HEADER_BUFFER_STATE_1; /*!< 0x00000484 Receive Type2 Packet Header Buffer Status 1 */ 271 __IM uint32_t RESERVED9[30]; 272 __IM uint32_t LNK_TX_TYPE1_HEADER_BUFFER[21]; /*!< 0x00000500 Transmit Type1 Packet Header Buffer */ 273 __IM uint32_t RESERVED10[11]; 274 __IM uint32_t LNK_TX_TYPE1_HEADER_BUFFER_STATE_0; /*!< 0x00000580 Transmit Type1 Packet Header Buffer Status 0 */ 275 __IM uint32_t LNK_TX_TYPE1_HEADER_BUFFER_STATE_1; /*!< 0x00000584 Transmit Type1 Packet Header Buffer Status 1 */ 276 __IM uint32_t RESERVED11[30]; 277 __IM uint32_t LNK_TX_TYPE2_HEADER_BUFFER[21]; /*!< 0x00000600 Transmit Type2 Packet Header Buffer */ 278 __IM uint32_t RESERVED12[11]; 279 __IM uint32_t LNK_TX_TYPE2_HEADER_BUFFER_STATE_0; /*!< 0x00000680 Transmit Type2 Packet Header Buffer Status 0 */ 280 __IM uint32_t LNK_TX_TYPE2_HEADER_BUFFER_STATE_1; /*!< 0x00000684 Transmit Type2 Packet Header Buffer Status 1 */ 281 __IM uint32_t RESERVED13[606]; 282 } USB32DEV_LNK_V1_Type; /*!< Size = 4096 (0x1000) */ 283 284 /** 285 * \brief USB32 SuperSpeedPlus Device Controller Protocol Layer Registers (USB32DEV_PROT) 286 */ 287 typedef struct { 288 __IOM uint32_t PROT_CS; /*!< 0x00000000 Protocol Control and Status */ 289 __IOM uint32_t PROT_INTR; /*!< 0x00000004 Protocol Interrupts */ 290 __IOM uint32_t PROT_INTR_SET; /*!< 0x00000008 Protocol Interrupts Set */ 291 __IOM uint32_t PROT_INTR_MASK; /*!< 0x0000000C Protocol Interrupts Mask */ 292 __IM uint32_t PROT_INTR_MASKED; /*!< 0x00000010 Protocol Interrupts Masked */ 293 __IM uint32_t PROT_EP_INTR; /*!< 0x00000014 Endpoint Interrupts */ 294 __IOM uint32_t PROT_EP_INTR_SET; /*!< 0x00000018 Endpoint Interrupts set */ 295 __IOM uint32_t PROT_EP_INTR_MASK; /*!< 0x0000001C Endpoint Interrupts Mask */ 296 __IM uint32_t PROT_EP_INTR_MASKED; /*!< 0x00000020 Endpoint Interrupts Masked */ 297 __IOM uint32_t PROT_DEVICE_NOTIF_FUNC_WAKE; /*!< 0x00000024 Device Notification Remote Wake up TP */ 298 __IOM uint32_t PROT_DEVICE_NOTIF_LTM; /*!< 0x00000028 Device Notification Latency Tolerance Message TP */ 299 __IOM uint32_t PROT_DEVICE_NOTIF_BIAM; /*!< 0x0000002C Device Notification Bus Interval Adjustment TP */ 300 __IOM uint32_t PROT_LMP_PORT_CAPABILITY_TIMER; /*!< 0x00000030 Port Capabilites LMP Timeout Configuration */ 301 __IOM uint32_t PROT_LMP_PORT_CONFIGURATION_TIMER; /*!< 0x00000034 Port Configuration LMP Timeout Configuration */ 302 __IOM uint32_t PROT_PING_TIMEOUT; /*!< 0x00000038 Ping Timeout Configuration */ 303 __IM uint32_t RESERVED[2]; 304 __IM uint32_t PROT_FRAMECNT; /*!< 0x00000044 Frame Counter Register */ 305 __IM uint32_t PROT_ITP_CORRECTION; /*!< 0x00000048 Correction field of ITP. */ 306 __IM uint32_t RESERVED1[2]; 307 __IM uint32_t PROT_SETUPDAT0; /*!< 0x00000054 Received SETUP Packet Data */ 308 __IM uint32_t PROT_SETUPDAT1; /*!< 0x00000058 Received SETUP Packet Data */ 309 __IOM uint32_t PROT_SEQ_NUM; /*!< 0x0000005C Sequence Number */ 310 __IM uint32_t RESERVED2[8]; 311 __IM uint32_t PROT_LMP_RECEIVED; /*!< 0x00000080 Link Management Packet Received Value */ 312 __IOM uint32_t PROT_LMP_OVERRIDE; /*!< 0x00000084 Link Management Packet Override Values */ 313 __IM uint32_t PROT_LMP_PORT_CAPABILITIES_RX; /*!< 0x00000088 Port Capabilities LMP Received */ 314 __IOM uint32_t PROT_LMP_PORT_CAPABILITIES_TX; /*!< 0x0000008C Port Capabilities LMP Transmitted */ 315 __IM uint32_t PROT_LMP_PORT_CONFIGURATION_RX; /*!< 0x00000090 Port Configuration LMP Received */ 316 __IOM uint32_t PROT_LMP_PORT_CONFIGURATION_TX; /*!< 0x00000094 Port Configuration Response LMP */ 317 __IOM uint32_t PROT_STREAM_ERROR_DISABLE; /*!< 0x00000098 Streams Error Disable Type Registers */ 318 __IOM uint32_t PROT_STREAM_ERROR_STATUS; /*!< 0x0000009C Streams Error STATUS Registers */ 319 __IM uint32_t RESERVED3[24]; 320 __IM uint32_t PROT_LMP_PACKET_RX[3]; /*!< 0x00000100 Link Management Packet Received */ 321 __IM uint32_t RESERVED4; 322 __IOM uint32_t PROT_LMP_PACKET_TX[3]; /*!< 0x00000110 Link Management Packet to be sent */ 323 __IM uint32_t RESERVED5[9]; 324 __IOM uint32_t PROT_EPI_INTR[16]; /*!< 0x00000140 Per IN-Endpoint Interrupt */ 325 __IOM uint32_t PROT_EPI_INTR_SET[16]; /*!< 0x00000180 Per IN-Endpoint Interrupt set */ 326 __IOM uint32_t PROT_EPI_INTR_MASK[16]; /*!< 0x000001C0 Per IN-Endpoint Interrupt Mask */ 327 __IM uint32_t PROT_EPI_INTR_MASKED[16]; /*!< 0x00000200 Per IN-Endpoint Interrupt Masked */ 328 __IOM uint32_t PROT_EPI_CS1[16]; /*!< 0x00000240 SuperSpeed IN Endpoint Control and Status */ 329 __IOM uint32_t PROT_EPI_CS2[16]; /*!< 0x00000280 SuperSpeed IN Endpoint Control and Status */ 330 __IOM uint32_t PROT_EPI_UNMAPPED_STREAM[16]; /*!< 0x000002C0 Unmapped Stream Request */ 331 __IOM uint32_t PROT_EPI_MAPPED_STREAM[16]; /*!< 0x00000300 Mapped Streams Registers */ 332 __IOM uint32_t PROT_EPO_INTR[16]; /*!< 0x00000340 Per OUT-Endpoint Interrupt */ 333 __IOM uint32_t PROT_EPO_INTR_SET[16]; /*!< 0x00000380 Per OUT-Endpoint Interrupt set */ 334 __IOM uint32_t PROT_EPO_INTR_MASK[16]; /*!< 0x000003C0 Per OUT-Endpoint Interrupt Mask */ 335 __IM uint32_t PROT_EPO_INTR_MASKED[16]; /*!< 0x00000400 Per OUT-Endpoint Interrupt Masked */ 336 __IOM uint32_t PROT_EPO_CS1[16]; /*!< 0x00000440 SuperSpeed OUT Endpoint Control and Status */ 337 __IOM uint32_t PROT_EPO_CS2[16]; /*!< 0x00000480 SuperSpeed IN Endpoint Control and Status */ 338 __IOM uint32_t PROT_EPO_UNMAPPED_STREAM[16]; /*!< 0x000004C0 Unmapped Stream Request */ 339 __IOM uint32_t PROT_EPO_MAPPED_STREAM[16]; /*!< 0x00000500 Mapped Streams Registers */ 340 __IM uint32_t RESERVED6[16]; 341 __IOM uint32_t PROT_SUBLINK_DEV_NNOTIFICATION; /*!< 0x00000580 Sublink Speed Device Notification Settings */ 342 __IOM uint32_t PROT_SUBLINK_LSM; /*!< 0x00000584 Sublink Speed Device Notification Lane Speed Mantissa */ 343 __IOM uint32_t PROT_PTM_CONFIG; /*!< 0x00000588 PTM configuration register */ 344 __IOM uint32_t PROT_FW_PTM_COUNTER; /*!< 0x0000058C FW Load PTM counter register */ 345 __IOM uint32_t PROT_HW_PTM_COUNTER; /*!< 0x00000590 HW Internal PTM counter */ 346 __IM uint32_t PROT_PTM_STATUS; /*!< 0x00000594 PTM status register */ 347 __IM uint32_t PROT_PTM_T1; /*!< 0x00000598 PTM T1 value */ 348 __IM uint32_t PROT_PTM_T4; /*!< 0x0000059C PTM T4 value */ 349 __IM uint32_t PROT_LMP_LDM_RESPONSE; /*!< 0x000005A0 Protocol LMP LDM received */ 350 __IM uint32_t RESERVED7[311]; 351 __IOM uint32_t PROT_EPI_ENHANCE[16]; /*!< 0x00000A80 Enhancements for IN-Endpoint transactions */ 352 __IOM uint32_t PROT_ENHANCE; /*!< 0x00000AC0 Protocol Enhancements Configuration register */ 353 __IM uint32_t RESERVED8[335]; 354 } USB32DEV_PROT_V1_Type; /*!< Size = 4096 (0x1000) */ 355 356 /** 357 * \brief PHY TOP, PCS, Tx registers (USB32DEV_PHYSS_USB40PHY_TOP) 358 */ 359 typedef struct { 360 __IM uint32_t RESERVED; 361 __IOM uint32_t TOP_CTRL_0; /*!< 0x00000004 TOP control register */ 362 __IM uint32_t RESERVED1[2]; 363 __IOM uint32_t PCS_CTRL_0; /*!< 0x00000010 PCS control register */ 364 __IM uint32_t RESERVED2; 365 __IM uint32_t PCS_STATUS; /*!< 0x00000018 PCS status register */ 366 __IOM uint32_t PCS_SPARE; /*!< 0x0000001C PCS spare */ 367 __IM uint32_t ERR_STATUS; /*!< 0x00000020 Error status register */ 368 __IM uint32_t RESERVED3[3]; 369 __IOM uint32_t PIPE_OVERRIDE_0; /*!< 0x00000030 PIPE interface control signals override register #0 */ 370 __IM uint32_t RESERVED4; 371 __IM uint32_t PIPE_STATUS; /*!< 0x00000038 PIPE interface status read register */ 372 __IM uint32_t RESERVED5; 373 __IOM uint32_t INTR0; /*!< 0x00000040 INTR0 Cause. These are the wakeup interrupts get reflected on 374 interrupt_wakeup pin. */ 375 __IOM uint32_t INTR0_SET; /*!< 0x00000044 INTR0 Set */ 376 __IOM uint32_t INTR0_MASK; /*!< 0x00000048 INTR0 Mask */ 377 __IM uint32_t INTR0_MASKED; /*!< 0x0000004C INTR0 Masked */ 378 __IOM uint32_t INTR1; /*!< 0x00000050 INTR1 Cause. These are the wakeup interrupts get reflected on 379 interrupt_wakeup pin. */ 380 __IOM uint32_t INTR1_SET; /*!< 0x00000054 INTR1 Set */ 381 __IOM uint32_t INTR1_MASK; /*!< 0x00000058 INTR1 Mask */ 382 __IM uint32_t INTR1_MASKED; /*!< 0x0000005C INTR1 Masked */ 383 __IOM uint32_t TX_AFE_CTRL_0; /*!< 0x00000060 Tx AFE control register #0 */ 384 __IOM uint32_t TX_AFE_CTRL_1; /*!< 0x00000064 Tx AFE control register #1 */ 385 __IM uint32_t RESERVED6; 386 __IOM uint32_t TX_AFE_RXDETECT_CNT; /*!< 0x0000006C Tx AFE TxDetectRx wait counter */ 387 __IOM uint32_t TX_AFE_OVERRIDE_0; /*!< 0x00000070 Tx AFE override 0 register */ 388 __IM uint32_t RESERVED7; 389 __IM uint32_t TX_AFE_DEBUG; /*!< 0x00000078 Tx AFE debug register */ 390 __IM uint32_t TX_AFE_STATUS; /*!< 0x0000007C Tx AFE status register */ 391 __IM uint32_t RESERVED8; 392 __IOM uint32_t TX_AFE_ZTRIM; /*!< 0x00000084 Tx AFE impedance calibration register */ 393 __IM uint32_t RESERVED9[2]; 394 __IOM uint32_t TX_AFE_CFG; /*!< 0x00000090 Tx AFE configuration control register */ 395 __IOM uint32_t TX_AFE_CFG_SFT_W_0; /*!< 0x00000094 Tx AFE configuration control shift write register #0 */ 396 __IOM uint32_t TX_AFE_CFG_SFT_W_1; /*!< 0x00000098 Tx AFE configuration control shift write register #1 */ 397 __IOM uint32_t TX_AFE_CFG_SFT_W_2; /*!< 0x0000009C Tx AFE configuration control shift write register #2 */ 398 __IOM uint32_t TX_AFE_CFG_SFT_W_3; /*!< 0x000000A0 Tx AFE configuration control shift write register #3 */ 399 __IOM uint32_t TX_AFE_CFG_SFT_W_4; /*!< 0x000000A4 Tx AFE configuration control shift write register #4 */ 400 __IOM uint32_t TX_AFE_CFG_SFT_W_5; /*!< 0x000000A8 Tx AFE configuration control shift write register #5 */ 401 __IOM uint32_t TX_AFE_CFG_SFT_W_6; /*!< 0x000000AC Tx AFE configuration control shift write register #6 */ 402 __IOM uint32_t TX_AFE_CFG_SFT_W_7; /*!< 0x000000B0 Tx AFE configuration control shift write register #7 */ 403 __IM uint32_t TX_AFE_CFG_SFT_R; /*!< 0x000000B4 Tx AFE configuration control shift read register for debug */ 404 __IM uint32_t RESERVED10[2]; 405 __IOM uint32_t ADC; /*!< 0x000000C0 Analog to Digital Converter register #0 */ 406 __IM uint32_t ADC_STATUS; /*!< 0x000000C4 Analog to Digital Converter status register */ 407 __IM uint32_t RESERVED11[3]; 408 __IOM uint32_t PHYSS_LOOPBACK_CTRL_0; /*!< 0x000000D4 PHY Loopback control register #0 */ 409 __IM uint32_t PHYSS_LOOPBACK_DEBUG_0; /*!< 0x000000D8 PHY Loopback debug register #0 */ 410 __IM uint32_t PHYSS_LOOPBACK_DEBUG_1; /*!< 0x000000DC PHY Loopback debug register #1 */ 411 __IM uint32_t PHYSS_LOOPBACK_STATUS_1; /*!< 0x000000E0 PHY Loopback status register #1 */ 412 __IOM uint32_t PHYSS_LOOPBACK_USER_0; /*!< 0x000000E4 PHY Loopback user pattern register #0 */ 413 __IOM uint32_t PHYSS_LOOPBACK_USER_1; /*!< 0x000000E8 PHY Loopback user pattern register #1 */ 414 __IM uint32_t RESERVED12; 415 __IOM uint32_t PHYSS_DDFT_MUX_SEL; /*!< 0x000000F0 PHY DDFT selection */ 416 __IOM uint32_t PIPE_RX_CTRL; /*!< 0x000000F4 Configuration for PIPE RX */ 417 __IOM uint32_t LOW_POWER_CTRL; /*!< 0x000000F8 Low Power configuration */ 418 __IOM uint32_t CDR_SW_CTRL; /*!< 0x000000FC Configuration for CDR mode switching */ 419 __IM uint32_t RESERVED13[448]; 420 } USB32DEV_PHYSS_USB40PHY_TOP_V1_Type; /*!< Size = 2048 (0x800) */ 421 422 /** 423 * \brief PHY Rx registers (USB32DEV_PHYSS_USB40PHY_RX) 424 */ 425 typedef struct { 426 __IOM uint32_t RX_SDM_CFG0; /*!< 0x00000000 Sigma-Delta Modulator (SDM) Configuration */ 427 __IOM uint32_t RX_SDM_CFG1; /*!< 0x00000004 Sigma-Delta Modulator (SDM) Configuration */ 428 __IOM uint32_t RX_SDM_CFG2; /*!< 0x00000008 Sigma-Delta Modulator (SDM) Configuration */ 429 __IOM uint32_t RX_SDM_CFG3; /*!< 0x0000000C Sigma-Delta Modulator (SDM) Configuration */ 430 __IOM uint32_t RX_DFE_CFG0; /*!< 0x00000010 DFE FSM (DFE) Configuration */ 431 __IOM uint32_t RX_DFE_CFG1; /*!< 0x00000014 DFE FSM (DFE) Configuration */ 432 __IOM uint32_t RX_DFE_CFG2; /*!< 0x00000018 DFE FSM (DFE) Configuration */ 433 __IOM uint32_t RX_DFE_CFG3; /*!< 0x0000001C DFE FSM (DFE) Configuration */ 434 __IM uint32_t RX_DFE_STAT0; /*!< 0x00000020 DFE FSM (DFE) status */ 435 __IM uint32_t RX_DFE_STAT1; /*!< 0x00000024 DFE FSM (DFE) status */ 436 __IM uint32_t RX_DFE_STAT2; /*!< 0x00000028 DFE FSM (DFE) status */ 437 __IOM uint32_t RX_OSA_CFG0; /*!< 0x0000002C Offset Calibration FSM (OSA) Configuration */ 438 __IOM uint32_t RX_OSA_CFG1; /*!< 0x00000030 Offset Calibration FSM (OSA) Configuration */ 439 __IOM uint32_t RX_OSA_CFG2; /*!< 0x00000034 Offset Calibration FSM (OSA) Configuration */ 440 __IOM uint32_t RX_OSA_CFG3; /*!< 0x00000038 Offset Calibration FSM (OSA) Configuration */ 441 __IOM uint32_t RX_OSA_CFG4; /*!< 0x0000003C Offset Calibration FSM (OSA) Configuration */ 442 __IOM uint32_t RX_OSA_CFG5; /*!< 0x00000040 Offset Calibration FSM (OSA) Configuration */ 443 __IM uint32_t RX_OSA_STAT0; /*!< 0x00000044 Offset Calibration FSM (OSA) status */ 444 __IM uint32_t RX_OSA_STAT1; /*!< 0x00000048 Offset Calibration FSM (OSA) status */ 445 __IM uint32_t RX_OSA_STAT2; /*!< 0x0000004C Offset Calibration FSM (OSA) status */ 446 __IM uint32_t RX_OSA_STAT3; /*!< 0x00000050 Offset Calibration FSM (OSA) status */ 447 __IM uint32_t RX_OSA_STAT4; /*!< 0x00000054 Offset Calibration FSM (OSA) status */ 448 __IM uint32_t RX_OSA_STAT5; /*!< 0x00000058 Offset Calibration FSM (OSA) status */ 449 __IM uint32_t RX_OSA_STAT6; /*!< 0x0000005C Offset Calibration FSM (OSA) status */ 450 __IM uint32_t RX_OSA_STAT7; /*!< 0x00000060 Offset Calibration FSM (OSA) status */ 451 __IM uint32_t RX_OSA_STAT8; /*!< 0x00000064 Offset Calibration FSM (OSA) status */ 452 __IOM uint32_t RX_CTLE_CFG0; /*!< 0x00000068 CTLE controls Configuration */ 453 __IOM uint32_t RX_CTLE_CFG1; /*!< 0x0000006C CTLE controls Configuration */ 454 __IM uint32_t RX_CTLE_STAT0; /*!< 0x00000070 CTLE controls status */ 455 __IM uint32_t RX_CTLE_STAT1; /*!< 0x00000074 CTLE controls status */ 456 __IOM uint32_t RX_EM_CFG0; /*!< 0x00000078 Eye monitor FSM (EM) Configuration */ 457 __IOM uint32_t RX_EM_CFG1; /*!< 0x0000007C Eye monitor FSM (EM) Configuration */ 458 __IM uint32_t RX_EM_STAT0; /*!< 0x00000080 Eye monitor FSM (EM) status */ 459 __IM uint32_t RX_EM_STAT1; /*!< 0x00000084 Eye monitor FSM (EM) status */ 460 __IOM uint32_t RX_DFEA_CFG0; /*!< 0x00000088 DFE Analog Configuration */ 461 __IOM uint32_t RX_OSAA_CFG0; /*!< 0x0000008C Offset Calibration Analog Configuration */ 462 __IOM uint32_t RX_OSAA_CFG1; /*!< 0x00000090 Offset Calibration Analog Configuration */ 463 __IOM uint32_t RX_AFE_CFG; /*!< 0x00000094 Analog Front End (AFE) Configuration */ 464 __IOM uint32_t RX_EMA_CFG; /*!< 0x00000098 Eye Monitor Analog Configuration */ 465 __IOM uint32_t RX_REFCKSEL_CFG; /*!< 0x0000009C Reference Clock Select (REFCLKSEL) Configuration */ 466 __IOM uint32_t RX_DIVH_CFG; /*!< 0x000000A0 HS Divider (DIVH) Configuration */ 467 __IOM uint32_t RX_PFD_CFG; /*!< 0x000000A4 Phase/Frequency Detector (PFD) Configuration */ 468 __IOM uint32_t RX_CP_CFG; /*!< 0x000000A8 Charge Pump (CP) Configuration */ 469 __IOM uint32_t RX_LF_CFG; /*!< 0x000000AC Loop Filter (LF) Configuration */ 470 __IOM uint32_t RX_BIASGEN_CFG0; /*!< 0x000000B0 Bias Generator (BIASGEN) Configuration */ 471 __IOM uint32_t RX_BIASGEN_CFG1; /*!< 0x000000B4 Bias Generator (BIASGEN) Configuration */ 472 __IOM uint32_t RX_GNRL_CFG; /*!< 0x000000B8 General Controls Configuration */ 473 __IOM uint32_t RX_VREG_CFG0; /*!< 0x000000BC Regulators Configuration */ 474 __IOM uint32_t RX_VREG_CFG1; /*!< 0x000000C0 Regulators Configuration */ 475 __IM uint32_t RX_VREG_STAT; /*!< 0x000000C4 Regulators Status */ 476 __IOM uint32_t RX_SD_CFG; /*!< 0x000000C8 Signal detect/LFPS Configuration */ 477 __IM uint32_t RX_SD_STAT; /*!< 0x000000CC Signal detect/LFPS Status */ 478 __IOM uint32_t RX_LD_CFG; /*!< 0x000000D0 Lock Detect Configuration */ 479 __IM uint32_t RX_LD_STAT; /*!< 0x000000D4 Lock Detect Status */ 480 __IOM uint32_t RX_DFE_CFG4; /*!< 0x000000D8 DFE FSM (DFE) Configuration */ 481 __IOM uint32_t RX_HDWR_ENABLE; /*!< 0x000000DC Configuration for hardware enable */ 482 __IOM uint32_t RX_ATEST_CFG; /*!< 0x000000E0 Analog Test Mux (ATEST) Configuration */ 483 __IOM uint32_t RX_DTEST_CFG; /*!< 0x000000E4 Digital Test Mux (DTEST) Configuration */ 484 __IOM uint32_t SPARE_CFG; /*!< 0x000000E8 Spare Configuration */ 485 __IM uint32_t SPARE_STAT; /*!< 0x000000EC Spare Status */ 486 __IOM uint32_t SPARE_HV_CFG; /*!< 0x000000F0 Spare Configuration for HV signlas */ 487 __IM uint32_t RESERVED[3]; 488 } USB32DEV_PHYSS_USB40PHY_RX_V1_Type; /*!< Size = 256 (0x100) */ 489 490 /** 491 * \brief PHY PLL SYS registers (USB32DEV_PHYSS_USB40PHY_PLL_SYS) 492 */ 493 typedef struct { 494 __IOM uint32_t PLL_SDM_CFG; /*!< 0x00000000 Sigma-Delta Modulator (SDM) Configuration */ 495 __IOM uint32_t PLL_SSM_CFG0; /*!< 0x00000004 Spread Spectrun Modulator (SSM) Configuration */ 496 __IOM uint32_t PLL_SSM_CFG1; /*!< 0x00000008 Spread Spectrun Modulator (SSM) Configuration */ 497 __IOM uint32_t PLL_SSM_CFG2; /*!< 0x0000000C Spread Spectrun Modulator (SSM) Configuration */ 498 __IOM uint32_t PLL_AFC_CFG0; /*!< 0x00000010 Automatic Frequency Control (AFC) Configuration */ 499 __IOM uint32_t PLL_AFC_CFG1; /*!< 0x00000014 Automatic Frequency Control (AFC) Configuration */ 500 __IOM uint32_t PLL_AFC_CFG2; /*!< 0x00000018 Automatic Frequency Control (AFC) Configuration */ 501 __IM uint32_t PLL_AFC_STAT; /*!< 0x0000001C Automatic Frequency Control (AFC) Status */ 502 __IOM uint32_t PLL_AAC_CFG0; /*!< 0x00000020 Automatic Amplitude Control (AAC) Configuration */ 503 __IOM uint32_t PLL_AAC_CFG1; /*!< 0x00000024 Automatic Amplitude Control (AAC) Configuration */ 504 __IM uint32_t PLL_AAC_STAT; /*!< 0x00000028 Automatic Amplitude Control (AAC) Status */ 505 __IOM uint32_t PLL_REFCKSEL_CFG; /*!< 0x0000002C Reference Clock Select (REFCLKSEL) Configuration */ 506 __IOM uint32_t PLL_DIVR_CFG; /*!< 0x00000030 Reference Clock Divider (DIVR) Configuration */ 507 __IOM uint32_t PLL_DIVP_CFG; /*!< 0x00000034 Post Divider (DIVP) Configuration */ 508 __IOM uint32_t PLL_DIVH_CFG; /*!< 0x00000038 HS Divider (DIVH) Configuration */ 509 __IOM uint32_t PLL_PFD_CFG; /*!< 0x0000003C Phase/Frequency Detector (PFD) Configuration */ 510 __IOM uint32_t PLL_CP_CFG; /*!< 0x00000040 Charge Pump (CP) Configuration */ 511 __IOM uint32_t PLL_LF_CFG; /*!< 0x00000044 Loop Filter (LF) Configuration */ 512 __IOM uint32_t PLL_VCO_CFG; /*!< 0x00000048 Voltage-Controlled Oscillator (VCO) Configuration */ 513 __IOM uint32_t PLL_BIASGEN_CFG; /*!< 0x0000004C Bias Generator (BIASGEN) Configuration */ 514 __IOM uint32_t PLL_GNRL_CFG; /*!< 0x00000050 General Controls Configuration */ 515 __IOM uint32_t PLL_VREG_CFG1; /*!< 0x00000054 Regulators Configuration */ 516 __IOM uint32_t PLL_VREG_CFG2; /*!< 0x00000058 Regulators Configuration */ 517 __IM uint32_t PLL_VREG_STAT; /*!< 0x0000005C Regulators Status */ 518 __IOM uint32_t PLL_LD_CFG; /*!< 0x00000060 Lock Detect Configuration */ 519 __IM uint32_t PLL_LD_STAT; /*!< 0x00000064 Lock Detect Status */ 520 __IOM uint32_t PLL_ATEST; /*!< 0x00000068 Analog Test Mux (ATEST) Configuration */ 521 __IOM uint32_t PLL_DTEST; /*!< 0x0000006C Digital Test Mux (DTEST) Configuration */ 522 __IOM uint32_t SPARE_CFG; /*!< 0x00000070 Spare Configuration */ 523 __IM uint32_t SPARE_STAT; /*!< 0x00000074 Spare Status */ 524 __IM uint32_t RESERVED[34]; 525 } USB32DEV_PHYSS_USB40PHY_PLL_SYS_V1_Type; /*!< Size = 256 (0x100) */ 526 527 /** 528 * \brief PHY Registers (USB32DEV_PHYSS_USB40PHY) 529 */ 530 typedef struct { 531 USB32DEV_PHYSS_USB40PHY_TOP_V1_Type USB40PHY_TOP; /*!< 0x00000000 PHY TOP, PCS, Tx registers */ 532 USB32DEV_PHYSS_USB40PHY_RX_V1_Type USB40PHY_RX; /*!< 0x00000800 PHY Rx registers */ 533 USB32DEV_PHYSS_USB40PHY_PLL_SYS_V1_Type USB40PHY_PLL_SYS; /*!< 0x00000900 PHY PLL SYS registers */ 534 __IM uint32_t RESERVED[384]; 535 } USB32DEV_PHYSS_USB40PHY_V1_Type; /*!< Size = 4096 (0x1000) */ 536 537 /** 538 * \brief USB32 SuperSpeedPlus Physical Layer Registers (USB32DEV_PHYSS) 539 */ 540 typedef struct { 541 USB32DEV_PHYSS_USB40PHY_V1_Type USB40PHY[2]; /*!< 0x00000000 PHY Registers */ 542 } USB32DEV_PHYSS_V1_Type; /*!< Size = 8192 (0x2000) */ 543 544 /** 545 * \brief Socket Registers (USB32DEV_ADAPTER_DMA_SCK) 546 */ 547 typedef struct { 548 __IOM uint32_t SCK_DSCR; /*!< 0x00000000 Descriptor Chain Pointer */ 549 __IOM uint32_t SCK_SIZE; /*!< 0x00000004 Transfer Size Register */ 550 __IOM uint32_t SCK_COUNT; /*!< 0x00000008 Transfer Count Register */ 551 __IOM uint32_t SCK_STATUS; /*!< 0x0000000C Socket Status Register */ 552 __IOM uint32_t SCK_INTR; /*!< 0x00000010 Socket Interrupt Request Register */ 553 __IOM uint32_t SCK_INTR_MASK; /*!< 0x00000014 Socket Interrupt Mask Register */ 554 __IM uint32_t RESERVED[2]; 555 __IOM uint32_t DSCR_BUFFER; /*!< 0x00000020 Descriptor buffer base address register */ 556 __IOM uint32_t DSCR_SYNC; /*!< 0x00000024 Descriptor synchronization pointers register */ 557 __IOM uint32_t DSCR_CHAIN; /*!< 0x00000028 Descriptor Chain Pointers Register */ 558 __IOM uint32_t DSCR_SIZE; /*!< 0x0000002C Descriptor Size Register */ 559 __IM uint32_t RESERVED1[19]; 560 __OM uint32_t EVENT; /*!< 0x0000007C Event Communication Register */ 561 } USB32DEV_ADAPTER_DMA_SCK_V1_Type; /*!< Size = 128 (0x80) */ 562 563 /** 564 * \brief General DMA Registers (USB32DEV_ADAPTER_DMA_SCK_GBL) 565 */ 566 typedef struct { 567 __IM uint32_t SCK_INTR; /*!< 0x00000000 Socket Interrupt Request Register */ 568 __IM uint32_t RESERVED[59]; 569 __IOM uint32_t ADAPTER_CTRL; /*!< 0x000000F0 Adapter Control Register */ 570 __IM uint32_t ADAPTER_DEBUG; /*!< 0x000000F4 Adapter Debug Observation Register */ 571 __IOM uint32_t ADAPTER_CONF; /*!< 0x000000F8 Adapter Configuration Register */ 572 __IM uint32_t ADAPTER_STATUS; /*!< 0x000000FC Adapter Global Status Fields */ 573 } USB32DEV_ADAPTER_DMA_SCK_GBL_V1_Type; /*!< Size = 256 (0x100) */ 574 575 /** 576 * \brief USB32 DMA Adapter registers. 577 0x10000 is for Ingress and 0x20000 for egress Adapter (USB32DEV_ADAPTER_DMA) 578 */ 579 typedef struct { 580 __IM uint32_t RESERVED[8192]; 581 USB32DEV_ADAPTER_DMA_SCK_V1_Type SCK[16]; /*!< 0x00008000 Socket Registers */ 582 __IM uint32_t RESERVED1[7616]; 583 USB32DEV_ADAPTER_DMA_SCK_GBL_V1_Type SCK_GBL; /*!< 0x0000FF00 General DMA Registers */ 584 } USB32DEV_ADAPTER_DMA_V1_Type; /*!< Size = 65536 (0x10000) */ 585 586 /** 587 * \brief USB32DEV Registers (USB32DEV_USB32DEV) 588 */ 589 typedef struct { 590 USB32DEV_MAIN_V1_Type USB32DEV_MAIN; /*!< 0x00000000 USB32 Main Register */ 591 USB32DEV_EPM_V1_Type USB32DEV_EPM; /*!< 0x00001000 USB32 Controller End Point Manager Registers */ 592 USB32DEV_LNK_V1_Type USB32DEV_LNK; /*!< 0x00002000 USB32 SuperSpeedPlus Device Controller Link Layer Registers */ 593 USB32DEV_PROT_V1_Type USB32DEV_PROT; /*!< 0x00003000 USB32 SuperSpeedPlus Device Controller Protocol Layer Registers */ 594 USB32DEV_PHYSS_V1_Type USB32DEV_PHYSS; /*!< 0x00004000 USB32 SuperSpeedPlus Physical Layer Registers */ 595 __IM uint32_t RESERVED[10240]; 596 USB32DEV_ADAPTER_DMA_V1_Type USB32DEV_ADAPTER[2]; /*!< 0x00010000 USB32 DMA Adapter registers. 0x10000 is for Ingress and 0x20000 597 for egress Adapter */ 598 } USB32DEV_V1_Type; /*!< Size = 196608 (0x30000) */ 599 600 601 /* USB32DEV_MAIN.CTRL */ 602 #define USB32DEV_MAIN_CTRL_SSDEV_ENABLE_Pos 0UL 603 #define USB32DEV_MAIN_CTRL_SSDEV_ENABLE_Msk 0x1UL 604 #define USB32DEV_MAIN_CTRL_DISABLE_SRAM_Pos 2UL 605 #define USB32DEV_MAIN_CTRL_DISABLE_SRAM_Msk 0x4UL 606 #define USB32DEV_MAIN_CTRL_USB2_BUS_RESET_Pos 3UL 607 #define USB32DEV_MAIN_CTRL_USB2_BUS_RESET_Msk 0x8UL 608 #define USB32DEV_MAIN_CTRL_CLK_EN_Pos 4UL 609 #define USB32DEV_MAIN_CTRL_CLK_EN_Msk 0x10UL 610 #define USB32DEV_MAIN_CTRL_PCLK_SRC_Pos 5UL 611 #define USB32DEV_MAIN_CTRL_PCLK_SRC_Msk 0x60UL 612 #define USB32DEV_MAIN_CTRL_EN_RST_CLOCK_MUX_Pos 7UL 613 #define USB32DEV_MAIN_CTRL_EN_RST_CLOCK_MUX_Msk 0x80UL 614 #define USB32DEV_MAIN_CTRL_EN_EGRS_RQ_HALF_DATA_RATE_Pos 8UL 615 #define USB32DEV_MAIN_CTRL_EN_EGRS_RQ_HALF_DATA_RATE_Msk 0x100UL 616 #define USB32DEV_MAIN_CTRL_CONFIG_LANE_Pos 30UL 617 #define USB32DEV_MAIN_CTRL_CONFIG_LANE_Msk 0x40000000UL 618 #define USB32DEV_MAIN_CTRL_IP_ENABLED_Pos 31UL 619 #define USB32DEV_MAIN_CTRL_IP_ENABLED_Msk 0x80000000UL 620 /* USB32DEV_MAIN.INTR */ 621 #define USB32DEV_MAIN_INTR_LINK_Pos 0UL 622 #define USB32DEV_MAIN_INTR_LINK_Msk 0x1UL 623 #define USB32DEV_MAIN_INTR_PROT_Pos 1UL 624 #define USB32DEV_MAIN_INTR_PROT_Msk 0x2UL 625 #define USB32DEV_MAIN_INTR_PROT_EP_Pos 2UL 626 #define USB32DEV_MAIN_INTR_PROT_EP_Msk 0x4UL 627 #define USB32DEV_MAIN_INTR_EPM_URUN_Pos 3UL 628 #define USB32DEV_MAIN_INTR_EPM_URUN_Msk 0x8UL 629 #define USB32DEV_MAIN_INTR_P3P0_Pos 5UL 630 #define USB32DEV_MAIN_INTR_P3P0_Msk 0x20UL 631 #define USB32DEV_MAIN_INTR_P3P1_Pos 6UL 632 #define USB32DEV_MAIN_INTR_P3P1_Msk 0x40UL 633 #define USB32DEV_MAIN_INTR_P3P2_Pos 7UL 634 #define USB32DEV_MAIN_INTR_P3P2_Msk 0x80UL 635 #define USB32DEV_MAIN_INTR_PHY0_Pos 8UL 636 #define USB32DEV_MAIN_INTR_PHY0_Msk 0x100UL 637 #define USB32DEV_MAIN_INTR_PHY1_Pos 9UL 638 #define USB32DEV_MAIN_INTR_PHY1_Msk 0x200UL 639 /* USB32DEV_MAIN.INTR_SET */ 640 #define USB32DEV_MAIN_INTR_SET_LINK_Pos 0UL 641 #define USB32DEV_MAIN_INTR_SET_LINK_Msk 0x1UL 642 #define USB32DEV_MAIN_INTR_SET_PROT_Pos 1UL 643 #define USB32DEV_MAIN_INTR_SET_PROT_Msk 0x2UL 644 #define USB32DEV_MAIN_INTR_SET_PROT_EP_Pos 2UL 645 #define USB32DEV_MAIN_INTR_SET_PROT_EP_Msk 0x4UL 646 #define USB32DEV_MAIN_INTR_SET_EPM_URUN_Pos 3UL 647 #define USB32DEV_MAIN_INTR_SET_EPM_URUN_Msk 0x8UL 648 #define USB32DEV_MAIN_INTR_SET_P3P0_Pos 5UL 649 #define USB32DEV_MAIN_INTR_SET_P3P0_Msk 0x20UL 650 #define USB32DEV_MAIN_INTR_SET_P3P1_Pos 6UL 651 #define USB32DEV_MAIN_INTR_SET_P3P1_Msk 0x40UL 652 #define USB32DEV_MAIN_INTR_SET_P3P2_Pos 7UL 653 #define USB32DEV_MAIN_INTR_SET_P3P2_Msk 0x80UL 654 #define USB32DEV_MAIN_INTR_SET_PHY0_Pos 8UL 655 #define USB32DEV_MAIN_INTR_SET_PHY0_Msk 0x100UL 656 #define USB32DEV_MAIN_INTR_SET_PHY1_Pos 9UL 657 #define USB32DEV_MAIN_INTR_SET_PHY1_Msk 0x200UL 658 /* USB32DEV_MAIN.INTR_MASK */ 659 #define USB32DEV_MAIN_INTR_MASK_LINK_MASK_Pos 0UL 660 #define USB32DEV_MAIN_INTR_MASK_LINK_MASK_Msk 0x1UL 661 #define USB32DEV_MAIN_INTR_MASK_PROT_MASK_Pos 1UL 662 #define USB32DEV_MAIN_INTR_MASK_PROT_MASK_Msk 0x2UL 663 #define USB32DEV_MAIN_INTR_MASK_PROT_EP_MASK_Pos 2UL 664 #define USB32DEV_MAIN_INTR_MASK_PROT_EP_MASK_Msk 0x4UL 665 #define USB32DEV_MAIN_INTR_MASK_EPM_URUN_MASK_Pos 3UL 666 #define USB32DEV_MAIN_INTR_MASK_EPM_URUN_MASK_Msk 0x8UL 667 #define USB32DEV_MAIN_INTR_MASK_P3P0_MASK_Pos 5UL 668 #define USB32DEV_MAIN_INTR_MASK_P3P0_MASK_Msk 0x20UL 669 #define USB32DEV_MAIN_INTR_MASK_P3P1_MASK_Pos 6UL 670 #define USB32DEV_MAIN_INTR_MASK_P3P1_MASK_Msk 0x40UL 671 #define USB32DEV_MAIN_INTR_MASK_P3P2_MASK_Pos 7UL 672 #define USB32DEV_MAIN_INTR_MASK_P3P2_MASK_Msk 0x80UL 673 #define USB32DEV_MAIN_INTR_MASK_PHY0_MASK_Pos 8UL 674 #define USB32DEV_MAIN_INTR_MASK_PHY0_MASK_Msk 0x100UL 675 #define USB32DEV_MAIN_INTR_MASK_PHY1_MASK_Pos 9UL 676 #define USB32DEV_MAIN_INTR_MASK_PHY1_MASK_Msk 0x200UL 677 /* USB32DEV_MAIN.INTR_MASKED */ 678 #define USB32DEV_MAIN_INTR_MASKED_LINK_MASKED_Pos 0UL 679 #define USB32DEV_MAIN_INTR_MASKED_LINK_MASKED_Msk 0x1UL 680 #define USB32DEV_MAIN_INTR_MASKED_PROT_MASKED_Pos 1UL 681 #define USB32DEV_MAIN_INTR_MASKED_PROT_MASKED_Msk 0x2UL 682 #define USB32DEV_MAIN_INTR_MASKED_PROT_EP_MASKED_Pos 2UL 683 #define USB32DEV_MAIN_INTR_MASKED_PROT_EP_MASKED_Msk 0x4UL 684 #define USB32DEV_MAIN_INTR_MASKED_EPM_URUN_MASKED_Pos 3UL 685 #define USB32DEV_MAIN_INTR_MASKED_EPM_URUN_MASKED_Msk 0x8UL 686 #define USB32DEV_MAIN_INTR_MASKED_P3P0_MASKED_Pos 5UL 687 #define USB32DEV_MAIN_INTR_MASKED_P3P0_MASKED_Msk 0x20UL 688 #define USB32DEV_MAIN_INTR_MASKED_P3P1_MASKED_Pos 6UL 689 #define USB32DEV_MAIN_INTR_MASKED_P3P1_MASKED_Msk 0x40UL 690 #define USB32DEV_MAIN_INTR_MASKED_P3P2_MASKED_Pos 7UL 691 #define USB32DEV_MAIN_INTR_MASKED_P3P2_MASKED_Msk 0x80UL 692 #define USB32DEV_MAIN_INTR_MASKED_PHY0_MASKED_Pos 8UL 693 #define USB32DEV_MAIN_INTR_MASKED_PHY0_MASKED_Msk 0x100UL 694 #define USB32DEV_MAIN_INTR_MASKED_PHY1_MASKED_Pos 9UL 695 #define USB32DEV_MAIN_INTR_MASKED_PHY1_MASKED_Msk 0x200UL 696 /* USB32DEV_MAIN.DDFT_MUX */ 697 #define USB32DEV_MAIN_DDFT_MUX_DDFT0_SEL_Pos 0UL 698 #define USB32DEV_MAIN_DDFT_MUX_DDFT0_SEL_Msk 0xFFUL 699 #define USB32DEV_MAIN_DDFT_MUX_DDFT1_SEL_Pos 8UL 700 #define USB32DEV_MAIN_DDFT_MUX_DDFT1_SEL_Msk 0xFF00UL 701 /* USB32DEV_MAIN.GPIO_DDFT_MUX */ 702 #define USB32DEV_MAIN_GPIO_DDFT_MUX_DDFT0_SEL_Pos 0UL 703 #define USB32DEV_MAIN_GPIO_DDFT_MUX_DDFT0_SEL_Msk 0xFFUL 704 #define USB32DEV_MAIN_GPIO_DDFT_MUX_DDFT1_SEL_Pos 8UL 705 #define USB32DEV_MAIN_GPIO_DDFT_MUX_DDFT1_SEL_Msk 0xFF00UL 706 /* USB32DEV_MAIN.DEBUG_CONFIG */ 707 #define USB32DEV_MAIN_DEBUG_CONFIG_DEBUG_EN_Pos 0UL 708 #define USB32DEV_MAIN_DEBUG_CONFIG_DEBUG_EN_Msk 0x1UL 709 #define USB32DEV_MAIN_DEBUG_CONFIG_STOP_EN_Pos 1UL 710 #define USB32DEV_MAIN_DEBUG_CONFIG_STOP_EN_Msk 0x2UL 711 #define USB32DEV_MAIN_DEBUG_CONFIG_FUNC_SEL_Pos 2UL 712 #define USB32DEV_MAIN_DEBUG_CONFIG_FUNC_SEL_Msk 0x1CUL 713 #define USB32DEV_MAIN_DEBUG_CONFIG_START_EVENT_SEL_Pos 5UL 714 #define USB32DEV_MAIN_DEBUG_CONFIG_START_EVENT_SEL_Msk 0x7E0UL 715 #define USB32DEV_MAIN_DEBUG_CONFIG_END_EVENT_SEL_Pos 11UL 716 #define USB32DEV_MAIN_DEBUG_CONFIG_END_EVENT_SEL_Msk 0x1F800UL 717 #define USB32DEV_MAIN_DEBUG_CONFIG_NUM_OF_ACTIVITIES_Pos 17UL 718 #define USB32DEV_MAIN_DEBUG_CONFIG_NUM_OF_ACTIVITIES_Msk 0x1FE0000UL 719 #define USB32DEV_MAIN_DEBUG_CONFIG_SKT_NUM_Pos 25UL 720 #define USB32DEV_MAIN_DEBUG_CONFIG_SKT_NUM_Msk 0x1E000000UL 721 #define USB32DEV_MAIN_DEBUG_CONFIG_DEBUG_SKT_NUM_Pos 29UL 722 #define USB32DEV_MAIN_DEBUG_CONFIG_DEBUG_SKT_NUM_Msk 0xE0000000UL 723 /* USB32DEV_MAIN.DEBUG_MUX_SEL */ 724 #define USB32DEV_MAIN_DEBUG_MUX_SEL_BIT_31_0_SEL_Pos 0UL 725 #define USB32DEV_MAIN_DEBUG_MUX_SEL_BIT_31_0_SEL_Msk 0xFUL 726 #define USB32DEV_MAIN_DEBUG_MUX_SEL_BIT_63_32_SEL_Pos 4UL 727 #define USB32DEV_MAIN_DEBUG_MUX_SEL_BIT_63_32_SEL_Msk 0xF0UL 728 #define USB32DEV_MAIN_DEBUG_MUX_SEL_BIT_95_64_SEL_Pos 8UL 729 #define USB32DEV_MAIN_DEBUG_MUX_SEL_BIT_95_64_SEL_Msk 0xF00UL 730 #define USB32DEV_MAIN_DEBUG_MUX_SEL_BIT_127_96_SEL_Pos 12UL 731 #define USB32DEV_MAIN_DEBUG_MUX_SEL_BIT_127_96_SEL_Msk 0xF000UL 732 /* USB32DEV_MAIN.LOOPBACK */ 733 #define USB32DEV_MAIN_LOOPBACK_EP_NUM_Pos 0UL 734 #define USB32DEV_MAIN_LOOPBACK_EP_NUM_Msk 0xFUL 735 #define USB32DEV_MAIN_LOOPBACK_NUMP_Pos 4UL 736 #define USB32DEV_MAIN_LOOPBACK_NUMP_Msk 0x1F0UL 737 #define USB32DEV_MAIN_LOOPBACK_TT_FIELD_Pos 9UL 738 #define USB32DEV_MAIN_LOOPBACK_TT_FIELD_Msk 0xE00UL 739 #define USB32DEV_MAIN_LOOPBACK_SEQ_NUM_Pos 12UL 740 #define USB32DEV_MAIN_LOOPBACK_SEQ_NUM_Msk 0x1F000UL 741 #define USB32DEV_MAIN_LOOPBACK_SINGLE_XFER_Pos 29UL 742 #define USB32DEV_MAIN_LOOPBACK_SINGLE_XFER_Msk 0x20000000UL 743 #define USB32DEV_MAIN_LOOPBACK_BURN_IN_EN_Pos 30UL 744 #define USB32DEV_MAIN_LOOPBACK_BURN_IN_EN_Msk 0x40000000UL 745 #define USB32DEV_MAIN_LOOPBACK_PIPE_LOOPBACK_EN_Pos 31UL 746 #define USB32DEV_MAIN_LOOPBACK_PIPE_LOOPBACK_EN_Msk 0x80000000UL 747 /* USB32DEV_MAIN.BUG_FIX */ 748 #define USB32DEV_MAIN_BUG_FIX_EPM_T1_T2_COLLISION_EN_Pos 0UL 749 #define USB32DEV_MAIN_BUG_FIX_EPM_T1_T2_COLLISION_EN_Msk 0x1UL 750 #define USB32DEV_MAIN_BUG_FIX_EPM_READ_END_RST_EN_Pos 1UL 751 #define USB32DEV_MAIN_BUG_FIX_EPM_READ_END_RST_EN_Msk 0x2UL 752 #define USB32DEV_MAIN_BUG_FIX_PROT_RTY_COLLISION_EN_Pos 8UL 753 #define USB32DEV_MAIN_BUG_FIX_PROT_RTY_COLLISION_EN_Msk 0x100UL 754 #define USB32DEV_MAIN_BUG_FIX_PROT_B2B_EN_Pos 9UL 755 #define USB32DEV_MAIN_BUG_FIX_PROT_B2B_EN_Msk 0x200UL 756 #define USB32DEV_MAIN_BUG_FIX_PROT_ISO_BRST_0_EN_Pos 10UL 757 #define USB32DEV_MAIN_BUG_FIX_PROT_ISO_BRST_0_EN_Msk 0x400UL 758 #define USB32DEV_MAIN_BUG_FIX_PROT_RX_COLLISION_EN_Pos 11UL 759 #define USB32DEV_MAIN_BUG_FIX_PROT_RX_COLLISION_EN_Msk 0x800UL 760 #define USB32DEV_MAIN_BUG_FIX_PROT_RX_SKP_NO_WRITE_EN_Pos 12UL 761 #define USB32DEV_MAIN_BUG_FIX_PROT_RX_SKP_NO_WRITE_EN_Msk 0x1000UL 762 #define USB32DEV_MAIN_BUG_FIX_RESET_PROT_STATE_Pos 13UL 763 #define USB32DEV_MAIN_BUG_FIX_RESET_PROT_STATE_Msk 0x2000UL 764 #define USB32DEV_MAIN_BUG_FIX_RESET_SKT_HAS_EOB_FUNC_Pos 14UL 765 #define USB32DEV_MAIN_BUG_FIX_RESET_SKT_HAS_EOB_FUNC_Msk 0x4000UL 766 #define USB32DEV_MAIN_BUG_FIX_DPH_WITH_EOB_CLEARED_Pos 16UL 767 #define USB32DEV_MAIN_BUG_FIX_DPH_WITH_EOB_CLEARED_Msk 0xFFFF0000UL 768 769 770 /* USB32DEV_EPM.EEPM_CS */ 771 #define USB32DEV_EPM_EEPM_CS_A_RQ_EMPTY_DLY_Pos 0UL 772 #define USB32DEV_EPM_EEPM_CS_A_RQ_EMPTY_DLY_Msk 0x1FUL 773 #define USB32DEV_EPM_EEPM_CS_URUN_T1_EP_NUM_Pos 18UL 774 #define USB32DEV_EPM_EEPM_CS_URUN_T1_EP_NUM_Msk 0x3C0000UL 775 #define USB32DEV_EPM_EEPM_CS_URUN_T2_EP_NUM_Pos 22UL 776 #define USB32DEV_EPM_EEPM_CS_URUN_T2_EP_NUM_Msk 0x3C00000UL 777 #define USB32DEV_EPM_EEPM_CS_EG_EPNUM_Pos 28UL 778 #define USB32DEV_EPM_EEPM_CS_EG_EPNUM_Msk 0xF0000000UL 779 /* USB32DEV_EPM.IEPM_CS */ 780 #define USB32DEV_EPM_IEPM_CS_READ_PTR_Pos 0UL 781 #define USB32DEV_EPM_IEPM_CS_READ_PTR_Msk 0xFFFUL 782 #define USB32DEV_EPM_IEPM_CS_WRITE_PTR_Pos 16UL 783 #define USB32DEV_EPM_IEPM_CS_WRITE_PTR_Msk 0xFFF0000UL 784 #define USB32DEV_EPM_IEPM_CS_EPM_FLUSH_Pos 28UL 785 #define USB32DEV_EPM_IEPM_CS_EPM_FLUSH_Msk 0x10000000UL 786 #define USB32DEV_EPM_IEPM_CS_DISABLE_IEPM_CLK_GT_Pos 31UL 787 #define USB32DEV_EPM_IEPM_CS_DISABLE_IEPM_CLK_GT_Msk 0x80000000UL 788 /* USB32DEV_EPM.IEPM_MULT */ 789 #define USB32DEV_EPM_IEPM_MULT_MULT_EN_Pos 0UL 790 #define USB32DEV_EPM_IEPM_MULT_MULT_EN_Msk 0x7FFFUL 791 #define USB32DEV_EPM_IEPM_MULT_MULT_THRSHOLD_Pos 15UL 792 #define USB32DEV_EPM_IEPM_MULT_MULT_THRSHOLD_Msk 0x3FF8000UL 793 /* USB32DEV_EPM.EEPM_ENDPOINT */ 794 #define USB32DEV_EPM_EEPM_ENDPOINT_PACKET_SIZE_Pos 0UL 795 #define USB32DEV_EPM_EEPM_ENDPOINT_PACKET_SIZE_Msk 0x7FFUL 796 #define USB32DEV_EPM_EEPM_ENDPOINT_EEPM_BYTE_COUNT_Pos 11UL 797 #define USB32DEV_EPM_EEPM_ENDPOINT_EEPM_BYTE_COUNT_Msk 0x7FFF800UL 798 #define USB32DEV_EPM_EEPM_ENDPOINT_ZLP_Pos 27UL 799 #define USB32DEV_EPM_EEPM_ENDPOINT_ZLP_Msk 0x8000000UL 800 #define USB32DEV_EPM_EEPM_ENDPOINT_MSB_EEPM_BYTE_COUNT_Pos 28UL 801 #define USB32DEV_EPM_EEPM_ENDPOINT_MSB_EEPM_BYTE_COUNT_Msk 0x10000000UL 802 #define USB32DEV_EPM_EEPM_ENDPOINT_EPM_EMPTY_Pos 29UL 803 #define USB32DEV_EPM_EEPM_ENDPOINT_EPM_EMPTY_Msk 0x20000000UL 804 #define USB32DEV_EPM_EEPM_ENDPOINT_EEPM_EP_READY_Pos 30UL 805 #define USB32DEV_EPM_EEPM_ENDPOINT_EEPM_EP_READY_Msk 0x40000000UL 806 #define USB32DEV_EPM_EEPM_ENDPOINT_SOCKET_FLUSH_Pos 31UL 807 #define USB32DEV_EPM_EEPM_ENDPOINT_SOCKET_FLUSH_Msk 0x80000000UL 808 /* USB32DEV_EPM.IEPM_ENDPOINT */ 809 #define USB32DEV_EPM_IEPM_ENDPOINT_PACKET_SIZE_Pos 0UL 810 #define USB32DEV_EPM_IEPM_ENDPOINT_PACKET_SIZE_Msk 0x7FFUL 811 #define USB32DEV_EPM_IEPM_ENDPOINT_NUM_IN_PACKETS_Pos 11UL 812 #define USB32DEV_EPM_IEPM_ENDPOINT_NUM_IN_PACKETS_Msk 0x3FF800UL 813 #define USB32DEV_EPM_IEPM_ENDPOINT_EP_READY_Pos 22UL 814 #define USB32DEV_EPM_IEPM_ENDPOINT_EP_READY_Msk 0x400000UL 815 #define USB32DEV_EPM_IEPM_ENDPOINT_ODD_MAX_NUM_PKTS_Pos 24UL 816 #define USB32DEV_EPM_IEPM_ENDPOINT_ODD_MAX_NUM_PKTS_Msk 0x1F000000UL 817 #define USB32DEV_EPM_IEPM_ENDPOINT_ODD_MAX_PKT_SIZE_EN_Pos 29UL 818 #define USB32DEV_EPM_IEPM_ENDPOINT_ODD_MAX_PKT_SIZE_EN_Msk 0x20000000UL 819 #define USB32DEV_EPM_IEPM_ENDPOINT_EOT_EOP_Pos 30UL 820 #define USB32DEV_EPM_IEPM_ENDPOINT_EOT_EOP_Msk 0x40000000UL 821 #define USB32DEV_EPM_IEPM_ENDPOINT_SOCKET_FLUSH_Pos 31UL 822 #define USB32DEV_EPM_IEPM_ENDPOINT_SOCKET_FLUSH_Msk 0x80000000UL 823 /* USB32DEV_EPM.IEPM_FIFO */ 824 #define USB32DEV_EPM_IEPM_FIFO_BYTES_Pos 0UL 825 #define USB32DEV_EPM_IEPM_FIFO_BYTES_Msk 0x7FFUL 826 #define USB32DEV_EPM_IEPM_FIFO_EOT_Pos 11UL 827 #define USB32DEV_EPM_IEPM_FIFO_EOT_Msk 0x800UL 828 #define USB32DEV_EPM_IEPM_FIFO_IN_EPNUM_Pos 12UL 829 #define USB32DEV_EPM_IEPM_FIFO_IN_EPNUM_Msk 0xF000UL 830 #define USB32DEV_EPM_IEPM_FIFO_EP_VALID_Pos 16UL 831 #define USB32DEV_EPM_IEPM_FIFO_EP_VALID_Msk 0x10000UL 832 /* USB32DEV_EPM.EEPM_VALID */ 833 #define USB32DEV_EPM_EEPM_VALID_SKT_NUM_Pos 0UL 834 #define USB32DEV_EPM_EEPM_VALID_SKT_NUM_Msk 0xFUL 835 #define USB32DEV_EPM_EEPM_VALID_VALID_PACKETS_Pos 16UL 836 #define USB32DEV_EPM_EEPM_VALID_VALID_PACKETS_Msk 0xFFFF0000UL 837 /* USB32DEV_EPM.EEPM_RETRY_OFFSET */ 838 #define USB32DEV_EPM_EEPM_RETRY_OFFSET_START_OFFSET_Pos 0UL 839 #define USB32DEV_EPM_EEPM_RETRY_OFFSET_START_OFFSET_Msk 0x3FFFUL 840 /* USB32DEV_EPM.EEPM_INJECT_CRC32_ERROR */ 841 #define USB32DEV_EPM_EEPM_INJECT_CRC32_ERROR_EN_CRC32_ERROR_ON_SW_BUF_Pos 0UL 842 #define USB32DEV_EPM_EEPM_INJECT_CRC32_ERROR_EN_CRC32_ERROR_ON_SW_BUF_Msk 0x1UL 843 #define USB32DEV_EPM_EEPM_INJECT_CRC32_ERROR_EN_CRC32_ERROR_ON_RETRY_Pos 1UL 844 #define USB32DEV_EPM_EEPM_INJECT_CRC32_ERROR_EN_CRC32_ERROR_ON_RETRY_Msk 0x2UL 845 #define USB32DEV_EPM_EEPM_INJECT_CRC32_ERROR_SW_BUF_PKT_NUM_Pos 2UL 846 #define USB32DEV_EPM_EEPM_INJECT_CRC32_ERROR_SW_BUF_PKT_NUM_Msk 0x3CUL 847 #define USB32DEV_EPM_EEPM_INJECT_CRC32_ERROR_RETRY_BUF_PKT_NUM_Pos 6UL 848 #define USB32DEV_EPM_EEPM_INJECT_CRC32_ERROR_RETRY_BUF_PKT_NUM_Msk 0x3C0UL 849 850 851 /* USB32DEV_LNK.LNK_CONF */ 852 #define USB32DEV_LNK_CONF_TX_ARBITRATION_Pos 0UL 853 #define USB32DEV_LNK_CONF_TX_ARBITRATION_Msk 0x3UL 854 #define USB32DEV_LNK_CONF_LCW_IGNORE_RSVD_Pos 6UL 855 #define USB32DEV_LNK_CONF_LCW_IGNORE_RSVD_Msk 0x40UL 856 #define USB32DEV_LNK_CONF_DEBUG_FEATURE_ENABLE_Pos 7UL 857 #define USB32DEV_LNK_CONF_DEBUG_FEATURE_ENABLE_Msk 0x80UL 858 #define USB32DEV_LNK_CONF_FORCE_POWER_PRESENT_Pos 8UL 859 #define USB32DEV_LNK_CONF_FORCE_POWER_PRESENT_Msk 0x100UL 860 #define USB32DEV_LNK_CONF_LDN_DETECTION_Pos 9UL 861 #define USB32DEV_LNK_CONF_LDN_DETECTION_Msk 0x200UL 862 #define USB32DEV_LNK_CONF_CREDIT_ADV_HOLDOFF_Pos 10UL 863 #define USB32DEV_LNK_CONF_CREDIT_ADV_HOLDOFF_Msk 0x400UL 864 #define USB32DEV_LNK_CONF_GEN1X2_SKP_RULE_SEL_Pos 11UL 865 #define USB32DEV_LNK_CONF_GEN1X2_SKP_RULE_SEL_Msk 0x800UL 866 #define USB32DEV_LNK_CONF_EPM_FIRST_DELAY_Pos 12UL 867 #define USB32DEV_LNK_CONF_EPM_FIRST_DELAY_Msk 0xF000UL 868 #define USB32DEV_LNK_CONF_GEN1X1_INVALID_OS_DET_EN_Pos 16UL 869 #define USB32DEV_LNK_CONF_GEN1X1_INVALID_OS_DET_EN_Msk 0x10000UL 870 #define USB32DEV_LNK_CONF_GEN1X1_CP_TXDETECT_RXLPBK_EN_Pos 17UL 871 #define USB32DEV_LNK_CONF_GEN1X1_CP_TXDETECT_RXLPBK_EN_Msk 0x20000UL 872 #define USB32DEV_LNK_CONF_GEN1X1_LOOPBACK_MASTER_SKP_EN_Pos 18UL 873 #define USB32DEV_LNK_CONF_GEN1X1_LOOPBACK_MASTER_SKP_EN_Msk 0x40000UL 874 #define USB32DEV_LNK_CONF_DC_BAL_ALL_OS_Pos 19UL 875 #define USB32DEV_LNK_CONF_DC_BAL_ALL_OS_Msk 0x80000UL 876 #define USB32DEV_LNK_CONF_DC_BAL_NON_OS_RESET_Pos 20UL 877 #define USB32DEV_LNK_CONF_DC_BAL_NON_OS_RESET_Msk 0x100000UL 878 #define USB32DEV_LNK_CONF_SKP_IN_RXEQ_OFF_Pos 21UL 879 #define USB32DEV_LNK_CONF_SKP_IN_RXEQ_OFF_Msk 0x200000UL 880 #define USB32DEV_LNK_CONF_DC_BAL_EN_Pos 24UL 881 #define USB32DEV_LNK_CONF_DC_BAL_EN_Msk 0x1000000UL 882 #define USB32DEV_LNK_CONF_RX_DPP_ERR_GO_RECOVERY_EN_Pos 25UL 883 #define USB32DEV_LNK_CONF_RX_DPP_ERR_GO_RECOVERY_EN_Msk 0x2000000UL 884 #define USB32DEV_LNK_CONF_SKEW_VAL_Pos 26UL 885 #define USB32DEV_LNK_CONF_SKEW_VAL_Msk 0x7C000000UL 886 #define USB32DEV_LNK_CONF_DESKEW_CTRL_SEL_Pos 31UL 887 #define USB32DEV_LNK_CONF_DESKEW_CTRL_SEL_Msk 0x80000000UL 888 /* USB32DEV_LNK.LNK_INTR */ 889 #define USB32DEV_LNK_INTR_LTSSM_STATE_CHG_Pos 0UL 890 #define USB32DEV_LNK_INTR_LTSSM_STATE_CHG_Msk 0x1UL 891 #define USB32DEV_LNK_INTR_LGOOD_Pos 1UL 892 #define USB32DEV_LNK_INTR_LGOOD_Msk 0x2UL 893 #define USB32DEV_LNK_INTR_LRTY_Pos 2UL 894 #define USB32DEV_LNK_INTR_LRTY_Msk 0x4UL 895 #define USB32DEV_LNK_INTR_LBAD_Pos 3UL 896 #define USB32DEV_LNK_INTR_LBAD_Msk 0x8UL 897 #define USB32DEV_LNK_INTR_LCRD_Pos 4UL 898 #define USB32DEV_LNK_INTR_LCRD_Msk 0x10UL 899 #define USB32DEV_LNK_INTR_LGO_U1_Pos 5UL 900 #define USB32DEV_LNK_INTR_LGO_U1_Msk 0x20UL 901 #define USB32DEV_LNK_INTR_LGO_U2_Pos 6UL 902 #define USB32DEV_LNK_INTR_LGO_U2_Msk 0x40UL 903 #define USB32DEV_LNK_INTR_LGO_U3_Pos 7UL 904 #define USB32DEV_LNK_INTR_LGO_U3_Msk 0x80UL 905 #define USB32DEV_LNK_INTR_LAU_Pos 8UL 906 #define USB32DEV_LNK_INTR_LAU_Msk 0x100UL 907 #define USB32DEV_LNK_INTR_LXU_Pos 9UL 908 #define USB32DEV_LNK_INTR_LXU_Msk 0x200UL 909 #define USB32DEV_LNK_INTR_LPMA_Pos 10UL 910 #define USB32DEV_LNK_INTR_LPMA_Msk 0x400UL 911 #define USB32DEV_LNK_INTR_BAD_LCW_Pos 11UL 912 #define USB32DEV_LNK_INTR_BAD_LCW_Msk 0x800UL 913 #define USB32DEV_LNK_INTR_LINK_ERROR_Pos 12UL 914 #define USB32DEV_LNK_INTR_LINK_ERROR_Msk 0x1000UL 915 #define USB32DEV_LNK_INTR_PHY_ERROR_Pos 13UL 916 #define USB32DEV_LNK_INTR_PHY_ERROR_Msk 0x2000UL 917 #define USB32DEV_LNK_INTR_U2_INACTIVITY_TIMEOUT_Pos 14UL 918 #define USB32DEV_LNK_INTR_U2_INACTIVITY_TIMEOUT_Msk 0x4000UL 919 #define USB32DEV_LNK_INTR_LTSSM_CONNECT_Pos 15UL 920 #define USB32DEV_LNK_INTR_LTSSM_CONNECT_Msk 0x8000UL 921 #define USB32DEV_LNK_INTR_LTSSM_DISCONNECT_Pos 16UL 922 #define USB32DEV_LNK_INTR_LTSSM_DISCONNECT_Msk 0x10000UL 923 #define USB32DEV_LNK_INTR_LTSSM_RESET_Pos 17UL 924 #define USB32DEV_LNK_INTR_LTSSM_RESET_Msk 0x20000UL 925 #define USB32DEV_LNK_INTR_DATA_RATE_CHANGE_Pos 18UL 926 #define USB32DEV_LNK_INTR_DATA_RATE_CHANGE_Msk 0x40000UL 927 #define USB32DEV_LNK_INTR_LTSSM_U3_ENTRY_Pos 19UL 928 #define USB32DEV_LNK_INTR_LTSSM_U3_ENTRY_Msk 0x80000UL 929 #define USB32DEV_LNK_INTR_RX_PING_LFPS_Pos 20UL 930 #define USB32DEV_LNK_INTR_RX_PING_LFPS_Msk 0x100000UL 931 /* USB32DEV_LNK.LNK_INTR_SET */ 932 #define USB32DEV_LNK_INTR_SET_LTSSM_STATE_CHG_Pos 0UL 933 #define USB32DEV_LNK_INTR_SET_LTSSM_STATE_CHG_Msk 0x1UL 934 #define USB32DEV_LNK_INTR_SET_LGOOD_Pos 1UL 935 #define USB32DEV_LNK_INTR_SET_LGOOD_Msk 0x2UL 936 #define USB32DEV_LNK_INTR_SET_LRTY_Pos 2UL 937 #define USB32DEV_LNK_INTR_SET_LRTY_Msk 0x4UL 938 #define USB32DEV_LNK_INTR_SET_LBAD_Pos 3UL 939 #define USB32DEV_LNK_INTR_SET_LBAD_Msk 0x8UL 940 #define USB32DEV_LNK_INTR_SET_LCRD_Pos 4UL 941 #define USB32DEV_LNK_INTR_SET_LCRD_Msk 0x10UL 942 #define USB32DEV_LNK_INTR_SET_LGO_U1_Pos 5UL 943 #define USB32DEV_LNK_INTR_SET_LGO_U1_Msk 0x20UL 944 #define USB32DEV_LNK_INTR_SET_LGO_U2_Pos 6UL 945 #define USB32DEV_LNK_INTR_SET_LGO_U2_Msk 0x40UL 946 #define USB32DEV_LNK_INTR_SET_LGO_U3_Pos 7UL 947 #define USB32DEV_LNK_INTR_SET_LGO_U3_Msk 0x80UL 948 #define USB32DEV_LNK_INTR_SET_LAU_Pos 8UL 949 #define USB32DEV_LNK_INTR_SET_LAU_Msk 0x100UL 950 #define USB32DEV_LNK_INTR_SET_LXU_Pos 9UL 951 #define USB32DEV_LNK_INTR_SET_LXU_Msk 0x200UL 952 #define USB32DEV_LNK_INTR_SET_LPMA_Pos 10UL 953 #define USB32DEV_LNK_INTR_SET_LPMA_Msk 0x400UL 954 #define USB32DEV_LNK_INTR_SET_BAD_LCW_Pos 11UL 955 #define USB32DEV_LNK_INTR_SET_BAD_LCW_Msk 0x800UL 956 #define USB32DEV_LNK_INTR_SET_LINK_ERROR_Pos 12UL 957 #define USB32DEV_LNK_INTR_SET_LINK_ERROR_Msk 0x1000UL 958 #define USB32DEV_LNK_INTR_SET_PHY_ERROR_Pos 13UL 959 #define USB32DEV_LNK_INTR_SET_PHY_ERROR_Msk 0x2000UL 960 #define USB32DEV_LNK_INTR_SET_U2_INACTIVITY_TIMEOUT_Pos 14UL 961 #define USB32DEV_LNK_INTR_SET_U2_INACTIVITY_TIMEOUT_Msk 0x4000UL 962 #define USB32DEV_LNK_INTR_SET_LTSSM_CONNECT_Pos 15UL 963 #define USB32DEV_LNK_INTR_SET_LTSSM_CONNECT_Msk 0x8000UL 964 #define USB32DEV_LNK_INTR_SET_LTSSM_DISCONNECT_Pos 16UL 965 #define USB32DEV_LNK_INTR_SET_LTSSM_DISCONNECT_Msk 0x10000UL 966 #define USB32DEV_LNK_INTR_SET_LTSSM_RESET_Pos 17UL 967 #define USB32DEV_LNK_INTR_SET_LTSSM_RESET_Msk 0x20000UL 968 #define USB32DEV_LNK_INTR_SET_DATA_RATE_CHANGE_Pos 18UL 969 #define USB32DEV_LNK_INTR_SET_DATA_RATE_CHANGE_Msk 0x40000UL 970 #define USB32DEV_LNK_INTR_SET_LTSSM_U3_ENTRY_Pos 19UL 971 #define USB32DEV_LNK_INTR_SET_LTSSM_U3_ENTRY_Msk 0x80000UL 972 #define USB32DEV_LNK_INTR_SET_RX_PING_LFPS_Pos 20UL 973 #define USB32DEV_LNK_INTR_SET_RX_PING_LFPS_Msk 0x100000UL 974 /* USB32DEV_LNK.LNK_INTR_MASK */ 975 #define USB32DEV_LNK_INTR_MASK_LTSSM_STATE_CHG_MASK_Pos 0UL 976 #define USB32DEV_LNK_INTR_MASK_LTSSM_STATE_CHG_MASK_Msk 0x1UL 977 #define USB32DEV_LNK_INTR_MASK_LGOOD_MASK_Pos 1UL 978 #define USB32DEV_LNK_INTR_MASK_LGOOD_MASK_Msk 0x2UL 979 #define USB32DEV_LNK_INTR_MASK_LRTY_MASK_Pos 2UL 980 #define USB32DEV_LNK_INTR_MASK_LRTY_MASK_Msk 0x4UL 981 #define USB32DEV_LNK_INTR_MASK_LBAD_MASK_Pos 3UL 982 #define USB32DEV_LNK_INTR_MASK_LBAD_MASK_Msk 0x8UL 983 #define USB32DEV_LNK_INTR_MASK_LCRD_MASK_Pos 4UL 984 #define USB32DEV_LNK_INTR_MASK_LCRD_MASK_Msk 0x10UL 985 #define USB32DEV_LNK_INTR_MASK_LGO_U1_MASK_Pos 5UL 986 #define USB32DEV_LNK_INTR_MASK_LGO_U1_MASK_Msk 0x20UL 987 #define USB32DEV_LNK_INTR_MASK_LGO_U2_MASK_Pos 6UL 988 #define USB32DEV_LNK_INTR_MASK_LGO_U2_MASK_Msk 0x40UL 989 #define USB32DEV_LNK_INTR_MASK_LGO_U3_MASK_Pos 7UL 990 #define USB32DEV_LNK_INTR_MASK_LGO_U3_MASK_Msk 0x80UL 991 #define USB32DEV_LNK_INTR_MASK_LAU_MASK_Pos 8UL 992 #define USB32DEV_LNK_INTR_MASK_LAU_MASK_Msk 0x100UL 993 #define USB32DEV_LNK_INTR_MASK_LXU_MASK_Pos 9UL 994 #define USB32DEV_LNK_INTR_MASK_LXU_MASK_Msk 0x200UL 995 #define USB32DEV_LNK_INTR_MASK_LPMA_MASK_Pos 10UL 996 #define USB32DEV_LNK_INTR_MASK_LPMA_MASK_Msk 0x400UL 997 #define USB32DEV_LNK_INTR_MASK_BAD_LCW_MASK_Pos 11UL 998 #define USB32DEV_LNK_INTR_MASK_BAD_LCW_MASK_Msk 0x800UL 999 #define USB32DEV_LNK_INTR_MASK_LINK_ERROR_MASK_Pos 12UL 1000 #define USB32DEV_LNK_INTR_MASK_LINK_ERROR_MASK_Msk 0x1000UL 1001 #define USB32DEV_LNK_INTR_MASK_PHY_ERROR_MASK_Pos 13UL 1002 #define USB32DEV_LNK_INTR_MASK_PHY_ERROR_MASK_Msk 0x2000UL 1003 #define USB32DEV_LNK_INTR_MASK_U2_INACTIVITY_TIMEOUT_MASK_Pos 14UL 1004 #define USB32DEV_LNK_INTR_MASK_U2_INACTIVITY_TIMEOUT_MASK_Msk 0x4000UL 1005 #define USB32DEV_LNK_INTR_MASK_LTSSM_CONNECT_MASK_Pos 15UL 1006 #define USB32DEV_LNK_INTR_MASK_LTSSM_CONNECT_MASK_Msk 0x8000UL 1007 #define USB32DEV_LNK_INTR_MASK_LTSSM_DISCONNECT_MASK_Pos 16UL 1008 #define USB32DEV_LNK_INTR_MASK_LTSSM_DISCONNECT_MASK_Msk 0x10000UL 1009 #define USB32DEV_LNK_INTR_MASK_LTSSM_RESET_MASK_Pos 17UL 1010 #define USB32DEV_LNK_INTR_MASK_LTSSM_RESET_MASK_Msk 0x20000UL 1011 #define USB32DEV_LNK_INTR_MASK_DATA_RATE_CHANGE_MASK_Pos 18UL 1012 #define USB32DEV_LNK_INTR_MASK_DATA_RATE_CHANGE_MASK_Msk 0x40000UL 1013 #define USB32DEV_LNK_INTR_MASK_LTSSM_U3_ENTRY_MASK_Pos 19UL 1014 #define USB32DEV_LNK_INTR_MASK_LTSSM_U3_ENTRY_MASK_Msk 0x80000UL 1015 #define USB32DEV_LNK_INTR_MASK_RX_PING_LFPS_Pos 20UL 1016 #define USB32DEV_LNK_INTR_MASK_RX_PING_LFPS_Msk 0x100000UL 1017 /* USB32DEV_LNK.LNK_INTR_MASKED */ 1018 #define USB32DEV_LNK_INTR_MASKED_LTSSM_STATE_CHG_MASKED_Pos 0UL 1019 #define USB32DEV_LNK_INTR_MASKED_LTSSM_STATE_CHG_MASKED_Msk 0x1UL 1020 #define USB32DEV_LNK_INTR_MASKED_LGOOD_MASKED_Pos 1UL 1021 #define USB32DEV_LNK_INTR_MASKED_LGOOD_MASKED_Msk 0x2UL 1022 #define USB32DEV_LNK_INTR_MASKED_LRTY_MASKED_Pos 2UL 1023 #define USB32DEV_LNK_INTR_MASKED_LRTY_MASKED_Msk 0x4UL 1024 #define USB32DEV_LNK_INTR_MASKED_LBAD_MASKED_Pos 3UL 1025 #define USB32DEV_LNK_INTR_MASKED_LBAD_MASKED_Msk 0x8UL 1026 #define USB32DEV_LNK_INTR_MASKED_LCRD_MASKED_Pos 4UL 1027 #define USB32DEV_LNK_INTR_MASKED_LCRD_MASKED_Msk 0x10UL 1028 #define USB32DEV_LNK_INTR_MASKED_LGO_U1_MASKED_Pos 5UL 1029 #define USB32DEV_LNK_INTR_MASKED_LGO_U1_MASKED_Msk 0x20UL 1030 #define USB32DEV_LNK_INTR_MASKED_LGO_U2_MASKED_Pos 6UL 1031 #define USB32DEV_LNK_INTR_MASKED_LGO_U2_MASKED_Msk 0x40UL 1032 #define USB32DEV_LNK_INTR_MASKED_LGO_U3_MASKED_Pos 7UL 1033 #define USB32DEV_LNK_INTR_MASKED_LGO_U3_MASKED_Msk 0x80UL 1034 #define USB32DEV_LNK_INTR_MASKED_LAU_MASKED_Pos 8UL 1035 #define USB32DEV_LNK_INTR_MASKED_LAU_MASKED_Msk 0x100UL 1036 #define USB32DEV_LNK_INTR_MASKED_LXU_MASKED_Pos 9UL 1037 #define USB32DEV_LNK_INTR_MASKED_LXU_MASKED_Msk 0x200UL 1038 #define USB32DEV_LNK_INTR_MASKED_LPMA_MASKED_Pos 10UL 1039 #define USB32DEV_LNK_INTR_MASKED_LPMA_MASKED_Msk 0x400UL 1040 #define USB32DEV_LNK_INTR_MASKED_BAD_LCW_MASKED_Pos 11UL 1041 #define USB32DEV_LNK_INTR_MASKED_BAD_LCW_MASKED_Msk 0x800UL 1042 #define USB32DEV_LNK_INTR_MASKED_LINK_ERROR_MASKED_Pos 12UL 1043 #define USB32DEV_LNK_INTR_MASKED_LINK_ERROR_MASKED_Msk 0x1000UL 1044 #define USB32DEV_LNK_INTR_MASKED_PHY_ERROR_MASKED_Pos 13UL 1045 #define USB32DEV_LNK_INTR_MASKED_PHY_ERROR_MASKED_Msk 0x2000UL 1046 #define USB32DEV_LNK_INTR_MASKED_U2_INACTIVITY_TIMEOUT_MASKED_Pos 14UL 1047 #define USB32DEV_LNK_INTR_MASKED_U2_INACTIVITY_TIMEOUT_MASKED_Msk 0x4000UL 1048 #define USB32DEV_LNK_INTR_MASKED_LTSSM_CONNECT_MASKED_Pos 15UL 1049 #define USB32DEV_LNK_INTR_MASKED_LTSSM_CONNECT_MASKED_Msk 0x8000UL 1050 #define USB32DEV_LNK_INTR_MASKED_LTSSM_DISCONNECT_MASKED_Pos 16UL 1051 #define USB32DEV_LNK_INTR_MASKED_LTSSM_DISCONNECT_MASKED_Msk 0x10000UL 1052 #define USB32DEV_LNK_INTR_MASKED_LTSSM_RESET_MASKED_Pos 17UL 1053 #define USB32DEV_LNK_INTR_MASKED_LTSSM_RESET_MASKED_Msk 0x20000UL 1054 #define USB32DEV_LNK_INTR_MASKED_DATA_RATE_CHANGE_MASKED_Pos 18UL 1055 #define USB32DEV_LNK_INTR_MASKED_DATA_RATE_CHANGE_MASKED_Msk 0x40000UL 1056 #define USB32DEV_LNK_INTR_MASKED_LTSSM_U3_ENTRY_MASKED_Pos 19UL 1057 #define USB32DEV_LNK_INTR_MASKED_LTSSM_U3_ENTRY_MASKED_Msk 0x80000UL 1058 #define USB32DEV_LNK_INTR_MASKED_RX_PING_LFPS_Pos 20UL 1059 #define USB32DEV_LNK_INTR_MASKED_RX_PING_LFPS_Msk 0x100000UL 1060 /* USB32DEV_LNK.LNK_ERROR_CONF */ 1061 #define USB32DEV_LNK_ERROR_CONF_HP_TIMEOUT_EN_Pos 0UL 1062 #define USB32DEV_LNK_ERROR_CONF_HP_TIMEOUT_EN_Msk 0x1UL 1063 #define USB32DEV_LNK_ERROR_CONF_RX_SEQ_NUM_ERR_EN_Pos 1UL 1064 #define USB32DEV_LNK_ERROR_CONF_RX_SEQ_NUM_ERR_EN_Msk 0x2UL 1065 #define USB32DEV_LNK_ERROR_CONF_RX_HP_FAIL_EN_Pos 2UL 1066 #define USB32DEV_LNK_ERROR_CONF_RX_HP_FAIL_EN_Msk 0x4UL 1067 #define USB32DEV_LNK_ERROR_CONF_MISSING_LGOOD_EN_Pos 3UL 1068 #define USB32DEV_LNK_ERROR_CONF_MISSING_LGOOD_EN_Msk 0x8UL 1069 #define USB32DEV_LNK_ERROR_CONF_MISSING_LCRD_EN_Pos 4UL 1070 #define USB32DEV_LNK_ERROR_CONF_MISSING_LCRD_EN_Msk 0x10UL 1071 #define USB32DEV_LNK_ERROR_CONF_CREDIT_HP_TIMEOUT_EN_Pos 5UL 1072 #define USB32DEV_LNK_ERROR_CONF_CREDIT_HP_TIMEOUT_EN_Msk 0x20UL 1073 #define USB32DEV_LNK_ERROR_CONF_PM_LC_TIMEOUT_EN_Pos 6UL 1074 #define USB32DEV_LNK_ERROR_CONF_PM_LC_TIMEOUT_EN_Msk 0x40UL 1075 #define USB32DEV_LNK_ERROR_CONF_TX_SEQ_NUM_ERR_EN_Pos 7UL 1076 #define USB32DEV_LNK_ERROR_CONF_TX_SEQ_NUM_ERR_EN_Msk 0x80UL 1077 #define USB32DEV_LNK_ERROR_CONF_HDR_ADV_TIMEOUT_EN_Pos 8UL 1078 #define USB32DEV_LNK_ERROR_CONF_HDR_ADV_TIMEOUT_EN_Msk 0x100UL 1079 #define USB32DEV_LNK_ERROR_CONF_HDR_ADV_HP_EN_Pos 9UL 1080 #define USB32DEV_LNK_ERROR_CONF_HDR_ADV_HP_EN_Msk 0x200UL 1081 #define USB32DEV_LNK_ERROR_CONF_HDR_ADV_LCRD_EN_Pos 10UL 1082 #define USB32DEV_LNK_ERROR_CONF_HDR_ADV_LCRD_EN_Msk 0x400UL 1083 #define USB32DEV_LNK_ERROR_CONF_HDR_ADV_LGO_EN_Pos 11UL 1084 #define USB32DEV_LNK_ERROR_CONF_HDR_ADV_LGO_EN_Msk 0x800UL 1085 #define USB32DEV_LNK_ERROR_CONF_CREDIT_ADV_TIMEOUT_EN_Pos 12UL 1086 #define USB32DEV_LNK_ERROR_CONF_CREDIT_ADV_TIMEOUT_EN_Msk 0x1000UL 1087 #define USB32DEV_LNK_ERROR_CONF_CREDIT_ADV_HP_EN_Pos 13UL 1088 #define USB32DEV_LNK_ERROR_CONF_CREDIT_ADV_HP_EN_Msk 0x2000UL 1089 #define USB32DEV_LNK_ERROR_CONF_CREDIT_ADV_LGO_EN_Pos 14UL 1090 #define USB32DEV_LNK_ERROR_CONF_CREDIT_ADV_LGO_EN_Msk 0x4000UL 1091 /* USB32DEV_LNK.LNK_ERROR_STATUS */ 1092 #define USB32DEV_LNK_ERROR_STATUS_HP_TIMEOUT_EV_Pos 0UL 1093 #define USB32DEV_LNK_ERROR_STATUS_HP_TIMEOUT_EV_Msk 0x1UL 1094 #define USB32DEV_LNK_ERROR_STATUS_RX_SEQ_NUM_ERR_EV_Pos 1UL 1095 #define USB32DEV_LNK_ERROR_STATUS_RX_SEQ_NUM_ERR_EV_Msk 0x2UL 1096 #define USB32DEV_LNK_ERROR_STATUS_RX_HP_FAIL_EV_Pos 2UL 1097 #define USB32DEV_LNK_ERROR_STATUS_RX_HP_FAIL_EV_Msk 0x4UL 1098 #define USB32DEV_LNK_ERROR_STATUS_MISSING_LGOOD_EV_Pos 3UL 1099 #define USB32DEV_LNK_ERROR_STATUS_MISSING_LGOOD_EV_Msk 0x8UL 1100 #define USB32DEV_LNK_ERROR_STATUS_MISSING_LCRD_EV_Pos 4UL 1101 #define USB32DEV_LNK_ERROR_STATUS_MISSING_LCRD_EV_Msk 0x10UL 1102 #define USB32DEV_LNK_ERROR_STATUS_CREDIT_HP_TIMEOUT_EV_Pos 5UL 1103 #define USB32DEV_LNK_ERROR_STATUS_CREDIT_HP_TIMEOUT_EV_Msk 0x20UL 1104 #define USB32DEV_LNK_ERROR_STATUS_PM_LC_TIMEOUT_EV_Pos 6UL 1105 #define USB32DEV_LNK_ERROR_STATUS_PM_LC_TIMEOUT_EV_Msk 0x40UL 1106 #define USB32DEV_LNK_ERROR_STATUS_TX_SEQ_NUM_ERR_EV_Pos 7UL 1107 #define USB32DEV_LNK_ERROR_STATUS_TX_SEQ_NUM_ERR_EV_Msk 0x80UL 1108 #define USB32DEV_LNK_ERROR_STATUS_HDR_ADV_TIMEOUT_EV_Pos 8UL 1109 #define USB32DEV_LNK_ERROR_STATUS_HDR_ADV_TIMEOUT_EV_Msk 0x100UL 1110 #define USB32DEV_LNK_ERROR_STATUS_HDR_ADV_HP_EV_Pos 9UL 1111 #define USB32DEV_LNK_ERROR_STATUS_HDR_ADV_HP_EV_Msk 0x200UL 1112 #define USB32DEV_LNK_ERROR_STATUS_HDR_ADV_LCRD_EV_Pos 10UL 1113 #define USB32DEV_LNK_ERROR_STATUS_HDR_ADV_LCRD_EV_Msk 0x400UL 1114 #define USB32DEV_LNK_ERROR_STATUS_HDR_ADV_LGO_EV_Pos 11UL 1115 #define USB32DEV_LNK_ERROR_STATUS_HDR_ADV_LGO_EV_Msk 0x800UL 1116 #define USB32DEV_LNK_ERROR_STATUS_CREDIT_ADV_TIMEOUT_EV_Pos 12UL 1117 #define USB32DEV_LNK_ERROR_STATUS_CREDIT_ADV_TIMEOUT_EV_Msk 0x1000UL 1118 #define USB32DEV_LNK_ERROR_STATUS_CREDIT_ADV_HP_EV_Pos 13UL 1119 #define USB32DEV_LNK_ERROR_STATUS_CREDIT_ADV_HP_EV_Msk 0x2000UL 1120 #define USB32DEV_LNK_ERROR_STATUS_CREDIT_ADV_LGO_EV_Pos 14UL 1121 #define USB32DEV_LNK_ERROR_STATUS_CREDIT_ADV_LGO_EV_Msk 0x4000UL 1122 /* USB32DEV_LNK.LNK_ERROR_COUNT */ 1123 #define USB32DEV_LNK_ERROR_COUNT_LINK_ERROR_COUNT_Pos 0UL 1124 #define USB32DEV_LNK_ERROR_COUNT_LINK_ERROR_COUNT_Msk 0xFFFFUL 1125 #define USB32DEV_LNK_ERROR_COUNT_PHY_ERROR_COUNT_Pos 16UL 1126 #define USB32DEV_LNK_ERROR_COUNT_PHY_ERROR_COUNT_Msk 0xFFFF0000UL 1127 /* USB32DEV_LNK.LNK_ERROR_COUNT_THRESHOLD */ 1128 #define USB32DEV_LNK_ERROR_COUNT_THRESHOLD_LINK_ERROR_THRESHOLD_Pos 0UL 1129 #define USB32DEV_LNK_ERROR_COUNT_THRESHOLD_LINK_ERROR_THRESHOLD_Msk 0xFFFFUL 1130 #define USB32DEV_LNK_ERROR_COUNT_THRESHOLD_PHY_ERROR_THRESHOLD_Pos 16UL 1131 #define USB32DEV_LNK_ERROR_COUNT_THRESHOLD_PHY_ERROR_THRESHOLD_Msk 0xFFFF0000UL 1132 /* USB32DEV_LNK.LNK_PHY_CONF */ 1133 #define USB32DEV_LNK_PHY_CONF_PHY_MODE_Pos 0UL 1134 #define USB32DEV_LNK_PHY_CONF_PHY_MODE_Msk 0x3UL 1135 #define USB32DEV_LNK_PHY_CONF_ELASTICIY_BUFFER_MODE_Pos 2UL 1136 #define USB32DEV_LNK_PHY_CONF_ELASTICIY_BUFFER_MODE_Msk 0x4UL 1137 #define USB32DEV_LNK_PHY_CONF_TXDETECTRX_LB_OVR_Pos 3UL 1138 #define USB32DEV_LNK_PHY_CONF_TXDETECTRX_LB_OVR_Msk 0x8UL 1139 #define USB32DEV_LNK_PHY_CONF_TXDETECTRX_LB_OVR_VAL_Pos 4UL 1140 #define USB32DEV_LNK_PHY_CONF_TXDETECTRX_LB_OVR_VAL_Msk 0x10UL 1141 #define USB32DEV_LNK_PHY_CONF_TXELECIDLE_OVR_Pos 5UL 1142 #define USB32DEV_LNK_PHY_CONF_TXELECIDLE_OVR_Msk 0x20UL 1143 #define USB32DEV_LNK_PHY_CONF_TXELECIDLE_OVR_VAL_Pos 6UL 1144 #define USB32DEV_LNK_PHY_CONF_TXELECIDLE_OVR_VAL_Msk 0x40UL 1145 #define USB32DEV_LNK_PHY_CONF_TXCOMPLIANCE_OVR_Pos 7UL 1146 #define USB32DEV_LNK_PHY_CONF_TXCOMPLIANCE_OVR_Msk 0x80UL 1147 #define USB32DEV_LNK_PHY_CONF_TXCOMPLIANCE_OVR_VAL_Pos 8UL 1148 #define USB32DEV_LNK_PHY_CONF_TXCOMPLIANCE_OVR_VAL_Msk 0x100UL 1149 #define USB32DEV_LNK_PHY_CONF_TXONESZEROS_OVR_Pos 9UL 1150 #define USB32DEV_LNK_PHY_CONF_TXONESZEROS_OVR_Msk 0x200UL 1151 #define USB32DEV_LNK_PHY_CONF_TXONESZEROS_OVR_VAL_Pos 10UL 1152 #define USB32DEV_LNK_PHY_CONF_TXONESZEROS_OVR_VAL_Msk 0x400UL 1153 #define USB32DEV_LNK_PHY_CONF_RXPOLARITY_OVR_Pos 11UL 1154 #define USB32DEV_LNK_PHY_CONF_RXPOLARITY_OVR_Msk 0x800UL 1155 #define USB32DEV_LNK_PHY_CONF_RXPOLARITY_OVR_VAL_Pos 12UL 1156 #define USB32DEV_LNK_PHY_CONF_RXPOLARITY_OVR_VAL_Msk 0x1000UL 1157 #define USB32DEV_LNK_PHY_CONF_RXEQ_TRAINING_OVR_Pos 13UL 1158 #define USB32DEV_LNK_PHY_CONF_RXEQ_TRAINING_OVR_Msk 0x2000UL 1159 #define USB32DEV_LNK_PHY_CONF_RXEQ_TRAINING_OVR_VAL_Pos 14UL 1160 #define USB32DEV_LNK_PHY_CONF_RXEQ_TRAINING_OVR_VAL_Msk 0x4000UL 1161 #define USB32DEV_LNK_PHY_CONF_PHY_RESET_N_OVR_Pos 15UL 1162 #define USB32DEV_LNK_PHY_CONF_PHY_RESET_N_OVR_Msk 0x8000UL 1163 #define USB32DEV_LNK_PHY_CONF_PHY_RESET_N_OVR_VAL_Pos 16UL 1164 #define USB32DEV_LNK_PHY_CONF_PHY_RESET_N_OVR_VAL_Msk 0x10000UL 1165 #define USB32DEV_LNK_PHY_CONF_PHY_POWERDOWN_OVR_Pos 17UL 1166 #define USB32DEV_LNK_PHY_CONF_PHY_POWERDOWN_OVR_Msk 0x20000UL 1167 #define USB32DEV_LNK_PHY_CONF_PHY_POWERDOWN_OVR_VAL_Pos 18UL 1168 #define USB32DEV_LNK_PHY_CONF_PHY_POWERDOWN_OVR_VAL_Msk 0xC0000UL 1169 #define USB32DEV_LNK_PHY_CONF_PHY_RATE_OVR_Pos 20UL 1170 #define USB32DEV_LNK_PHY_CONF_PHY_RATE_OVR_Msk 0x100000UL 1171 #define USB32DEV_LNK_PHY_CONF_PHY_RATE_OVR_VAL_Pos 21UL 1172 #define USB32DEV_LNK_PHY_CONF_PHY_RATE_OVR_VAL_Msk 0x200000UL 1173 #define USB32DEV_LNK_PHY_CONF_PHY_TX_DEEMPH_OVR_Pos 22UL 1174 #define USB32DEV_LNK_PHY_CONF_PHY_TX_DEEMPH_OVR_Msk 0x400000UL 1175 #define USB32DEV_LNK_PHY_CONF_PHY_TX_DEEMPH_OVR_VAL_Pos 23UL 1176 #define USB32DEV_LNK_PHY_CONF_PHY_TX_DEEMPH_OVR_VAL_Msk 0x1800000UL 1177 #define USB32DEV_LNK_PHY_CONF_PHY_TX_MARGIN_Pos 25UL 1178 #define USB32DEV_LNK_PHY_CONF_PHY_TX_MARGIN_Msk 0xE000000UL 1179 #define USB32DEV_LNK_PHY_CONF_TXSWING_Pos 28UL 1180 #define USB32DEV_LNK_PHY_CONF_TXSWING_Msk 0x10000000UL 1181 #define USB32DEV_LNK_PHY_CONF_RX_TERMINATION_OVR_Pos 29UL 1182 #define USB32DEV_LNK_PHY_CONF_RX_TERMINATION_OVR_Msk 0x20000000UL 1183 #define USB32DEV_LNK_PHY_CONF_RX_TERMINATION_OVR_VAL_Pos 30UL 1184 #define USB32DEV_LNK_PHY_CONF_RX_TERMINATION_OVR_VAL_Msk 0x40000000UL 1185 #define USB32DEV_LNK_PHY_CONF_RX_TERMINATION_ENABLE_Pos 31UL 1186 #define USB32DEV_LNK_PHY_CONF_RX_TERMINATION_ENABLE_Msk 0x80000000UL 1187 /* USB32DEV_LNK.LNK_PHY_STATUS */ 1188 #define USB32DEV_LNK_PHY_STATUS_RXVALID_Pos 0UL 1189 #define USB32DEV_LNK_PHY_STATUS_RXVALID_Msk 0x1UL 1190 #define USB32DEV_LNK_PHY_STATUS_PHY_STATUS_Pos 1UL 1191 #define USB32DEV_LNK_PHY_STATUS_PHY_STATUS_Msk 0x2UL 1192 #define USB32DEV_LNK_PHY_STATUS_RX_ELEC_IDLE_Pos 2UL 1193 #define USB32DEV_LNK_PHY_STATUS_RX_ELEC_IDLE_Msk 0x4UL 1194 #define USB32DEV_LNK_PHY_STATUS_RXSTATUS_Pos 3UL 1195 #define USB32DEV_LNK_PHY_STATUS_RXSTATUS_Msk 0x38UL 1196 #define USB32DEV_LNK_PHY_STATUS_POWER_PRESENT_Pos 6UL 1197 #define USB32DEV_LNK_PHY_STATUS_POWER_PRESENT_Msk 0x40UL 1198 #define USB32DEV_LNK_PHY_STATUS_DATA_BUS_WIDTH_Pos 7UL 1199 #define USB32DEV_LNK_PHY_STATUS_DATA_BUS_WIDTH_Msk 0x180UL 1200 #define USB32DEV_LNK_PHY_STATUS_RXCONNECT_Pos 9UL 1201 #define USB32DEV_LNK_PHY_STATUS_RXCONNECT_Msk 0x200UL 1202 /* USB32DEV_LNK.LNK_PHY_ERROR_CONF */ 1203 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_ERROR_DECODE_EN_Pos 0UL 1204 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_ERROR_DECODE_EN_Msk 0x1UL 1205 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_ERROR_EB_OVR_EN_Pos 1UL 1206 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_ERROR_EB_OVR_EN_Msk 0x2UL 1207 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_ERROR_EB_UND_EN_Pos 2UL 1208 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_ERROR_EB_UND_EN_Msk 0x4UL 1209 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_ERROR_DISPARITY_EN_Pos 3UL 1210 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_ERROR_DISPARITY_EN_Msk 0x8UL 1211 #define USB32DEV_LNK_PHY_ERROR_CONF_RX_ERROR_CRC5_EN_Pos 4UL 1212 #define USB32DEV_LNK_PHY_ERROR_CONF_RX_ERROR_CRC5_EN_Msk 0x10UL 1213 #define USB32DEV_LNK_PHY_ERROR_CONF_RX_ERROR_CRC16_EN_Pos 5UL 1214 #define USB32DEV_LNK_PHY_ERROR_CONF_RX_ERROR_CRC16_EN_Msk 0x20UL 1215 #define USB32DEV_LNK_PHY_ERROR_CONF_RX_ERROR_CRC32_EN_Pos 6UL 1216 #define USB32DEV_LNK_PHY_ERROR_CONF_RX_ERROR_CRC32_EN_Msk 0x40UL 1217 #define USB32DEV_LNK_PHY_ERROR_CONF_TRAINING_ERROR_EN_Pos 7UL 1218 #define USB32DEV_LNK_PHY_ERROR_CONF_TRAINING_ERROR_EN_Msk 0x80UL 1219 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_LOCK_EN_Pos 8UL 1220 #define USB32DEV_LNK_PHY_ERROR_CONF_PHY_LOCK_EN_Msk 0x100UL 1221 /* USB32DEV_LNK.LNK_PHY_ERROR_STATUS */ 1222 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_ERROR_DECODE_EV_Pos 0UL 1223 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_ERROR_DECODE_EV_Msk 0x1UL 1224 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_ERROR_EB_OVR_EV_Pos 1UL 1225 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_ERROR_EB_OVR_EV_Msk 0x2UL 1226 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_ERROR_EB_UND_EV_Pos 2UL 1227 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_ERROR_EB_UND_EV_Msk 0x4UL 1228 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_ERROR_DISPARITY_EV_Pos 3UL 1229 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_ERROR_DISPARITY_EV_Msk 0x8UL 1230 #define USB32DEV_LNK_PHY_ERROR_STATUS_RX_ERROR_CRC5_EV_Pos 4UL 1231 #define USB32DEV_LNK_PHY_ERROR_STATUS_RX_ERROR_CRC5_EV_Msk 0x10UL 1232 #define USB32DEV_LNK_PHY_ERROR_STATUS_RX_ERROR_CRC16_EV_Pos 5UL 1233 #define USB32DEV_LNK_PHY_ERROR_STATUS_RX_ERROR_CRC16_EV_Msk 0x20UL 1234 #define USB32DEV_LNK_PHY_ERROR_STATUS_RX_ERROR_CRC32_EV_Pos 6UL 1235 #define USB32DEV_LNK_PHY_ERROR_STATUS_RX_ERROR_CRC32_EV_Msk 0x40UL 1236 #define USB32DEV_LNK_PHY_ERROR_STATUS_TRAINING_ERROR_EV_Pos 7UL 1237 #define USB32DEV_LNK_PHY_ERROR_STATUS_TRAINING_ERROR_EV_Msk 0x80UL 1238 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_LOCK_EV_Pos 8UL 1239 #define USB32DEV_LNK_PHY_ERROR_STATUS_PHY_LOCK_EV_Msk 0x100UL 1240 /* USB32DEV_LNK.LNK_PHY_TRAINING_HOLDOFF */ 1241 #define USB32DEV_LNK_PHY_TRAINING_HOLDOFF_GEN1_HOLDOFF_Pos 0UL 1242 #define USB32DEV_LNK_PHY_TRAINING_HOLDOFF_GEN1_HOLDOFF_Msk 0xFFFFUL 1243 #define USB32DEV_LNK_PHY_TRAINING_HOLDOFF_GEN2_HOLDOFF_Pos 16UL 1244 #define USB32DEV_LNK_PHY_TRAINING_HOLDOFF_GEN2_HOLDOFF_Msk 0xFFFF0000UL 1245 /* USB32DEV_LNK.LNK_COMMAND_WORD */ 1246 #define USB32DEV_LNK_COMMAND_WORD_COMMAND_Pos 0UL 1247 #define USB32DEV_LNK_COMMAND_WORD_COMMAND_Msk 0x7FFUL 1248 /* USB32DEV_LNK.LNK_DEVICE_POWER_CONTROL */ 1249 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_U1_Pos 0UL 1250 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_U1_Msk 0x1UL 1251 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_U2_Pos 1UL 1252 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_U2_Msk 0x2UL 1253 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_U3_Pos 2UL 1254 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_U3_Msk 0x4UL 1255 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_RX_U1_Pos 4UL 1256 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_RX_U1_Msk 0x10UL 1257 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_RX_U2_Pos 5UL 1258 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_RX_U2_Msk 0x20UL 1259 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_RX_U3_Pos 6UL 1260 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_RX_U3_Msk 0x40UL 1261 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_LAU_Pos 7UL 1262 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_LAU_Msk 0x80UL 1263 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_LXU_Pos 8UL 1264 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_TX_LXU_Msk 0x100UL 1265 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_EXIT_LP_Pos 9UL 1266 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_EXIT_LP_Msk 0x200UL 1267 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_U3_EXIT_ON_HOLD_Pos 16UL 1268 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_U3_EXIT_ON_HOLD_Msk 0x10000UL 1269 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_U3_EXIT_ON_HOLD_EN_Pos 17UL 1270 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_U3_EXIT_ON_HOLD_EN_Msk 0x20000UL 1271 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_AUTO_U1_Pos 26UL 1272 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_AUTO_U1_Msk 0x4000000UL 1273 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_AUTO_U2_Pos 27UL 1274 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_AUTO_U2_Msk 0x8000000UL 1275 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_NO_U1_Pos 28UL 1276 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_NO_U1_Msk 0x10000000UL 1277 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_NO_U2_Pos 29UL 1278 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_NO_U2_Msk 0x20000000UL 1279 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_YES_U1_Pos 30UL 1280 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_YES_U1_Msk 0x40000000UL 1281 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_YES_U2_Pos 31UL 1282 #define USB32DEV_LNK_DEVICE_POWER_CONTROL_YES_U2_Msk 0x80000000UL 1283 /* USB32DEV_LNK.LNK_LTSSM_STATE */ 1284 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_STATE_Pos 0UL 1285 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_STATE_Msk 0x3FUL 1286 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_OVERRIDE_VALUE_Pos 6UL 1287 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_OVERRIDE_VALUE_Msk 0xFC0UL 1288 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_OVERRIDE_EN_Pos 12UL 1289 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_OVERRIDE_EN_Msk 0x1000UL 1290 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_OVERRIDE_GO_Pos 13UL 1291 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_OVERRIDE_GO_Msk 0x2000UL 1292 #define USB32DEV_LNK_LTSSM_STATE_LOOPBACK_MASTER_Pos 14UL 1293 #define USB32DEV_LNK_LTSSM_STATE_LOOPBACK_MASTER_Msk 0x4000UL 1294 #define USB32DEV_LNK_LTSSM_STATE_DISABLE_SCRAMBLING_Pos 15UL 1295 #define USB32DEV_LNK_LTSSM_STATE_DISABLE_SCRAMBLING_Msk 0x8000UL 1296 #define USB32DEV_LNK_LTSSM_STATE_LOOPBACK_ERROR_Pos 16UL 1297 #define USB32DEV_LNK_LTSSM_STATE_LOOPBACK_ERROR_Msk 0x10000UL 1298 #define USB32DEV_LNK_LTSSM_STATE_LOOPBACK_GOOD_Pos 17UL 1299 #define USB32DEV_LNK_LTSSM_STATE_LOOPBACK_GOOD_Msk 0x20000UL 1300 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_FREEZE_Pos 31UL 1301 #define USB32DEV_LNK_LTSSM_STATE_LTSSM_FREEZE_Msk 0x80000000UL 1302 /* USB32DEV_LNK.LNK_LOOPBACK_INIT */ 1303 #define USB32DEV_LNK_LOOPBACK_INIT_INIT_Pos 0UL 1304 #define USB32DEV_LNK_LOOPBACK_INIT_INIT_Msk 0xFFFFFFFFUL 1305 /* USB32DEV_LNK.LNK_LOOPBACK_GENERATOR */ 1306 #define USB32DEV_LNK_LOOPBACK_GENERATOR_GENERATOR_Pos 0UL 1307 #define USB32DEV_LNK_LOOPBACK_GENERATOR_GENERATOR_Msk 0xFFFFFFFFUL 1308 /* USB32DEV_LNK.LNK_LTSSM_OBSERVE */ 1309 #define USB32DEV_LNK_LTSSM_OBSERVE_RX_DETECT_MISS_CNT_Pos 0UL 1310 #define USB32DEV_LNK_LTSSM_OBSERVE_RX_DETECT_MISS_CNT_Msk 0xFUL 1311 #define USB32DEV_LNK_LTSSM_OBSERVE_RX_DETECT_MISS_LIMIT_Pos 4UL 1312 #define USB32DEV_LNK_LTSSM_OBSERVE_RX_DETECT_MISS_LIMIT_Msk 0xF0UL 1313 #define USB32DEV_LNK_LTSSM_OBSERVE_RECOVERY_CNT_Pos 8UL 1314 #define USB32DEV_LNK_LTSSM_OBSERVE_RECOVERY_CNT_Msk 0xF00UL 1315 #define USB32DEV_LNK_LTSSM_OBSERVE_RECOVERY_LIMIT_Pos 12UL 1316 #define USB32DEV_LNK_LTSSM_OBSERVE_RECOVERY_LIMIT_Msk 0xF000UL 1317 #define USB32DEV_LNK_LTSSM_OBSERVE_TS1_RCVD_CNT_Pos 16UL 1318 #define USB32DEV_LNK_LTSSM_OBSERVE_TS1_RCVD_CNT_Msk 0xF0000UL 1319 #define USB32DEV_LNK_LTSSM_OBSERVE_TS2_RCVD_CNT_Pos 20UL 1320 #define USB32DEV_LNK_LTSSM_OBSERVE_TS2_RCVD_CNT_Msk 0xF00000UL 1321 #define USB32DEV_LNK_LTSSM_OBSERVE_IDLE_RCVD_CNT_Pos 24UL 1322 #define USB32DEV_LNK_LTSSM_OBSERVE_IDLE_RCVD_CNT_Msk 0xF000000UL 1323 #define USB32DEV_LNK_LTSSM_OBSERVE_POLLING_LFPS_COMPLETED_Pos 28UL 1324 #define USB32DEV_LNK_LTSSM_OBSERVE_POLLING_LFPS_COMPLETED_Msk 0x10000000UL 1325 #define USB32DEV_LNK_LTSSM_OBSERVE_RX_DISABLE_SCRAMBLING_Pos 29UL 1326 #define USB32DEV_LNK_LTSSM_OBSERVE_RX_DISABLE_SCRAMBLING_Msk 0x20000000UL 1327 #define USB32DEV_LNK_LTSSM_OBSERVE_DATA_RATE_CONFIG_Pos 30UL 1328 #define USB32DEV_LNK_LTSSM_OBSERVE_DATA_RATE_CONFIG_Msk 0xC0000000UL 1329 /* USB32DEV_LNK.LNK_LFPS_OBSERVE */ 1330 #define USB32DEV_LNK_LFPS_OBSERVE_POLLING_DET_Pos 0UL 1331 #define USB32DEV_LNK_LFPS_OBSERVE_POLLING_DET_Msk 0x1UL 1332 #define USB32DEV_LNK_LFPS_OBSERVE_PING_DET_Pos 1UL 1333 #define USB32DEV_LNK_LFPS_OBSERVE_PING_DET_Msk 0x2UL 1334 #define USB32DEV_LNK_LFPS_OBSERVE_RESET_DET_Pos 2UL 1335 #define USB32DEV_LNK_LFPS_OBSERVE_RESET_DET_Msk 0x4UL 1336 #define USB32DEV_LNK_LFPS_OBSERVE_U1_EXIT_DET_Pos 3UL 1337 #define USB32DEV_LNK_LFPS_OBSERVE_U1_EXIT_DET_Msk 0x8UL 1338 #define USB32DEV_LNK_LFPS_OBSERVE_U2_EXIT_DET_Pos 4UL 1339 #define USB32DEV_LNK_LFPS_OBSERVE_U2_EXIT_DET_Msk 0x10UL 1340 #define USB32DEV_LNK_LFPS_OBSERVE_U3_EXIT_DET_Pos 5UL 1341 #define USB32DEV_LNK_LFPS_OBSERVE_U3_EXIT_DET_Msk 0x20UL 1342 #define USB32DEV_LNK_LFPS_OBSERVE_LOOPBACK_DET_Pos 6UL 1343 #define USB32DEV_LNK_LFPS_OBSERVE_LOOPBACK_DET_Msk 0x40UL 1344 #define USB32DEV_LNK_LFPS_OBSERVE_SCD1_DET_Pos 7UL 1345 #define USB32DEV_LNK_LFPS_OBSERVE_SCD1_DET_Msk 0x80UL 1346 #define USB32DEV_LNK_LFPS_OBSERVE_SCD2_DET_Pos 8UL 1347 #define USB32DEV_LNK_LFPS_OBSERVE_SCD2_DET_Msk 0x100UL 1348 #define USB32DEV_LNK_LFPS_OBSERVE_PHY_CAP_LBPM_10G_DET_Pos 9UL 1349 #define USB32DEV_LNK_LFPS_OBSERVE_PHY_CAP_LBPM_10G_DET_Msk 0x200UL 1350 #define USB32DEV_LNK_LFPS_OBSERVE_PHY_CAP_LBPM_5G_DET_Pos 10UL 1351 #define USB32DEV_LNK_LFPS_OBSERVE_PHY_CAP_LBPM_5G_DET_Msk 0x400UL 1352 #define USB32DEV_LNK_LFPS_OBSERVE_PHY_READY_LBPM_DET_Pos 11UL 1353 #define USB32DEV_LNK_LFPS_OBSERVE_PHY_READY_LBPM_DET_Msk 0x800UL 1354 #define USB32DEV_LNK_LFPS_OBSERVE_POLLING_LFPS_RCVD_Pos 16UL 1355 #define USB32DEV_LNK_LFPS_OBSERVE_POLLING_LFPS_RCVD_Msk 0x1F0000UL 1356 #define USB32DEV_LNK_LFPS_OBSERVE_POLLING_LFPS_SENT_Pos 21UL 1357 #define USB32DEV_LNK_LFPS_OBSERVE_POLLING_LFPS_SENT_Msk 0x3E00000UL 1358 /* USB32DEV_LNK.LNK_LFPS_TX_POLLING_BURST */ 1359 #define USB32DEV_LNK_LFPS_TX_POLLING_BURST_BURST16_Pos 0UL 1360 #define USB32DEV_LNK_LFPS_TX_POLLING_BURST_BURST16_Msk 0xFFFFUL 1361 /* USB32DEV_LNK.LNK_LFPS_TX_POLLING_REPEAT */ 1362 #define USB32DEV_LNK_LFPS_TX_POLLING_REPEAT_REPEAT16_Pos 0UL 1363 #define USB32DEV_LNK_LFPS_TX_POLLING_REPEAT_REPEAT16_Msk 0xFFFFUL 1364 /* USB32DEV_LNK.LNK_LFPS_TX_PING_BURST */ 1365 #define USB32DEV_LNK_LFPS_TX_PING_BURST_BURST16_Pos 0UL 1366 #define USB32DEV_LNK_LFPS_TX_PING_BURST_BURST16_Msk 0xFFFFUL 1367 /* USB32DEV_LNK.LNK_LFPS_TX_PING_REPEAT */ 1368 #define USB32DEV_LNK_LFPS_TX_PING_REPEAT_REPEAT32_Pos 0UL 1369 #define USB32DEV_LNK_LFPS_TX_PING_REPEAT_REPEAT32_Msk 0xFFFFFFFFUL 1370 /* USB32DEV_LNK.LNK_LFPS_TX_U1_EXIT */ 1371 #define USB32DEV_LNK_LFPS_TX_U1_EXIT_BURST24_Pos 0UL 1372 #define USB32DEV_LNK_LFPS_TX_U1_EXIT_BURST24_Msk 0xFFFFFFUL 1373 /* USB32DEV_LNK.LNK_LFPS_TX_U2_EXIT */ 1374 #define USB32DEV_LNK_LFPS_TX_U2_EXIT_BURST24_Pos 0UL 1375 #define USB32DEV_LNK_LFPS_TX_U2_EXIT_BURST24_Msk 0xFFFFFFUL 1376 /* USB32DEV_LNK.LNK_LFPS_TX_U3_EXIT */ 1377 #define USB32DEV_LNK_LFPS_TX_U3_EXIT_BURST24_Pos 0UL 1378 #define USB32DEV_LNK_LFPS_TX_U3_EXIT_BURST24_Msk 0xFFFFFFUL 1379 /* USB32DEV_LNK.LNK_LFPS_RX_POLLING_BURST */ 1380 #define USB32DEV_LNK_LFPS_RX_POLLING_BURST_BURST_MIN_Pos 0UL 1381 #define USB32DEV_LNK_LFPS_RX_POLLING_BURST_BURST_MIN_Msk 0xFFFFUL 1382 #define USB32DEV_LNK_LFPS_RX_POLLING_BURST_BURST_MAX_Pos 16UL 1383 #define USB32DEV_LNK_LFPS_RX_POLLING_BURST_BURST_MAX_Msk 0xFFFF0000UL 1384 /* USB32DEV_LNK.LNK_LFPS_RX_POLLING_REPEAT */ 1385 #define USB32DEV_LNK_LFPS_RX_POLLING_REPEAT_REPEAT_MIN_Pos 0UL 1386 #define USB32DEV_LNK_LFPS_RX_POLLING_REPEAT_REPEAT_MIN_Msk 0xFFFFUL 1387 #define USB32DEV_LNK_LFPS_RX_POLLING_REPEAT_REPEAT_MAX_Pos 16UL 1388 #define USB32DEV_LNK_LFPS_RX_POLLING_REPEAT_REPEAT_MAX_Msk 0xFFFF0000UL 1389 /* USB32DEV_LNK.LNK_LFPS_RX_PING */ 1390 #define USB32DEV_LNK_LFPS_RX_PING_BURST_MIN_Pos 0UL 1391 #define USB32DEV_LNK_LFPS_RX_PING_BURST_MIN_Msk 0xFFFFUL 1392 #define USB32DEV_LNK_LFPS_RX_PING_BURST_MAX_Pos 16UL 1393 #define USB32DEV_LNK_LFPS_RX_PING_BURST_MAX_Msk 0xFFFF0000UL 1394 /* USB32DEV_LNK.LNK_LFPS_RX_RESET */ 1395 #define USB32DEV_LNK_LFPS_RX_RESET_BURST24_Pos 0UL 1396 #define USB32DEV_LNK_LFPS_RX_RESET_BURST24_Msk 0xFFFFFFUL 1397 /* USB32DEV_LNK.LNK_LFPS_RX_U1_EXIT */ 1398 #define USB32DEV_LNK_LFPS_RX_U1_EXIT_BURST24_Pos 0UL 1399 #define USB32DEV_LNK_LFPS_RX_U1_EXIT_BURST24_Msk 0xFFFFFFUL 1400 /* USB32DEV_LNK.LNK_LFPS_RX_U2_EXIT */ 1401 #define USB32DEV_LNK_LFPS_RX_U2_EXIT_BURST24_Pos 0UL 1402 #define USB32DEV_LNK_LFPS_RX_U2_EXIT_BURST24_Msk 0xFFFFFFUL 1403 /* USB32DEV_LNK.LNK_LFPS_RX_U3_EXIT */ 1404 #define USB32DEV_LNK_LFPS_RX_U3_EXIT_BURST24_Pos 0UL 1405 #define USB32DEV_LNK_LFPS_RX_U3_EXIT_BURST24_Msk 0xFFFFFFUL 1406 /* USB32DEV_LNK.LNK_LFPS_RX_U1_HANDSHAKE */ 1407 #define USB32DEV_LNK_LFPS_RX_U1_HANDSHAKE_BURST24_Pos 0UL 1408 #define USB32DEV_LNK_LFPS_RX_U1_HANDSHAKE_BURST24_Msk 0xFFFFFFUL 1409 /* USB32DEV_LNK.LNK_LFPS_RX_U2_HANDSHAKE */ 1410 #define USB32DEV_LNK_LFPS_RX_U2_HANDSHAKE_BURST24_Pos 0UL 1411 #define USB32DEV_LNK_LFPS_RX_U2_HANDSHAKE_BURST24_Msk 0xFFFFFFUL 1412 /* USB32DEV_LNK.LNK_LFPS_RX_U3_HANDSHAKE */ 1413 #define USB32DEV_LNK_LFPS_RX_U3_HANDSHAKE_BURST24_Pos 0UL 1414 #define USB32DEV_LNK_LFPS_RX_U3_HANDSHAKE_BURST24_Msk 0xFFFFFFUL 1415 /* USB32DEV_LNK.LNK_LFPS_RX_LOOPBACK_EXIT */ 1416 #define USB32DEV_LNK_LFPS_RX_LOOPBACK_EXIT_BURST24_Pos 0UL 1417 #define USB32DEV_LNK_LFPS_RX_LOOPBACK_EXIT_BURST24_Msk 0xFFFFFFUL 1418 /* USB32DEV_LNK.LNK_LFPS_RX_LOOPBACK_HANDSHAKE */ 1419 #define USB32DEV_LNK_LFPS_RX_LOOPBACK_HANDSHAKE_BURST24_Pos 0UL 1420 #define USB32DEV_LNK_LFPS_RX_LOOPBACK_HANDSHAKE_BURST24_Msk 0xFFFFFFUL 1421 /* USB32DEV_LNK.LNK_LFPS_RX_IDLE */ 1422 #define USB32DEV_LNK_LFPS_RX_IDLE_TIME_Pos 0UL 1423 #define USB32DEV_LNK_LFPS_RX_IDLE_TIME_Msk 0xFFFFFFFFUL 1424 /* USB32DEV_LNK.LNK_LFPS_RX_BURST */ 1425 #define USB32DEV_LNK_LFPS_RX_BURST_TIME_Pos 0UL 1426 #define USB32DEV_LNK_LFPS_RX_BURST_TIME_Msk 0xFFFFFFFFUL 1427 /* USB32DEV_LNK.LNK_LFPS_RX_TIME */ 1428 #define USB32DEV_LNK_LFPS_RX_TIME_TIME_Pos 0UL 1429 #define USB32DEV_LNK_LFPS_RX_TIME_TIME_Msk 0xFFFFFFFFUL 1430 /* USB32DEV_LNK.LNK_PENDING_HP_TIMER */ 1431 #define USB32DEV_LNK_PENDING_HP_TIMER_TIMER16_Pos 0UL 1432 #define USB32DEV_LNK_PENDING_HP_TIMER_TIMER16_Msk 0xFFFFUL 1433 /* USB32DEV_LNK.LNK_PENDING_HP_TIMEOUT */ 1434 #define USB32DEV_LNK_PENDING_HP_TIMEOUT_TIMEOUT16_Pos 0UL 1435 #define USB32DEV_LNK_PENDING_HP_TIMEOUT_TIMEOUT16_Msk 0xFFFFUL 1436 /* USB32DEV_LNK.LNK_CREDIT_HP_TIMER */ 1437 #define USB32DEV_LNK_CREDIT_HP_TIMER_TIMER_Pos 0UL 1438 #define USB32DEV_LNK_CREDIT_HP_TIMER_TIMER_Msk 0xFFFFFFFFUL 1439 /* USB32DEV_LNK.LNK_CREDIT_HP_TIMEOUT */ 1440 #define USB32DEV_LNK_CREDIT_HP_TIMEOUT_TIMEOUT_Pos 0UL 1441 #define USB32DEV_LNK_CREDIT_HP_TIMEOUT_TIMEOUT_Msk 0xFFFFFFFFUL 1442 /* USB32DEV_LNK.LNK_PM_TIMER */ 1443 #define USB32DEV_LNK_PM_TIMER_TIMER_Pos 0UL 1444 #define USB32DEV_LNK_PM_TIMER_TIMER_Msk 0xFFFFFFFFUL 1445 /* USB32DEV_LNK.LNK_PM_LC_TIMEOUT */ 1446 #define USB32DEV_LNK_PM_LC_TIMEOUT_TIMEOUT16_Pos 0UL 1447 #define USB32DEV_LNK_PM_LC_TIMEOUT_TIMEOUT16_Msk 0xFFFFUL 1448 /* USB32DEV_LNK.LNK_PM_ENTRY_TIMEOUT */ 1449 #define USB32DEV_LNK_PM_ENTRY_TIMEOUT_TIMEOUT16_Pos 0UL 1450 #define USB32DEV_LNK_PM_ENTRY_TIMEOUT_TIMEOUT16_Msk 0xFFFFUL 1451 /* USB32DEV_LNK.LNK_PM_UX_EXIT_TIMEOUT */ 1452 #define USB32DEV_LNK_PM_UX_EXIT_TIMEOUT_TIMEOUT_Pos 0UL 1453 #define USB32DEV_LNK_PM_UX_EXIT_TIMEOUT_TIMEOUT_Msk 0xFFFFFFFFUL 1454 /* USB32DEV_LNK.LNK_LTSSM_TIMER */ 1455 #define USB32DEV_LNK_LTSSM_TIMER_TIMER_Pos 0UL 1456 #define USB32DEV_LNK_LTSSM_TIMER_TIMER_Msk 0xFFFFFFFFUL 1457 /* USB32DEV_LNK.LNK_LTSSM_TIMEOUT */ 1458 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_LFPS_Pos 0UL 1459 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_LFPS_Msk 0x1UL 1460 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_ACTIVE_Pos 1UL 1461 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_ACTIVE_Msk 0x2UL 1462 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_IDLE_Pos 2UL 1463 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_IDLE_Msk 0x4UL 1464 #define USB32DEV_LNK_LTSSM_TIMEOUT_U1_EXIT_Pos 3UL 1465 #define USB32DEV_LNK_LTSSM_TIMEOUT_U1_EXIT_Msk 0x8UL 1466 #define USB32DEV_LNK_LTSSM_TIMEOUT_U2_EXIT_Pos 4UL 1467 #define USB32DEV_LNK_LTSSM_TIMEOUT_U2_EXIT_Msk 0x10UL 1468 #define USB32DEV_LNK_LTSSM_TIMEOUT_U3_EXIT_Pos 5UL 1469 #define USB32DEV_LNK_LTSSM_TIMEOUT_U3_EXIT_Msk 0x20UL 1470 #define USB32DEV_LNK_LTSSM_TIMEOUT_HOT_RESET_ACTIVE_Pos 6UL 1471 #define USB32DEV_LNK_LTSSM_TIMEOUT_HOT_RESET_ACTIVE_Msk 0x40UL 1472 #define USB32DEV_LNK_LTSSM_TIMEOUT_HOT_RESET_EXIT_Pos 7UL 1473 #define USB32DEV_LNK_LTSSM_TIMEOUT_HOT_RESET_EXIT_Msk 0x80UL 1474 #define USB32DEV_LNK_LTSSM_TIMEOUT_LOOPBACK_EXIT_Pos 8UL 1475 #define USB32DEV_LNK_LTSSM_TIMEOUT_LOOPBACK_EXIT_Msk 0x100UL 1476 #define USB32DEV_LNK_LTSSM_TIMEOUT_RECOVERY_IDLE_Pos 9UL 1477 #define USB32DEV_LNK_LTSSM_TIMEOUT_RECOVERY_IDLE_Msk 0x200UL 1478 #define USB32DEV_LNK_LTSSM_TIMEOUT_RECOVERY_ACTIVE_Pos 10UL 1479 #define USB32DEV_LNK_LTSSM_TIMEOUT_RECOVERY_ACTIVE_Msk 0x400UL 1480 #define USB32DEV_LNK_LTSSM_TIMEOUT_RECOVERY_CONFIG_Pos 11UL 1481 #define USB32DEV_LNK_LTSSM_TIMEOUT_RECOVERY_CONFIG_Msk 0x800UL 1482 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_SCD_LFPS_Pos 12UL 1483 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_SCD_LFPS_Msk 0x1000UL 1484 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_LBPM_LFPS_Pos 13UL 1485 #define USB32DEV_LNK_LTSSM_TIMEOUT_POLLING_LBPM_LFPS_Msk 0x2000UL 1486 /* USB32DEV_LNK.LNK_LTSSM_RX_DETECT_PERIOD */ 1487 #define USB32DEV_LNK_LTSSM_RX_DETECT_PERIOD_PERIOD24_Pos 0UL 1488 #define USB32DEV_LNK_LTSSM_RX_DETECT_PERIOD_PERIOD24_Msk 0xFFFFFFUL 1489 /* USB32DEV_LNK.LNK_LTSSM_LUP_PERIOD */ 1490 #define USB32DEV_LNK_LTSSM_LUP_PERIOD_PERIOD24_Pos 0UL 1491 #define USB32DEV_LNK_LTSSM_LUP_PERIOD_PERIOD24_Msk 0xFFFFFFUL 1492 /* USB32DEV_LNK.LNK_LTSSM_SS_INACTIVE_PERIOD */ 1493 #define USB32DEV_LNK_LTSSM_SS_INACTIVE_PERIOD_PERIOD24_Pos 0UL 1494 #define USB32DEV_LNK_LTSSM_SS_INACTIVE_PERIOD_PERIOD24_Msk 0xFFFFFFUL 1495 /* USB32DEV_LNK.LNK_LTSSM_POLLING_LFPS_TIMEOUT */ 1496 #define USB32DEV_LNK_LTSSM_POLLING_LFPS_TIMEOUT_TIMEOUT_Pos 0UL 1497 #define USB32DEV_LNK_LTSSM_POLLING_LFPS_TIMEOUT_TIMEOUT_Msk 0xFFFFFFFFUL 1498 /* USB32DEV_LNK.LNK_LTSSM_POLLING_ACTIVE_TIMEOUT */ 1499 #define USB32DEV_LNK_LTSSM_POLLING_ACTIVE_TIMEOUT_TIMEOUT24_Pos 0UL 1500 #define USB32DEV_LNK_LTSSM_POLLING_ACTIVE_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1501 /* USB32DEV_LNK.LNK_LTSSM_POLLING_CONFIG_TIMEOUT */ 1502 #define USB32DEV_LNK_LTSSM_POLLING_CONFIG_TIMEOUT_TIMEOUT24_Pos 0UL 1503 #define USB32DEV_LNK_LTSSM_POLLING_CONFIG_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1504 /* USB32DEV_LNK.LNK_LTSSM_POLLING_IDLE_TIMEOUT */ 1505 #define USB32DEV_LNK_LTSSM_POLLING_IDLE_TIMEOUT_TIMEOUT24_Pos 0UL 1506 #define USB32DEV_LNK_LTSSM_POLLING_IDLE_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1507 /* USB32DEV_LNK.LNK_LTSSM_U1_EXIT_TIMEOUT */ 1508 #define USB32DEV_LNK_LTSSM_U1_EXIT_TIMEOUT_TIMEOUT24_Pos 0UL 1509 #define USB32DEV_LNK_LTSSM_U1_EXIT_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1510 /* USB32DEV_LNK.LNK_LTSSM_U2_EXIT_TIMEOUT */ 1511 #define USB32DEV_LNK_LTSSM_U2_EXIT_TIMEOUT_TIMEOUT24_Pos 0UL 1512 #define USB32DEV_LNK_LTSSM_U2_EXIT_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1513 /* USB32DEV_LNK.LNK_LTSSM_U3_EXIT_TIMEOUT */ 1514 #define USB32DEV_LNK_LTSSM_U3_EXIT_TIMEOUT_TIMEOUT24_Pos 0UL 1515 #define USB32DEV_LNK_LTSSM_U3_EXIT_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1516 /* USB32DEV_LNK.LNK_LTSSM_HOT_RESET_ACTIVE_TIMEOUT */ 1517 #define USB32DEV_LNK_LTSSM_HOT_RESET_ACTIVE_TIMEOUT_TIMEOUT24_Pos 0UL 1518 #define USB32DEV_LNK_LTSSM_HOT_RESET_ACTIVE_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1519 /* USB32DEV_LNK.LNK_LTSSM_HOT_RESET_EXIT_TIMEOUT */ 1520 #define USB32DEV_LNK_LTSSM_HOT_RESET_EXIT_TIMEOUT_TIMEOUT24_Pos 0UL 1521 #define USB32DEV_LNK_LTSSM_HOT_RESET_EXIT_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1522 /* USB32DEV_LNK.LNK_LTSSM_LOOPBACK_EXIT_TIMEOUT */ 1523 #define USB32DEV_LNK_LTSSM_LOOPBACK_EXIT_TIMEOUT_TIMEOUT_Pos 0UL 1524 #define USB32DEV_LNK_LTSSM_LOOPBACK_EXIT_TIMEOUT_TIMEOUT_Msk 0xFFFFFFFFUL 1525 /* USB32DEV_LNK.LNK_LTSSM_RECOVERY_IDLE_TIMEOUT */ 1526 #define USB32DEV_LNK_LTSSM_RECOVERY_IDLE_TIMEOUT_TIMEOUT24_Pos 0UL 1527 #define USB32DEV_LNK_LTSSM_RECOVERY_IDLE_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1528 /* USB32DEV_LNK.LNK_LTSSM_RECOVERY_ACTIVE_TIMEOUT */ 1529 #define USB32DEV_LNK_LTSSM_RECOVERY_ACTIVE_TIMEOUT_TIMEOUT24_Pos 0UL 1530 #define USB32DEV_LNK_LTSSM_RECOVERY_ACTIVE_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1531 /* USB32DEV_LNK.LNK_LTSSM_RECOVERY_CONFIG_TIMEOUT */ 1532 #define USB32DEV_LNK_LTSSM_RECOVERY_CONFIG_TIMEOUT_TIMEOUT24_Pos 0UL 1533 #define USB32DEV_LNK_LTSSM_RECOVERY_CONFIG_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1534 /* USB32DEV_LNK.LNK_LTSSM_LDN_TIMEOUT */ 1535 #define USB32DEV_LNK_LTSSM_LDN_TIMEOUT_TIMEOUT24_Pos 0UL 1536 #define USB32DEV_LNK_LTSSM_LDN_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1537 /* USB32DEV_LNK.LNK_LTSSM_LDN_TIMER */ 1538 #define USB32DEV_LNK_LTSSM_LDN_TIMER_TIMER24_Pos 0UL 1539 #define USB32DEV_LNK_LTSSM_LDN_TIMER_TIMER24_Msk 0xFFFFFFUL 1540 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_0 */ 1541 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_CP_Pos 0UL 1542 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_CP_Msk 0xFFUL 1543 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_K_D_Pos 8UL 1544 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_K_D_Msk 0x100UL 1545 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_SCRAMBLED_Pos 9UL 1546 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_SCRAMBLED_Msk 0x200UL 1547 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_DEEMPHASIS_Pos 10UL 1548 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_DEEMPHASIS_Msk 0x400UL 1549 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_LFPS_Pos 11UL 1550 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_LFPS_Msk 0x800UL 1551 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_TXONESZEROS_Pos 12UL 1552 #define USB32DEV_LNK_COMPLIANCE_PATTERN_0_TXONESZEROS_Msk 0x1000UL 1553 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_1 */ 1554 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_CP_Pos 0UL 1555 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_CP_Msk 0xFFUL 1556 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_K_D_Pos 8UL 1557 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_K_D_Msk 0x100UL 1558 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_SCRAMBLED_Pos 9UL 1559 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_SCRAMBLED_Msk 0x200UL 1560 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_DEEMPHASIS_Pos 10UL 1561 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_DEEMPHASIS_Msk 0x400UL 1562 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_LFPS_Pos 11UL 1563 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_LFPS_Msk 0x800UL 1564 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_TXONESZEROS_Pos 12UL 1565 #define USB32DEV_LNK_COMPLIANCE_PATTERN_1_TXONESZEROS_Msk 0x1000UL 1566 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_2 */ 1567 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_CP_Pos 0UL 1568 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_CP_Msk 0xFFUL 1569 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_K_D_Pos 8UL 1570 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_K_D_Msk 0x100UL 1571 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_SCRAMBLED_Pos 9UL 1572 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_SCRAMBLED_Msk 0x200UL 1573 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_DEEMPHASIS_Pos 10UL 1574 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_DEEMPHASIS_Msk 0x400UL 1575 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_LFPS_Pos 11UL 1576 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_LFPS_Msk 0x800UL 1577 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_TXONESZEROS_Pos 12UL 1578 #define USB32DEV_LNK_COMPLIANCE_PATTERN_2_TXONESZEROS_Msk 0x1000UL 1579 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_3 */ 1580 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_CP_Pos 0UL 1581 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_CP_Msk 0xFFUL 1582 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_K_D_Pos 8UL 1583 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_K_D_Msk 0x100UL 1584 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_SCRAMBLED_Pos 9UL 1585 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_SCRAMBLED_Msk 0x200UL 1586 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_DEEMPHASIS_Pos 10UL 1587 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_DEEMPHASIS_Msk 0x400UL 1588 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_LFPS_Pos 11UL 1589 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_LFPS_Msk 0x800UL 1590 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_TXONESZEROS_Pos 12UL 1591 #define USB32DEV_LNK_COMPLIANCE_PATTERN_3_TXONESZEROS_Msk 0x1000UL 1592 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_4 */ 1593 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_CP_Pos 0UL 1594 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_CP_Msk 0xFFUL 1595 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_K_D_Pos 8UL 1596 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_K_D_Msk 0x100UL 1597 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_SCRAMBLED_Pos 9UL 1598 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_SCRAMBLED_Msk 0x200UL 1599 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_DEEMPHASIS_Pos 10UL 1600 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_DEEMPHASIS_Msk 0x400UL 1601 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_LFPS_Pos 11UL 1602 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_LFPS_Msk 0x800UL 1603 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_TXONESZEROS_Pos 12UL 1604 #define USB32DEV_LNK_COMPLIANCE_PATTERN_4_TXONESZEROS_Msk 0x1000UL 1605 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_5 */ 1606 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_CP_Pos 0UL 1607 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_CP_Msk 0xFFUL 1608 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_K_D_Pos 8UL 1609 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_K_D_Msk 0x100UL 1610 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_SCRAMBLED_Pos 9UL 1611 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_SCRAMBLED_Msk 0x200UL 1612 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_DEEMPHASIS_Pos 10UL 1613 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_DEEMPHASIS_Msk 0x400UL 1614 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_LFPS_Pos 11UL 1615 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_LFPS_Msk 0x800UL 1616 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_TXONESZEROS_Pos 12UL 1617 #define USB32DEV_LNK_COMPLIANCE_PATTERN_5_TXONESZEROS_Msk 0x1000UL 1618 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_6 */ 1619 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_CP_Pos 0UL 1620 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_CP_Msk 0xFFUL 1621 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_K_D_Pos 8UL 1622 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_K_D_Msk 0x100UL 1623 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_SCRAMBLED_Pos 9UL 1624 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_SCRAMBLED_Msk 0x200UL 1625 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_DEEMPHASIS_Pos 10UL 1626 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_DEEMPHASIS_Msk 0x400UL 1627 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_LFPS_Pos 11UL 1628 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_LFPS_Msk 0x800UL 1629 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_TXONESZEROS_Pos 12UL 1630 #define USB32DEV_LNK_COMPLIANCE_PATTERN_6_TXONESZEROS_Msk 0x1000UL 1631 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_7 */ 1632 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_CP_Pos 0UL 1633 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_CP_Msk 0xFFUL 1634 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_K_D_Pos 8UL 1635 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_K_D_Msk 0x100UL 1636 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_SCRAMBLED_Pos 9UL 1637 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_SCRAMBLED_Msk 0x200UL 1638 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_DEEMPHASIS_Pos 10UL 1639 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_DEEMPHASIS_Msk 0x400UL 1640 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_LFPS_Pos 11UL 1641 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_LFPS_Msk 0x800UL 1642 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_TXONESZEROS_Pos 12UL 1643 #define USB32DEV_LNK_COMPLIANCE_PATTERN_7_TXONESZEROS_Msk 0x1000UL 1644 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_8 */ 1645 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_CP_Pos 0UL 1646 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_CP_Msk 0xFFUL 1647 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_K_D_Pos 8UL 1648 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_K_D_Msk 0x100UL 1649 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_SCRAMBLED_Pos 9UL 1650 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_SCRAMBLED_Msk 0x200UL 1651 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_DEEMPHASIS_Pos 10UL 1652 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_DEEMPHASIS_Msk 0x400UL 1653 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_LFPS_Pos 11UL 1654 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_LFPS_Msk 0x800UL 1655 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_TXONESZEROS_Pos 12UL 1656 #define USB32DEV_LNK_COMPLIANCE_PATTERN_8_TXONESZEROS_Msk 0x1000UL 1657 /* USB32DEV_LNK.LNK_DEBUG_BUFFER_CTRL */ 1658 #define USB32DEV_LNK_DEBUG_BUFFER_CTRL_MEM_PTR_Pos 0UL 1659 #define USB32DEV_LNK_DEBUG_BUFFER_CTRL_MEM_PTR_Msk 0x7UL 1660 /* USB32DEV_LNK.LNK_DATARATE_CHG_OBSERVE */ 1661 #define USB32DEV_LNK_DATARATE_CHG_OBSERVE_DATA_RATE_CHG_DET_Pos 0UL 1662 #define USB32DEV_LNK_DATARATE_CHG_OBSERVE_DATA_RATE_CHG_DET_Msk 0x1FUL 1663 /* USB32DEV_LNK.LNK_LFPS_TX_POLLING_BURST_GEN2 */ 1664 #define USB32DEV_LNK_LFPS_TX_POLLING_BURST_GEN2_BURST16_Pos 0UL 1665 #define USB32DEV_LNK_LFPS_TX_POLLING_BURST_GEN2_BURST16_Msk 0xFFFFUL 1666 /* USB32DEV_LNK.LNK_LFPS_TX_POLLING_REPEAT_GEN2 */ 1667 #define USB32DEV_LNK_LFPS_TX_POLLING_REPEAT_GEN2_REPEAT16_Pos 0UL 1668 #define USB32DEV_LNK_LFPS_TX_POLLING_REPEAT_GEN2_REPEAT16_Msk 0xFFFFUL 1669 /* USB32DEV_LNK.LNK_LFPS_TX_PING_BURST_GEN2 */ 1670 #define USB32DEV_LNK_LFPS_TX_PING_BURST_GEN2_BURST16_Pos 0UL 1671 #define USB32DEV_LNK_LFPS_TX_PING_BURST_GEN2_BURST16_Msk 0xFFFFUL 1672 /* USB32DEV_LNK.LNK_LFPS_TX_PING_REPEAT_GEN2 */ 1673 #define USB32DEV_LNK_LFPS_TX_PING_REPEAT_GEN2_REPEAT32_Pos 0UL 1674 #define USB32DEV_LNK_LFPS_TX_PING_REPEAT_GEN2_REPEAT32_Msk 0xFFFFFFFFUL 1675 /* USB32DEV_LNK.LNK_LFPS_TX_U1_EXIT_GEN2 */ 1676 #define USB32DEV_LNK_LFPS_TX_U1_EXIT_GEN2_BURST24_Pos 0UL 1677 #define USB32DEV_LNK_LFPS_TX_U1_EXIT_GEN2_BURST24_Msk 0xFFFFFFUL 1678 /* USB32DEV_LNK.LNK_LFPS_TX_U2_EXIT_GEN2 */ 1679 #define USB32DEV_LNK_LFPS_TX_U2_EXIT_GEN2_BURST24_Pos 0UL 1680 #define USB32DEV_LNK_LFPS_TX_U2_EXIT_GEN2_BURST24_Msk 0xFFFFFFUL 1681 /* USB32DEV_LNK.LNK_LFPS_TX_U3_EXIT_GEN2 */ 1682 #define USB32DEV_LNK_LFPS_TX_U3_EXIT_GEN2_BURST24_Pos 0UL 1683 #define USB32DEV_LNK_LFPS_TX_U3_EXIT_GEN2_BURST24_Msk 0xFFFFFFUL 1684 /* USB32DEV_LNK.LNK_LFPS_RX_POLLING_BURST_GEN2 */ 1685 #define USB32DEV_LNK_LFPS_RX_POLLING_BURST_GEN2_BURST_MIN_Pos 0UL 1686 #define USB32DEV_LNK_LFPS_RX_POLLING_BURST_GEN2_BURST_MIN_Msk 0xFFFFUL 1687 #define USB32DEV_LNK_LFPS_RX_POLLING_BURST_GEN2_BURST_MAX_Pos 16UL 1688 #define USB32DEV_LNK_LFPS_RX_POLLING_BURST_GEN2_BURST_MAX_Msk 0xFFFF0000UL 1689 /* USB32DEV_LNK.LNK_LFPS_RX_POLLING_REPEAT_GEN2 */ 1690 #define USB32DEV_LNK_LFPS_RX_POLLING_REPEAT_GEN2_REPEAT_MIN_Pos 0UL 1691 #define USB32DEV_LNK_LFPS_RX_POLLING_REPEAT_GEN2_REPEAT_MIN_Msk 0xFFFFUL 1692 #define USB32DEV_LNK_LFPS_RX_POLLING_REPEAT_GEN2_REPEAT_MAX_Pos 16UL 1693 #define USB32DEV_LNK_LFPS_RX_POLLING_REPEAT_GEN2_REPEAT_MAX_Msk 0xFFFF0000UL 1694 /* USB32DEV_LNK.LNK_LFPS_RX_PING_GEN2 */ 1695 #define USB32DEV_LNK_LFPS_RX_PING_GEN2_BURST_MIN_Pos 0UL 1696 #define USB32DEV_LNK_LFPS_RX_PING_GEN2_BURST_MIN_Msk 0xFFFFUL 1697 #define USB32DEV_LNK_LFPS_RX_PING_GEN2_BURST_MAX_Pos 16UL 1698 #define USB32DEV_LNK_LFPS_RX_PING_GEN2_BURST_MAX_Msk 0xFFFF0000UL 1699 /* USB32DEV_LNK.LNK_LFPS_RX_RESET_GEN2 */ 1700 #define USB32DEV_LNK_LFPS_RX_RESET_GEN2_BURST32_Pos 0UL 1701 #define USB32DEV_LNK_LFPS_RX_RESET_GEN2_BURST32_Msk 0xFFFFFFFFUL 1702 /* USB32DEV_LNK.LNK_LFPS_RX_U1_EXIT_GEN2 */ 1703 #define USB32DEV_LNK_LFPS_RX_U1_EXIT_GEN2_BURST24_Pos 0UL 1704 #define USB32DEV_LNK_LFPS_RX_U1_EXIT_GEN2_BURST24_Msk 0xFFFFFFUL 1705 /* USB32DEV_LNK.LNK_LFPS_RX_U2_EXIT_GEN2 */ 1706 #define USB32DEV_LNK_LFPS_RX_U2_EXIT_GEN2_BURST24_Pos 0UL 1707 #define USB32DEV_LNK_LFPS_RX_U2_EXIT_GEN2_BURST24_Msk 0xFFFFFFUL 1708 /* USB32DEV_LNK.LNK_LFPS_RX_U1_HANDSHAKE_GEN2 */ 1709 #define USB32DEV_LNK_LFPS_RX_U1_HANDSHAKE_GEN2_BURST24_Pos 0UL 1710 #define USB32DEV_LNK_LFPS_RX_U1_HANDSHAKE_GEN2_BURST24_Msk 0xFFFFFFUL 1711 /* USB32DEV_LNK.LNK_LFPS_RX_U2_HANDSHAKE_GEN2 */ 1712 #define USB32DEV_LNK_LFPS_RX_U2_HANDSHAKE_GEN2_BURST24_Pos 0UL 1713 #define USB32DEV_LNK_LFPS_RX_U2_HANDSHAKE_GEN2_BURST24_Msk 0xFFFFFFUL 1714 /* USB32DEV_LNK.LNK_LFPS_RX_U3_HANDSHAKE_GEN2 */ 1715 #define USB32DEV_LNK_LFPS_RX_U3_HANDSHAKE_GEN2_BURST24_Pos 0UL 1716 #define USB32DEV_LNK_LFPS_RX_U3_HANDSHAKE_GEN2_BURST24_Msk 0xFFFFFFUL 1717 /* USB32DEV_LNK.LNK_LFPS_RX_LOOPBACK_EXIT_GEN2 */ 1718 #define USB32DEV_LNK_LFPS_RX_LOOPBACK_EXIT_GEN2_BURST24_Pos 0UL 1719 #define USB32DEV_LNK_LFPS_RX_LOOPBACK_EXIT_GEN2_BURST24_Msk 0xFFFFFFUL 1720 /* USB32DEV_LNK.LNK_LFPS_RX_LOOPBACK_HANDSHAKE_GEN2 */ 1721 #define USB32DEV_LNK_LFPS_RX_LOOPBACK_HANDSHAKE_GEN2_BURST24_Pos 0UL 1722 #define USB32DEV_LNK_LFPS_RX_LOOPBACK_HANDSHAKE_GEN2_BURST24_Msk 0xFFFFFFUL 1723 /* USB32DEV_LNK.LNK_PENDING_HP_TIMEOUT_GEN2 */ 1724 #define USB32DEV_LNK_PENDING_HP_TIMEOUT_GEN2_TIMEOUT16_Pos 0UL 1725 #define USB32DEV_LNK_PENDING_HP_TIMEOUT_GEN2_TIMEOUT16_Msk 0xFFFFUL 1726 /* USB32DEV_LNK.LNK_CREDIT_HP_TIMEOUT_GEN2 */ 1727 #define USB32DEV_LNK_CREDIT_HP_TIMEOUT_GEN2_TIMEOUT_Pos 0UL 1728 #define USB32DEV_LNK_CREDIT_HP_TIMEOUT_GEN2_TIMEOUT_Msk 0xFFFFFFFFUL 1729 /* USB32DEV_LNK.LNK_PM_LC_X2_TIMEOUT_GEN1 */ 1730 #define USB32DEV_LNK_PM_LC_X2_TIMEOUT_GEN1_TIMEOUT16_Pos 0UL 1731 #define USB32DEV_LNK_PM_LC_X2_TIMEOUT_GEN1_TIMEOUT16_Msk 0xFFFFUL 1732 /* USB32DEV_LNK.LNK_PM_LC_X1_TIMEOUT_GEN2 */ 1733 #define USB32DEV_LNK_PM_LC_X1_TIMEOUT_GEN2_TIMEOUT16_Pos 0UL 1734 #define USB32DEV_LNK_PM_LC_X1_TIMEOUT_GEN2_TIMEOUT16_Msk 0xFFFFUL 1735 /* USB32DEV_LNK.LNK_PM_LC_X2_TIMEOUT_GEN2 */ 1736 #define USB32DEV_LNK_PM_LC_X2_TIMEOUT_GEN2_TIMEOUT16_Pos 0UL 1737 #define USB32DEV_LNK_PM_LC_X2_TIMEOUT_GEN2_TIMEOUT16_Msk 0xFFFFUL 1738 /* USB32DEV_LNK.LNK_PM_ENTRY_X2_TIMEOUT_GEN1 */ 1739 #define USB32DEV_LNK_PM_ENTRY_X2_TIMEOUT_GEN1_TIMEOUT16_Pos 0UL 1740 #define USB32DEV_LNK_PM_ENTRY_X2_TIMEOUT_GEN1_TIMEOUT16_Msk 0xFFFFUL 1741 /* USB32DEV_LNK.LNK_PM_ENTRY_X1_TIMEOUT_GEN2 */ 1742 #define USB32DEV_LNK_PM_ENTRY_X1_TIMEOUT_GEN2_TIMEOUT16_Pos 0UL 1743 #define USB32DEV_LNK_PM_ENTRY_X1_TIMEOUT_GEN2_TIMEOUT16_Msk 0xFFFFUL 1744 /* USB32DEV_LNK.LNK_PM_ENTRY_X2_TIMEOUT_GEN2 */ 1745 #define USB32DEV_LNK_PM_ENTRY_X2_TIMEOUT_GEN2_TIMEOUT16_Pos 0UL 1746 #define USB32DEV_LNK_PM_ENTRY_X2_TIMEOUT_GEN2_TIMEOUT16_Msk 0xFFFFUL 1747 /* USB32DEV_LNK.LNK_PM_UX_EXIT_TIMEOUT_GEN2 */ 1748 #define USB32DEV_LNK_PM_UX_EXIT_TIMEOUT_GEN2_TIMEOUT_Pos 0UL 1749 #define USB32DEV_LNK_PM_UX_EXIT_TIMEOUT_GEN2_TIMEOUT_Msk 0xFFFFFFFFUL 1750 /* USB32DEV_LNK.LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN1 */ 1751 #define USB32DEV_LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN1_TIMEOUT16_Pos 0UL 1752 #define USB32DEV_LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN1_TIMEOUT16_Msk 0xFFFFUL 1753 /* USB32DEV_LNK.LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN2 */ 1754 #define USB32DEV_LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN2_TIMEOUT16_Pos 0UL 1755 #define USB32DEV_LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN2_TIMEOUT16_Msk 0xFFFFUL 1756 /* USB32DEV_LNK.LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN1 */ 1757 #define USB32DEV_LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN1_REPEAT16_Pos 0UL 1758 #define USB32DEV_LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN1_REPEAT16_Msk 0xFFFFUL 1759 /* USB32DEV_LNK.LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN1 */ 1760 #define USB32DEV_LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN1_REPEAT16_Pos 0UL 1761 #define USB32DEV_LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN1_REPEAT16_Msk 0xFFFFUL 1762 /* USB32DEV_LNK.LNK_LFPS_TX_SCD_END_REPEAT_GEN1 */ 1763 #define USB32DEV_LNK_LFPS_TX_SCD_END_REPEAT_GEN1_REPEAT16_Pos 0UL 1764 #define USB32DEV_LNK_LFPS_TX_SCD_END_REPEAT_GEN1_REPEAT16_Msk 0xFFFFUL 1765 /* USB32DEV_LNK.LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN1 */ 1766 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN1_REPEAT_MIN_Pos 0UL 1767 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN1_REPEAT_MIN_Msk 0xFFFFUL 1768 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN1_REPEAT_MAX_Pos 16UL 1769 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN1_REPEAT_MAX_Msk 0xFFFF0000UL 1770 /* USB32DEV_LNK.LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN1 */ 1771 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN1_REPEAT_MIN_Pos 0UL 1772 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN1_REPEAT_MIN_Msk 0xFFFFUL 1773 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN1_REPEAT_MAX_Pos 16UL 1774 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN1_REPEAT_MAX_Msk 0xFFFF0000UL 1775 /* USB32DEV_LNK.LNK_LFPS_RX_SCD_END_REPEAT_GEN1 */ 1776 #define USB32DEV_LNK_LFPS_RX_SCD_END_REPEAT_GEN1_REPEAT_MIN_Pos 0UL 1777 #define USB32DEV_LNK_LFPS_RX_SCD_END_REPEAT_GEN1_REPEAT_MIN_Msk 0xFFFFUL 1778 /* USB32DEV_LNK.LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN2 */ 1779 #define USB32DEV_LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN2_REPEAT16_Pos 0UL 1780 #define USB32DEV_LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN2_REPEAT16_Msk 0xFFFFUL 1781 /* USB32DEV_LNK.LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN2 */ 1782 #define USB32DEV_LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN2_REPEAT16_Pos 0UL 1783 #define USB32DEV_LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN2_REPEAT16_Msk 0xFFFFUL 1784 /* USB32DEV_LNK.LNK_LFPS_TX_SCD_END_REPEAT_GEN2 */ 1785 #define USB32DEV_LNK_LFPS_TX_SCD_END_REPEAT_GEN2_REPEAT16_Pos 0UL 1786 #define USB32DEV_LNK_LFPS_TX_SCD_END_REPEAT_GEN2_REPEAT16_Msk 0xFFFFUL 1787 /* USB32DEV_LNK.LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN2 */ 1788 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN2_REPEAT_MIN_Pos 0UL 1789 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN2_REPEAT_MIN_Msk 0xFFFFUL 1790 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN2_REPEAT_MAX_Pos 16UL 1791 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN2_REPEAT_MAX_Msk 0xFFFF0000UL 1792 /* USB32DEV_LNK.LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN2 */ 1793 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN2_REPEAT_MIN_Pos 0UL 1794 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN2_REPEAT_MIN_Msk 0xFFFFUL 1795 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN2_REPEAT_MAX_Pos 16UL 1796 #define USB32DEV_LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN2_REPEAT_MAX_Msk 0xFFFF0000UL 1797 /* USB32DEV_LNK.LNK_LFPS_RX_SCD_END_REPEAT_GEN2 */ 1798 #define USB32DEV_LNK_LFPS_RX_SCD_END_REPEAT_GEN2_REPEAT_MIN_Pos 0UL 1799 #define USB32DEV_LNK_LFPS_RX_SCD_END_REPEAT_GEN2_REPEAT_MIN_Msk 0xFFFFUL 1800 /* USB32DEV_LNK.LNK_LFPS_TX_LBPS_TPWM_GEN1 */ 1801 #define USB32DEV_LNK_LFPS_TX_LBPS_TPWM_GEN1_REPEAT16_Pos 0UL 1802 #define USB32DEV_LNK_LFPS_TX_LBPS_TPWM_GEN1_REPEAT16_Msk 0xFFFFUL 1803 /* USB32DEV_LNK.LNK_LFPS_TX_LBPS_TLFPS0_GEN1 */ 1804 #define USB32DEV_LNK_LFPS_TX_LBPS_TLFPS0_GEN1_BURST16_Pos 0UL 1805 #define USB32DEV_LNK_LFPS_TX_LBPS_TLFPS0_GEN1_BURST16_Msk 0xFFFFUL 1806 /* USB32DEV_LNK.LNK_LFPS_TX_LBPS_TLFPS1_GEN1 */ 1807 #define USB32DEV_LNK_LFPS_TX_LBPS_TLFPS1_GEN1_BURST16_Pos 0UL 1808 #define USB32DEV_LNK_LFPS_TX_LBPS_TLFPS1_GEN1_BURST16_Msk 0xFFFFUL 1809 /* USB32DEV_LNK.LNK_LFPS_RX_LBPS_TPWM_GEN1 */ 1810 #define USB32DEV_LNK_LFPS_RX_LBPS_TPWM_GEN1_REPEAT_MIN_Pos 0UL 1811 #define USB32DEV_LNK_LFPS_RX_LBPS_TPWM_GEN1_REPEAT_MIN_Msk 0xFFFFUL 1812 #define USB32DEV_LNK_LFPS_RX_LBPS_TPWM_GEN1_REPEAT_MAX_Pos 16UL 1813 #define USB32DEV_LNK_LFPS_RX_LBPS_TPWM_GEN1_REPEAT_MAX_Msk 0xFFFF0000UL 1814 /* USB32DEV_LNK.LNK_LFPS_RX_LBPS_TLFPS0_GEN1 */ 1815 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS0_GEN1_BURST_MIN_Pos 0UL 1816 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS0_GEN1_BURST_MIN_Msk 0xFFFFUL 1817 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS0_GEN1_BURST_MAX_Pos 16UL 1818 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS0_GEN1_BURST_MAX_Msk 0xFFFF0000UL 1819 /* USB32DEV_LNK.LNK_LFPS_RX_LBPS_TLFPS1_GEN1 */ 1820 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS1_GEN1_BURST_MIN_Pos 0UL 1821 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS1_GEN1_BURST_MIN_Msk 0xFFFFUL 1822 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS1_GEN1_BURST_MAX_Pos 16UL 1823 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS1_GEN1_BURST_MAX_Msk 0xFFFF0000UL 1824 /* USB32DEV_LNK.LNK_LFPS_TX_LBPS_TPWM_GEN2 */ 1825 #define USB32DEV_LNK_LFPS_TX_LBPS_TPWM_GEN2_REPEAT16_Pos 0UL 1826 #define USB32DEV_LNK_LFPS_TX_LBPS_TPWM_GEN2_REPEAT16_Msk 0xFFFFUL 1827 /* USB32DEV_LNK.LNK_LFPS_TX_LBPS_TLFPS0_GEN2 */ 1828 #define USB32DEV_LNK_LFPS_TX_LBPS_TLFPS0_GEN2_BURST16_Pos 0UL 1829 #define USB32DEV_LNK_LFPS_TX_LBPS_TLFPS0_GEN2_BURST16_Msk 0xFFFFUL 1830 /* USB32DEV_LNK.LNK_LFPS_TX_LBPS_TLFPS1_GEN2 */ 1831 #define USB32DEV_LNK_LFPS_TX_LBPS_TLFPS1_GEN2_BURST16_Pos 0UL 1832 #define USB32DEV_LNK_LFPS_TX_LBPS_TLFPS1_GEN2_BURST16_Msk 0xFFFFUL 1833 /* USB32DEV_LNK.LNK_LFPS_RX_LBPS_TPWM_GEN2 */ 1834 #define USB32DEV_LNK_LFPS_RX_LBPS_TPWM_GEN2_REPEAT_MIN_Pos 0UL 1835 #define USB32DEV_LNK_LFPS_RX_LBPS_TPWM_GEN2_REPEAT_MIN_Msk 0xFFFFUL 1836 #define USB32DEV_LNK_LFPS_RX_LBPS_TPWM_GEN2_REPEAT_MAX_Pos 16UL 1837 #define USB32DEV_LNK_LFPS_RX_LBPS_TPWM_GEN2_REPEAT_MAX_Msk 0xFFFF0000UL 1838 /* USB32DEV_LNK.LNK_LFPS_RX_LBPS_TLFPS0_GEN2 */ 1839 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS0_GEN2_BURST_MIN_Pos 0UL 1840 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS0_GEN2_BURST_MIN_Msk 0xFFFFUL 1841 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS0_GEN2_BURST_MAX_Pos 16UL 1842 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS0_GEN2_BURST_MAX_Msk 0xFFFF0000UL 1843 /* USB32DEV_LNK.LNK_LFPS_RX_LBPS_TLFPS1_GEN2 */ 1844 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS1_GEN2_BURST_MIN_Pos 0UL 1845 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS1_GEN2_BURST_MIN_Msk 0xFFFFUL 1846 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS1_GEN2_BURST_MAX_Pos 16UL 1847 #define USB32DEV_LNK_LFPS_RX_LBPS_TLFPS1_GEN2_BURST_MAX_Msk 0xFFFF0000UL 1848 /* USB32DEV_LNK.LNK_LFPS_SCD_PATTERN */ 1849 #define USB32DEV_LNK_LFPS_SCD_PATTERN_SCD1_PATTERN_Pos 0UL 1850 #define USB32DEV_LNK_LFPS_SCD_PATTERN_SCD1_PATTERN_Msk 0xFUL 1851 #define USB32DEV_LNK_LFPS_SCD_PATTERN_SCD2_PATTERN_Pos 4UL 1852 #define USB32DEV_LNK_LFPS_SCD_PATTERN_SCD2_PATTERN_Msk 0xF0UL 1853 /* USB32DEV_LNK.LNK_TSEQ_COUNT_GEN1 */ 1854 #define USB32DEV_LNK_TSEQ_COUNT_GEN1_COUNT24_Pos 0UL 1855 #define USB32DEV_LNK_TSEQ_COUNT_GEN1_COUNT24_Msk 0xFFFFFFUL 1856 /* USB32DEV_LNK.LNK_TSEQ_COUNT_GEN2 */ 1857 #define USB32DEV_LNK_TSEQ_COUNT_GEN2_COUNT24_Pos 0UL 1858 #define USB32DEV_LNK_TSEQ_COUNT_GEN2_COUNT24_Msk 0xFFFFFFUL 1859 /* USB32DEV_LNK.LNK_SCD1_GEN2_HSK */ 1860 #define USB32DEV_LNK_SCD1_GEN2_HSK_RX_SCDX_CNT_Pos 0UL 1861 #define USB32DEV_LNK_SCD1_GEN2_HSK_RX_SCDX_CNT_Msk 0x7UL 1862 #define USB32DEV_LNK_SCD1_GEN2_HSK_ARX_SCDX_LIMIT_Pos 8UL 1863 #define USB32DEV_LNK_SCD1_GEN2_HSK_ARX_SCDX_LIMIT_Msk 0x300UL 1864 #define USB32DEV_LNK_SCD1_GEN2_HSK_TX_ARX_SCD1_CNT_Pos 12UL 1865 #define USB32DEV_LNK_SCD1_GEN2_HSK_TX_ARX_SCD1_CNT_Msk 0x7000UL 1866 /* USB32DEV_LNK.LNK_SCD1_GEN2_TO_GEN1_HSK */ 1867 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_SCDXCHK_RX_LFPS_CNT_Pos 0UL 1868 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_SCDXCHK_RX_LFPS_CNT_Msk 0x7FUL 1869 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_TX_SCD1_CNT_Pos 8UL 1870 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_TX_SCD1_CNT_Msk 0xF00UL 1871 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_RX_LFPS_CNT_Pos 12UL 1872 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_RX_LFPS_CNT_Msk 0x7000UL 1873 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_ARX_LFPS_LIMIT_Pos 16UL 1874 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_ARX_LFPS_LIMIT_Msk 0x70000UL 1875 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_TX_ARX_SCD1_CNT_Pos 20UL 1876 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_TX_ARX_SCD1_CNT_Msk 0x700000UL 1877 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_TX_LFPS_CNT_Pos 24UL 1878 #define USB32DEV_LNK_SCD1_GEN2_TO_GEN1_HSK_G2G1_TX_LFPS_CNT_Msk 0x1F000000UL 1879 /* USB32DEV_LNK.LNK_SCD1_OBSERVE */ 1880 #define USB32DEV_LNK_SCD1_OBSERVE_RCVD_SCD2_CNT_Pos 0UL 1881 #define USB32DEV_LNK_SCD1_OBSERVE_RCVD_SCD2_CNT_Msk 0x7UL 1882 #define USB32DEV_LNK_SCD1_OBSERVE_RCVD_SCD1_CNT_Pos 4UL 1883 #define USB32DEV_LNK_SCD1_OBSERVE_RCVD_SCD1_CNT_Msk 0x70UL 1884 #define USB32DEV_LNK_SCD1_OBSERVE_SENT_SCD1_CNT_G2_ARX_Pos 12UL 1885 #define USB32DEV_LNK_SCD1_OBSERVE_SENT_SCD1_CNT_G2_ARX_Msk 0x7000UL 1886 #define USB32DEV_LNK_SCD1_OBSERVE_SENT_SCD1_CNT_G2G1_ARX_Pos 20UL 1887 #define USB32DEV_LNK_SCD1_OBSERVE_SENT_SCD1_CNT_G2G1_ARX_Msk 0x700000UL 1888 #define USB32DEV_LNK_SCD1_OBSERVE_G2G1_LFPS_HSK_DONE_Pos 30UL 1889 #define USB32DEV_LNK_SCD1_OBSERVE_G2G1_LFPS_HSK_DONE_Msk 0x40000000UL 1890 #define USB32DEV_LNK_SCD1_OBSERVE_SCD1_HSK_DONE_Pos 31UL 1891 #define USB32DEV_LNK_SCD1_OBSERVE_SCD1_HSK_DONE_Msk 0x80000000UL 1892 /* USB32DEV_LNK.LNK_SCD2_GEN2_HSK */ 1893 #define USB32DEV_LNK_SCD2_GEN2_HSK_RX_SCD2_CNT_Pos 0UL 1894 #define USB32DEV_LNK_SCD2_GEN2_HSK_RX_SCD2_CNT_Msk 0x7UL 1895 #define USB32DEV_LNK_SCD2_GEN2_HSK_ARX_SCD2_LIMIT_Pos 8UL 1896 #define USB32DEV_LNK_SCD2_GEN2_HSK_ARX_SCD2_LIMIT_Msk 0x300UL 1897 #define USB32DEV_LNK_SCD2_GEN2_HSK_TX_ARX_SCD2_CNT_Pos 12UL 1898 #define USB32DEV_LNK_SCD2_GEN2_HSK_TX_ARX_SCD2_CNT_Msk 0x7000UL 1899 /* USB32DEV_LNK.LNK_SCD2_GEN2_TO_GEN1_HSK */ 1900 #define USB32DEV_LNK_SCD2_GEN2_TO_GEN1_HSK_SCD2CHK_RX_LFPS_CNT_Pos 0UL 1901 #define USB32DEV_LNK_SCD2_GEN2_TO_GEN1_HSK_SCD2CHK_RX_LFPS_CNT_Msk 0x7FUL 1902 #define USB32DEV_LNK_SCD2_GEN2_TO_GEN1_HSK_G2G1_TX_LFPS_CNT_Pos 24UL 1903 #define USB32DEV_LNK_SCD2_GEN2_TO_GEN1_HSK_G2G1_TX_LFPS_CNT_Msk 0x1F000000UL 1904 /* USB32DEV_LNK.LNK_SCD2_OBSERVE */ 1905 #define USB32DEV_LNK_SCD2_OBSERVE_RCVD_SCD2_CNT_Pos 0UL 1906 #define USB32DEV_LNK_SCD2_OBSERVE_RCVD_SCD2_CNT_Msk 0x7UL 1907 #define USB32DEV_LNK_SCD2_OBSERVE_SENT_SCD2_CNT_G2_ARX_Pos 8UL 1908 #define USB32DEV_LNK_SCD2_OBSERVE_SENT_SCD2_CNT_G2_ARX_Msk 0x700UL 1909 #define USB32DEV_LNK_SCD2_OBSERVE_G2G1_LFPS_HSK_DONE_Pos 30UL 1910 #define USB32DEV_LNK_SCD2_OBSERVE_G2G1_LFPS_HSK_DONE_Msk 0x40000000UL 1911 #define USB32DEV_LNK_SCD2_OBSERVE_SCD2_HSK_DONE_Pos 31UL 1912 #define USB32DEV_LNK_SCD2_OBSERVE_SCD2_HSK_DONE_Msk 0x80000000UL 1913 /* USB32DEV_LNK.LNK_CAP_LBPM_HSK */ 1914 #define USB32DEV_LNK_CAP_LBPM_HSK_RX_CAP_LBPM_CNT_Pos 4UL 1915 #define USB32DEV_LNK_CAP_LBPM_HSK_RX_CAP_LBPM_CNT_Msk 0x70UL 1916 #define USB32DEV_LNK_CAP_LBPM_HSK_ARX_LBPM_LIMIT_Pos 8UL 1917 #define USB32DEV_LNK_CAP_LBPM_HSK_ARX_LBPM_LIMIT_Msk 0x700UL 1918 #define USB32DEV_LNK_CAP_LBPM_HSK_TX_ARX_CAP_LBPM_CNT_Pos 12UL 1919 #define USB32DEV_LNK_CAP_LBPM_HSK_TX_ARX_CAP_LBPM_CNT_Msk 0xF000UL 1920 /* USB32DEV_LNK.LNK_CAP_LBPM_OBSERVE */ 1921 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_10GX1_CAP_LBPM_CNT_Pos 0UL 1922 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_10GX1_CAP_LBPM_CNT_Msk 0x7UL 1923 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_5GX1_CAP_LBPM_CNT_Pos 4UL 1924 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_5GX1_CAP_LBPM_CNT_Msk 0x70UL 1925 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_10GX2_CAP_LBPM_CNT_Pos 8UL 1926 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_10GX2_CAP_LBPM_CNT_Msk 0x700UL 1927 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_5GX2_CAP_LBPM_CNT_Pos 12UL 1928 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_5GX2_CAP_LBPM_CNT_Msk 0x7000UL 1929 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_READY_LBPM_CNT_Pos 16UL 1930 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_RCVD_READY_LBPM_CNT_Msk 0x70000UL 1931 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_SENT_CAP_LBPM_CNT_ARX_Pos 20UL 1932 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_SENT_CAP_LBPM_CNT_ARX_Msk 0x700000UL 1933 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_CAP_LBPM_HSK_DONE_Pos 31UL 1934 #define USB32DEV_LNK_CAP_LBPM_OBSERVE_CAP_LBPM_HSK_DONE_Msk 0x80000000UL 1935 /* USB32DEV_LNK.LNK_READY_LBPM_HSK */ 1936 #define USB32DEV_LNK_READY_LBPM_HSK_RX_RDY_LBPM_CNT_Pos 0UL 1937 #define USB32DEV_LNK_READY_LBPM_HSK_RX_RDY_LBPM_CNT_Msk 0x7UL 1938 #define USB32DEV_LNK_READY_LBPM_HSK_ARX_RDY_LBPM_LIMIT_Pos 4UL 1939 #define USB32DEV_LNK_READY_LBPM_HSK_ARX_RDY_LBPM_LIMIT_Msk 0x70UL 1940 #define USB32DEV_LNK_READY_LBPM_HSK_TX_ARX_RDY_LBPM_CNT_Pos 8UL 1941 #define USB32DEV_LNK_READY_LBPM_HSK_TX_ARX_RDY_LBPM_CNT_Msk 0xF00UL 1942 #define USB32DEV_LNK_READY_LBPM_HSK_ENTRY_TO_TX_DELAY_Pos 16UL 1943 #define USB32DEV_LNK_READY_LBPM_HSK_ENTRY_TO_TX_DELAY_Msk 0xFF0000UL 1944 /* USB32DEV_LNK.LNK_READY_LBPM_OBSERVE */ 1945 #define USB32DEV_LNK_READY_LBPM_OBSERVE_RCVD_RDY_LBPM_CNT_Pos 0UL 1946 #define USB32DEV_LNK_READY_LBPM_OBSERVE_RCVD_RDY_LBPM_CNT_Msk 0x7UL 1947 #define USB32DEV_LNK_READY_LBPM_OBSERVE_SENT_RDY_LBPM_CNT_ARX_Pos 4UL 1948 #define USB32DEV_LNK_READY_LBPM_OBSERVE_SENT_RDY_LBPM_CNT_ARX_Msk 0xF0UL 1949 #define USB32DEV_LNK_READY_LBPM_OBSERVE_RDY_LBPM_HSK_DONE_Pos 31UL 1950 #define USB32DEV_LNK_READY_LBPM_OBSERVE_RDY_LBPM_HSK_DONE_Msk 0x80000000UL 1951 /* USB32DEV_LNK.LNK_RCVD_LBPM_OBSERVE */ 1952 #define USB32DEV_LNK_RCVD_LBPM_OBSERVE_LBPM_Pos 0UL 1953 #define USB32DEV_LNK_RCVD_LBPM_OBSERVE_LBPM_Msk 0xFFUL 1954 /* USB32DEV_LNK.LNK_LTSSM_SCD_LFPS_TIMEOUT */ 1955 #define USB32DEV_LNK_LTSSM_SCD_LFPS_TIMEOUT_TIMEOUT16_Pos 0UL 1956 #define USB32DEV_LNK_LTSSM_SCD_LFPS_TIMEOUT_TIMEOUT16_Msk 0xFFFFUL 1957 /* USB32DEV_LNK.LNK_LTSSM_LBPM_LFPS_TIMEOUT */ 1958 #define USB32DEV_LNK_LTSSM_LBPM_LFPS_TIMEOUT_TIMEOUT24_Pos 0UL 1959 #define USB32DEV_LNK_LTSSM_LBPM_LFPS_TIMEOUT_TIMEOUT24_Msk 0xFFFFFFUL 1960 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_9_TO_12 */ 1961 #define USB32DEV_LNK_COMPLIANCE_PATTERN_9_TO_12_DEEMPH_COEFF_Pos 0UL 1962 #define USB32DEV_LNK_COMPLIANCE_PATTERN_9_TO_12_DEEMPH_COEFF_Msk 0x3FFFFUL 1963 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_13 */ 1964 #define USB32DEV_LNK_COMPLIANCE_PATTERN_13_DEEMPH_COEFF_Pos 0UL 1965 #define USB32DEV_LNK_COMPLIANCE_PATTERN_13_DEEMPH_COEFF_Msk 0x3FFFFUL 1966 #define USB32DEV_LNK_COMPLIANCE_PATTERN_13_GEN2_TXONESZEROS_Pos 18UL 1967 #define USB32DEV_LNK_COMPLIANCE_PATTERN_13_GEN2_TXONESZEROS_Msk 0x40000UL 1968 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_14 */ 1969 #define USB32DEV_LNK_COMPLIANCE_PATTERN_14_DEEMPH_COEFF_Pos 0UL 1970 #define USB32DEV_LNK_COMPLIANCE_PATTERN_14_DEEMPH_COEFF_Msk 0x3FFFFUL 1971 #define USB32DEV_LNK_COMPLIANCE_PATTERN_14_GEN2_TXONESZEROS_Pos 18UL 1972 #define USB32DEV_LNK_COMPLIANCE_PATTERN_14_GEN2_TXONESZEROS_Msk 0x40000UL 1973 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_15 */ 1974 #define USB32DEV_LNK_COMPLIANCE_PATTERN_15_DEEMPH_COEFF_Pos 0UL 1975 #define USB32DEV_LNK_COMPLIANCE_PATTERN_15_DEEMPH_COEFF_Msk 0x3FFFFUL 1976 #define USB32DEV_LNK_COMPLIANCE_PATTERN_15_GEN2_TXONESZEROS_Pos 18UL 1977 #define USB32DEV_LNK_COMPLIANCE_PATTERN_15_GEN2_TXONESZEROS_Msk 0x40000UL 1978 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_16 */ 1979 #define USB32DEV_LNK_COMPLIANCE_PATTERN_16_DEEMPH_COEFF_Pos 0UL 1980 #define USB32DEV_LNK_COMPLIANCE_PATTERN_16_DEEMPH_COEFF_Msk 0x3FFFFUL 1981 #define USB32DEV_LNK_COMPLIANCE_PATTERN_16_GEN2_TXONESZEROS_Pos 18UL 1982 #define USB32DEV_LNK_COMPLIANCE_PATTERN_16_GEN2_TXONESZEROS_Msk 0x40000UL 1983 /* USB32DEV_LNK.LNK_COMPLIANCE_PATTERN_OBSERVE */ 1984 #define USB32DEV_LNK_COMPLIANCE_PATTERN_OBSERVE_CP_OBSERVE_Pos 0UL 1985 #define USB32DEV_LNK_COMPLIANCE_PATTERN_OBSERVE_CP_OBSERVE_Msk 0x3FUL 1986 /* USB32DEV_LNK.LNK_SOFT_ERR_CNT_CONF */ 1987 #define USB32DEV_LNK_SOFT_ERR_CNT_CONF_SOFT_ERR_LFR_OPT_Pos 29UL 1988 #define USB32DEV_LNK_SOFT_ERR_CNT_CONF_SOFT_ERR_LFR_OPT_Msk 0x20000000UL 1989 #define USB32DEV_LNK_SOFT_ERR_CNT_CONF_SOFT_ERR_CNT_RESET_Pos 30UL 1990 #define USB32DEV_LNK_SOFT_ERR_CNT_CONF_SOFT_ERR_CNT_RESET_Msk 0x40000000UL 1991 #define USB32DEV_LNK_SOFT_ERR_CNT_CONF_SOFT_ERR_CNT_EN_Pos 31UL 1992 #define USB32DEV_LNK_SOFT_ERR_CNT_CONF_SOFT_ERR_CNT_EN_Msk 0x80000000UL 1993 /* USB32DEV_LNK.LNK_SOFT_ERR_CNT_OBSERVE */ 1994 #define USB32DEV_LNK_SOFT_ERR_CNT_OBSERVE_SOFT_ERR_CNT_OBSERVE_Pos 0UL 1995 #define USB32DEV_LNK_SOFT_ERR_CNT_OBSERVE_SOFT_ERR_CNT_OBSERVE_Msk 0xFFFFUL 1996 /* USB32DEV_LNK.LNK_LTSSM_STATE_CHG_INTR_CONF */ 1997 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_SS_DISABLE_INTR_Pos 0UL 1998 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_SS_DISABLE_INTR_Msk 0x1UL 1999 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RX_DETECT_RESET_INTR_Pos 1UL 2000 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RX_DETECT_RESET_INTR_Msk 0x2UL 2001 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RX_DETECT_ACTIVE_INTR_Pos 2UL 2002 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RX_DETECT_ACTIVE_INTR_Msk 0x4UL 2003 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RX_DETECT_QUIET_INTR_Pos 3UL 2004 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RX_DETECT_QUIET_INTR_Msk 0x8UL 2005 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_SS_INACTIVE_QUIET_INTR_Pos 4UL 2006 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_SS_INACTIVE_QUIET_INTR_Msk 0x10UL 2007 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_SS_INACTIVE_DISCONNECT_DETECT_INTR_Pos 5UL 2008 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_SS_INACTIVE_DISCONNECT_DETECT_INTR_Msk 0x20UL 2009 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_HOTRESET_ACTIVE_INTR_Pos 6UL 2010 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_HOTRESET_ACTIVE_INTR_Msk 0x40UL 2011 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_HOTRESET_EXIT_INTR_Pos 7UL 2012 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_HOTRESET_EXIT_INTR_Msk 0x80UL 2013 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_LFPS_INTR_Pos 8UL 2014 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_LFPS_INTR_Msk 0x100UL 2015 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_RXEQ_INTR_Pos 9UL 2016 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_RXEQ_INTR_Msk 0x200UL 2017 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_ACTIVE_INTR_Pos 10UL 2018 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_ACTIVE_INTR_Msk 0x400UL 2019 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_CONFIGURATION_INTR_Pos 11UL 2020 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_CONFIGURATION_INTR_Msk 0x800UL 2021 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_IDLE_INTR_Pos 12UL 2022 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_IDLE_INTR_Msk 0x1000UL 2023 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_LFPSPLUS_INTR_Pos 13UL 2024 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_LFPSPLUS_INTR_Msk 0x2000UL 2025 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_PORT_MATCH_INTR_Pos 14UL 2026 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_PORT_MATCH_INTR_Msk 0x4000UL 2027 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_PORT_CONFIG_INTR_Pos 15UL 2028 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_POLLING_PORT_CONFIG_INTR_Msk 0x8000UL 2029 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_U0_INTR_Pos 16UL 2030 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_U0_INTR_Msk 0x10000UL 2031 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_U1_INTR_Pos 17UL 2032 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_U1_INTR_Msk 0x20000UL 2033 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_U2_INTR_Pos 18UL 2034 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_U2_INTR_Msk 0x40000UL 2035 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_U3_INTR_Pos 19UL 2036 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_U3_INTR_Msk 0x80000UL 2037 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_LOOPBACK_ACTIVE_INTR_Pos 20UL 2038 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_LOOPBACK_ACTIVE_INTR_Msk 0x100000UL 2039 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_LOOPBACK_EXIT_INTR_Pos 21UL 2040 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_LOOPBACK_EXIT_INTR_Msk 0x200000UL 2041 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_COMPLIANCE_INTR_Pos 22UL 2042 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_COMPLIANCE_INTR_Msk 0x400000UL 2043 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RECOVERY_ACTIVE_INTR_Pos 23UL 2044 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RECOVERY_ACTIVE_INTR_Msk 0x800000UL 2045 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RECOVERY_CONFIGURATION_INTR_Pos 24UL 2046 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RECOVERY_CONFIGURATION_INTR_Msk 0x1000000UL 2047 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RECOVERY_IDLE_INTR_Pos 25UL 2048 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_RECOVERY_IDLE_INTR_Msk 0x2000000UL 2049 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_ILLEGAL_STATE_INTR_Pos 26UL 2050 #define USB32DEV_LNK_LTSSM_STATE_CHG_INTR_CONF_ILLEGAL_STATE_INTR_Msk 0x4000000UL 2051 /* USB32DEV_LNK.LNK_DEBUG_RSVD */ 2052 #define USB32DEV_LNK_DEBUG_RSVD_DEBUG_SIG_SEL_Pos 0UL 2053 #define USB32DEV_LNK_DEBUG_RSVD_DEBUG_SIG_SEL_Msk 0xFFFFUL 2054 #define USB32DEV_LNK_DEBUG_RSVD_HS_DDFT_SEL_Pos 16UL 2055 #define USB32DEV_LNK_DEBUG_RSVD_HS_DDFT_SEL_Msk 0x1F0000UL 2056 #define USB32DEV_LNK_DEBUG_RSVD_HS_DDFT_NOT_EXTD_Pos 21UL 2057 #define USB32DEV_LNK_DEBUG_RSVD_HS_DDFT_NOT_EXTD_Msk 0x200000UL 2058 #define USB32DEV_LNK_DEBUG_RSVD_RSVD_Pos 22UL 2059 #define USB32DEV_LNK_DEBUG_RSVD_RSVD_Msk 0x7FC00000UL 2060 #define USB32DEV_LNK_DEBUG_RSVD_FORCE_RATE_CONFIG_TO_GEN1_Pos 31UL 2061 #define USB32DEV_LNK_DEBUG_RSVD_FORCE_RATE_CONFIG_TO_GEN1_Msk 0x80000000UL 2062 /* USB32DEV_LNK.LNK_TX_TS1_HOLDOFF_TIMEOUT */ 2063 #define USB32DEV_LNK_TX_TS1_HOLDOFF_TIMEOUT_TX_TS1_HOLDOFF_TIMEOUT_Pos 0UL 2064 #define USB32DEV_LNK_TX_TS1_HOLDOFF_TIMEOUT_TX_TS1_HOLDOFF_TIMEOUT_Msk 0xFFFFUL 2065 /* USB32DEV_LNK.LNK_MISC_CONF */ 2066 #define USB32DEV_LNK_MISC_CONF_REPLACED_SKP_SYMB_Pos 0UL 2067 #define USB32DEV_LNK_MISC_CONF_REPLACED_SKP_SYMB_Msk 0xFFUL 2068 #define USB32DEV_LNK_MISC_CONF_TX_TS2_CONF_Pos 8UL 2069 #define USB32DEV_LNK_MISC_CONF_TX_TS2_CONF_Msk 0x300UL 2070 #define USB32DEV_LNK_MISC_CONF_INVALID_LFPS_NOT_RST_TIMER_EN_Pos 10UL 2071 #define USB32DEV_LNK_MISC_CONF_INVALID_LFPS_NOT_RST_TIMER_EN_Msk 0x400UL 2072 #define USB32DEV_LNK_MISC_CONF_GEN1X2_SKP_REMOVAL_EN_Pos 11UL 2073 #define USB32DEV_LNK_MISC_CONF_GEN1X2_SKP_REMOVAL_EN_Msk 0x800UL 2074 #define USB32DEV_LNK_MISC_CONF_TX_DL_SET_ENABLE_Pos 12UL 2075 #define USB32DEV_LNK_MISC_CONF_TX_DL_SET_ENABLE_Msk 0x1000UL 2076 #define USB32DEV_LNK_MISC_CONF_GEN1_GT_4CLK_SKEW_DET_EN_Pos 13UL 2077 #define USB32DEV_LNK_MISC_CONF_GEN1_GT_4CLK_SKEW_DET_EN_Msk 0x2000UL 2078 #define USB32DEV_LNK_MISC_CONF_GEN2_GT_4CLK_SKEW_DET_EN_Pos 14UL 2079 #define USB32DEV_LNK_MISC_CONF_GEN2_GT_4CLK_SKEW_DET_EN_Msk 0x4000UL 2080 #define USB32DEV_LNK_MISC_CONF_GEN1_SKEW_EVAL_EN_Pos 15UL 2081 #define USB32DEV_LNK_MISC_CONF_GEN1_SKEW_EVAL_EN_Msk 0x8000UL 2082 #define USB32DEV_LNK_MISC_CONF_GEN2_SKEW_EVAL_EN_Pos 16UL 2083 #define USB32DEV_LNK_MISC_CONF_GEN2_SKEW_EVAL_EN_Msk 0x10000UL 2084 #define USB32DEV_LNK_MISC_CONF_GEN2_SKP_REMOVAL_OPT_Pos 17UL 2085 #define USB32DEV_LNK_MISC_CONF_GEN2_SKP_REMOVAL_OPT_Msk 0x20000UL 2086 #define USB32DEV_LNK_MISC_CONF_GEN2_ALGN_FSM_RST_OPT_Pos 18UL 2087 #define USB32DEV_LNK_MISC_CONF_GEN2_ALGN_FSM_RST_OPT_Msk 0x40000UL 2088 #define USB32DEV_LNK_MISC_CONF_PENDING_LXU_BEFORE_LGOOD_BUG_FIX_EN_Pos 19UL 2089 #define USB32DEV_LNK_MISC_CONF_PENDING_LXU_BEFORE_LGOOD_BUG_FIX_EN_Msk 0x80000UL 2090 #define USB32DEV_LNK_MISC_CONF_RX_DESKEW_CLK_GT_EN_Pos 20UL 2091 #define USB32DEV_LNK_MISC_CONF_RX_DESKEW_CLK_GT_EN_Msk 0x100000UL 2092 #define USB32DEV_LNK_MISC_CONF_GEN2X2_DESKEW_ON_TS1_Pos 21UL 2093 #define USB32DEV_LNK_MISC_CONF_GEN2X2_DESKEW_ON_TS1_Msk 0x200000UL 2094 #define USB32DEV_LNK_MISC_CONF_TX_IDLE_CONF_Pos 22UL 2095 #define USB32DEV_LNK_MISC_CONF_TX_IDLE_CONF_Msk 0xC00000UL 2096 #define USB32DEV_LNK_MISC_CONF_RX_DESKEW_RST_IF_RECOV_Pos 30UL 2097 #define USB32DEV_LNK_MISC_CONF_RX_DESKEW_RST_IF_RECOV_Msk 0x40000000UL 2098 #define USB32DEV_LNK_MISC_CONF_RX_DESKEW_EN_Pos 31UL 2099 #define USB32DEV_LNK_MISC_CONF_RX_DESKEW_EN_Msk 0x80000000UL 2100 /* USB32DEV_LNK.LNK_MISC_OBSERVE */ 2101 #define USB32DEV_LNK_MISC_OBSERVE_LOCKED_SKEW_VAL_Pos 0UL 2102 #define USB32DEV_LNK_MISC_OBSERVE_LOCKED_SKEW_VAL_Msk 0x1FUL 2103 /* USB32DEV_LNK.LNK_LTSSM_SUBSTATE_OBSERVE */ 2104 #define USB32DEV_LNK_LTSSM_SUBSTATE_OBSERVE_LTSSM_SUBSTATE_OBSERVE_Pos 0UL 2105 #define USB32DEV_LNK_LTSSM_SUBSTATE_OBSERVE_LTSSM_SUBSTATE_OBSERVE_Msk 0xFFFFFFFFUL 2106 /* USB32DEV_LNK.LNK_RX_TYPE1_HEADER_BUFFER */ 2107 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_HEADER_Pos 0UL 2108 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_HEADER_Msk 0xFFFFFFFFUL 2109 /* USB32DEV_LNK.LNK_RX_TYPE1_HEADER_BUFFER_STATE_0 */ 2110 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE0_Pos 0UL 2111 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE0_Msk 0xFUL 2112 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_VALID0_Pos 4UL 2113 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_VALID0_Msk 0x10UL 2114 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_RCVD0_Pos 5UL 2115 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_RCVD0_Msk 0x20UL 2116 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE1_Pos 8UL 2117 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE1_Msk 0xF00UL 2118 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_VALID1_Pos 12UL 2119 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_VALID1_Msk 0x1000UL 2120 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_RCVD1_Pos 13UL 2121 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_RCVD1_Msk 0x2000UL 2122 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE2_Pos 16UL 2123 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE2_Msk 0xF0000UL 2124 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_VALID2_Pos 20UL 2125 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_VALID2_Msk 0x100000UL 2126 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_RCVD2_Pos 21UL 2127 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_RCVD2_Msk 0x200000UL 2128 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE3_Pos 24UL 2129 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE3_Msk 0xF000000UL 2130 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_VALID3_Pos 28UL 2131 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_VALID3_Msk 0x10000000UL 2132 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_RCVD3_Pos 29UL 2133 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_0_RCVD3_Msk 0x20000000UL 2134 /* USB32DEV_LNK.LNK_RX_TYPE1_HEADER_BUFFER_STATE_1 */ 2135 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE4_Pos 0UL 2136 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE4_Msk 0xFUL 2137 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_VALID4_Pos 4UL 2138 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_VALID4_Msk 0x10UL 2139 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_RCVD4_Pos 5UL 2140 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_RCVD4_Msk 0x20UL 2141 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE5_Pos 8UL 2142 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE5_Msk 0xF00UL 2143 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_VALID5_Pos 12UL 2144 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_VALID5_Msk 0x1000UL 2145 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_RCVD5_Pos 13UL 2146 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_RCVD5_Msk 0x2000UL 2147 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE6_Pos 16UL 2148 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE6_Msk 0xF0000UL 2149 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_VALID6_Pos 20UL 2150 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_VALID6_Msk 0x100000UL 2151 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_RCVD6_Pos 21UL 2152 #define USB32DEV_LNK_RX_TYPE1_HEADER_BUFFER_STATE_1_RCVD6_Msk 0x200000UL 2153 /* USB32DEV_LNK.LNK_RX_TYPE2_HEADER_BUFFER */ 2154 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_HEADER_Pos 0UL 2155 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_HEADER_Msk 0xFFFFFFFFUL 2156 /* USB32DEV_LNK.LNK_RX_TYPE2_HEADER_BUFFER_STATE_0 */ 2157 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE0_Pos 0UL 2158 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE0_Msk 0xFUL 2159 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_VALID0_Pos 4UL 2160 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_VALID0_Msk 0x10UL 2161 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_RCVD0_Pos 5UL 2162 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_RCVD0_Msk 0x20UL 2163 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE1_Pos 8UL 2164 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE1_Msk 0xF00UL 2165 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_VALID1_Pos 12UL 2166 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_VALID1_Msk 0x1000UL 2167 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_RCVD1_Pos 13UL 2168 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_RCVD1_Msk 0x2000UL 2169 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE2_Pos 16UL 2170 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE2_Msk 0xF0000UL 2171 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_VALID2_Pos 20UL 2172 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_VALID2_Msk 0x100000UL 2173 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_RCVD2_Pos 21UL 2174 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_RCVD2_Msk 0x200000UL 2175 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE3_Pos 24UL 2176 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE3_Msk 0xF000000UL 2177 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_VALID3_Pos 28UL 2178 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_VALID3_Msk 0x10000000UL 2179 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_RCVD3_Pos 29UL 2180 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_0_RCVD3_Msk 0x20000000UL 2181 /* USB32DEV_LNK.LNK_RX_TYPE2_HEADER_BUFFER_STATE_1 */ 2182 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE4_Pos 0UL 2183 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE4_Msk 0xFUL 2184 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_VALID4_Pos 4UL 2185 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_VALID4_Msk 0x10UL 2186 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_RCVD4_Pos 5UL 2187 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_RCVD4_Msk 0x20UL 2188 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE5_Pos 8UL 2189 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE5_Msk 0xF00UL 2190 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_VALID5_Pos 12UL 2191 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_VALID5_Msk 0x1000UL 2192 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_RCVD5_Pos 13UL 2193 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_RCVD5_Msk 0x2000UL 2194 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE6_Pos 16UL 2195 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE6_Msk 0xF0000UL 2196 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_VALID6_Pos 20UL 2197 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_VALID6_Msk 0x100000UL 2198 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_RCVD6_Pos 21UL 2199 #define USB32DEV_LNK_RX_TYPE2_HEADER_BUFFER_STATE_1_RCVD6_Msk 0x200000UL 2200 /* USB32DEV_LNK.LNK_TX_TYPE1_HEADER_BUFFER */ 2201 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_HEADER_Pos 0UL 2202 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_HEADER_Msk 0xFFFFFFFFUL 2203 /* USB32DEV_LNK.LNK_TX_TYPE1_HEADER_BUFFER_STATE_0 */ 2204 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE0_Pos 0UL 2205 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE0_Msk 0xFUL 2206 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_VALID0_Pos 4UL 2207 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_VALID0_Msk 0x10UL 2208 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SENT0_Pos 5UL 2209 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SENT0_Msk 0x20UL 2210 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE1_Pos 8UL 2211 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE1_Msk 0xF00UL 2212 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_VALID1_Pos 12UL 2213 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_VALID1_Msk 0x1000UL 2214 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SENT1_Pos 13UL 2215 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SENT1_Msk 0x2000UL 2216 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE2_Pos 16UL 2217 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE2_Msk 0xF0000UL 2218 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_VALID2_Pos 20UL 2219 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_VALID2_Msk 0x100000UL 2220 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SENT2_Pos 21UL 2221 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SENT2_Msk 0x200000UL 2222 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE3_Pos 24UL 2223 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SEQUENCE3_Msk 0xF000000UL 2224 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_VALID3_Pos 28UL 2225 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_VALID3_Msk 0x10000000UL 2226 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SENT3_Pos 29UL 2227 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_0_SENT3_Msk 0x20000000UL 2228 /* USB32DEV_LNK.LNK_TX_TYPE1_HEADER_BUFFER_STATE_1 */ 2229 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE4_Pos 0UL 2230 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE4_Msk 0xFUL 2231 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_VALID4_Pos 4UL 2232 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_VALID4_Msk 0x10UL 2233 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SENT4_Pos 5UL 2234 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SENT4_Msk 0x20UL 2235 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE5_Pos 8UL 2236 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE5_Msk 0xF00UL 2237 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_VALID5_Pos 12UL 2238 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_VALID5_Msk 0x1000UL 2239 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SENT5_Pos 13UL 2240 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SENT5_Msk 0x2000UL 2241 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE6_Pos 16UL 2242 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SEQUENCE6_Msk 0xF0000UL 2243 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_VALID6_Pos 20UL 2244 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_VALID6_Msk 0x100000UL 2245 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SENT6_Pos 21UL 2246 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_SENT6_Msk 0x200000UL 2247 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_REMOTE_CREDITS_Pos 29UL 2248 #define USB32DEV_LNK_TX_TYPE1_HEADER_BUFFER_STATE_1_REMOTE_CREDITS_Msk 0xE0000000UL 2249 /* USB32DEV_LNK.LNK_TX_TYPE2_HEADER_BUFFER */ 2250 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_HEADER_Pos 0UL 2251 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_HEADER_Msk 0xFFFFFFFFUL 2252 /* USB32DEV_LNK.LNK_TX_TYPE2_HEADER_BUFFER_STATE_0 */ 2253 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE0_Pos 0UL 2254 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE0_Msk 0xFUL 2255 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_VALID0_Pos 4UL 2256 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_VALID0_Msk 0x10UL 2257 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SENT0_Pos 5UL 2258 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SENT0_Msk 0x20UL 2259 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE1_Pos 8UL 2260 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE1_Msk 0xF00UL 2261 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_VALID1_Pos 12UL 2262 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_VALID1_Msk 0x1000UL 2263 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SENT1_Pos 13UL 2264 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SENT1_Msk 0x2000UL 2265 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE2_Pos 16UL 2266 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE2_Msk 0xF0000UL 2267 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_VALID2_Pos 20UL 2268 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_VALID2_Msk 0x100000UL 2269 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SENT2_Pos 21UL 2270 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SENT2_Msk 0x200000UL 2271 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE3_Pos 24UL 2272 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SEQUENCE3_Msk 0xF000000UL 2273 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_VALID3_Pos 28UL 2274 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_VALID3_Msk 0x10000000UL 2275 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SENT3_Pos 29UL 2276 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_0_SENT3_Msk 0x20000000UL 2277 /* USB32DEV_LNK.LNK_TX_TYPE2_HEADER_BUFFER_STATE_1 */ 2278 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE4_Pos 0UL 2279 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE4_Msk 0xFUL 2280 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_VALID4_Pos 4UL 2281 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_VALID4_Msk 0x10UL 2282 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SENT4_Pos 5UL 2283 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SENT4_Msk 0x20UL 2284 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE5_Pos 8UL 2285 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE5_Msk 0xF00UL 2286 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_VALID5_Pos 12UL 2287 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_VALID5_Msk 0x1000UL 2288 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SENT5_Pos 13UL 2289 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SENT5_Msk 0x2000UL 2290 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE6_Pos 16UL 2291 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SEQUENCE6_Msk 0xF0000UL 2292 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_VALID6_Pos 20UL 2293 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_VALID6_Msk 0x100000UL 2294 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SENT6_Pos 21UL 2295 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_SENT6_Msk 0x200000UL 2296 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_REMOTE_CREDITS_Pos 29UL 2297 #define USB32DEV_LNK_TX_TYPE2_HEADER_BUFFER_STATE_1_REMOTE_CREDITS_Msk 0xE0000000UL 2298 2299 2300 /* USB32DEV_PROT.PROT_CS */ 2301 #define USB32DEV_PROT_CS_DEVICEADDR_Pos 0UL 2302 #define USB32DEV_PROT_CS_DEVICEADDR_Msk 0x7FUL 2303 #define USB32DEV_PROT_CS_DISABLE_INGRS_SEQ_MATCH_Pos 7UL 2304 #define USB32DEV_PROT_CS_DISABLE_INGRS_SEQ_MATCH_Msk 0x80UL 2305 #define USB32DEV_PROT_CS_DISABLE_EGRS_SEQ_MATCH_Pos 8UL 2306 #define USB32DEV_PROT_CS_DISABLE_EGRS_SEQ_MATCH_Msk 0x100UL 2307 #define USB32DEV_PROT_CS_DISABLE_HE_DETECTION_Pos 9UL 2308 #define USB32DEV_PROT_CS_DISABLE_HE_DETECTION_Msk 0x200UL 2309 #define USB32DEV_PROT_CS_SPARE_CS_Pos 10UL 2310 #define USB32DEV_PROT_CS_SPARE_CS_Msk 0x1C00UL 2311 #define USB32DEV_PROT_CS_EN_STATUS_CONTROL_Pos 13UL 2312 #define USB32DEV_PROT_CS_EN_STATUS_CONTROL_Msk 0x2000UL 2313 #define USB32DEV_PROT_CS_STATUS_RESPONSE_Pos 14UL 2314 #define USB32DEV_PROT_CS_STATUS_RESPONSE_Msk 0x4000UL 2315 #define USB32DEV_PROT_CS_STATUS_CLR_BUSY_Pos 15UL 2316 #define USB32DEV_PROT_CS_STATUS_CLR_BUSY_Msk 0x8000UL 2317 #define USB32DEV_PROT_CS_SETUP_CLR_BUSY_Pos 16UL 2318 #define USB32DEV_PROT_CS_SETUP_CLR_BUSY_Msk 0x10000UL 2319 #define USB32DEV_PROT_CS_NRDY_ALL_Pos 17UL 2320 #define USB32DEV_PROT_CS_NRDY_ALL_Msk 0x20000UL 2321 #define USB32DEV_PROT_CS_TP_THRESHOLD_Pos 18UL 2322 #define USB32DEV_PROT_CS_TP_THRESHOLD_Msk 0xFC0000UL 2323 #define USB32DEV_PROT_CS_PROT_HOST_RESET_RESP_Pos 24UL 2324 #define USB32DEV_PROT_CS_PROT_HOST_RESET_RESP_Msk 0x1000000UL 2325 #define USB32DEV_PROT_CS_SEQ_NUM_CONFIG_Pos 25UL 2326 #define USB32DEV_PROT_CS_SEQ_NUM_CONFIG_Msk 0x2000000UL 2327 #define USB32DEV_PROT_CS_DISABLE_IDLE_DET_Pos 26UL 2328 #define USB32DEV_PROT_CS_DISABLE_IDLE_DET_Msk 0x4000000UL 2329 #define USB32DEV_PROT_CS_MULT_TIMER_Pos 27UL 2330 #define USB32DEV_PROT_CS_MULT_TIMER_Msk 0xF8000000UL 2331 /* USB32DEV_PROT.PROT_INTR */ 2332 #define USB32DEV_PROT_INTR_LMP_RCV_EV_Pos 0UL 2333 #define USB32DEV_PROT_INTR_LMP_RCV_EV_Msk 0x1UL 2334 #define USB32DEV_PROT_INTR_LMP_UNKNOWN_EV_Pos 1UL 2335 #define USB32DEV_PROT_INTR_LMP_UNKNOWN_EV_Msk 0x2UL 2336 #define USB32DEV_PROT_INTR_LMP_PORT_CAP_EV_Pos 2UL 2337 #define USB32DEV_PROT_INTR_LMP_PORT_CAP_EV_Msk 0x4UL 2338 #define USB32DEV_PROT_INTR_LMP_PORT_CFG_EV_Pos 3UL 2339 #define USB32DEV_PROT_INTR_LMP_PORT_CFG_EV_Msk 0x8UL 2340 #define USB32DEV_PROT_INTR_TIMEOUT_PORT_CAP_EV_Pos 4UL 2341 #define USB32DEV_PROT_INTR_TIMEOUT_PORT_CAP_EV_Msk 0x10UL 2342 #define USB32DEV_PROT_INTR_TIMEOUT_PORT_CFG_EV_Pos 5UL 2343 #define USB32DEV_PROT_INTR_TIMEOUT_PORT_CFG_EV_Msk 0x20UL 2344 #define USB32DEV_PROT_INTR_TIMEOUT_PING_EV_Pos 6UL 2345 #define USB32DEV_PROT_INTR_TIMEOUT_PING_EV_Msk 0x40UL 2346 #define USB32DEV_PROT_INTR_ITP_EV_Pos 8UL 2347 #define USB32DEV_PROT_INTR_ITP_EV_Msk 0x100UL 2348 #define USB32DEV_PROT_INTR_SUTOK_EV_Pos 9UL 2349 #define USB32DEV_PROT_INTR_SUTOK_EV_Msk 0x200UL 2350 #define USB32DEV_PROT_INTR_HOST_ERR_EV_Pos 10UL 2351 #define USB32DEV_PROT_INTR_HOST_ERR_EV_Msk 0x400UL 2352 #define USB32DEV_PROT_INTR_STATUS_STAGE_Pos 11UL 2353 #define USB32DEV_PROT_INTR_STATUS_STAGE_Msk 0x800UL 2354 #define USB32DEV_PROT_INTR_LMP_INVALID_PORT_CAP_EV_Pos 12UL 2355 #define USB32DEV_PROT_INTR_LMP_INVALID_PORT_CAP_EV_Msk 0x1000UL 2356 #define USB32DEV_PROT_INTR_LMP_INVALID_PORT_CFG_EV_Pos 13UL 2357 #define USB32DEV_PROT_INTR_LMP_INVALID_PORT_CFG_EV_Msk 0x2000UL 2358 #define USB32DEV_PROT_INTR_EP0_STALLED_EV_Pos 14UL 2359 #define USB32DEV_PROT_INTR_EP0_STALLED_EV_Msk 0x4000UL 2360 #define USB32DEV_PROT_INTR_SET_ADDR0_EV_Pos 15UL 2361 #define USB32DEV_PROT_INTR_SET_ADDR0_EV_Msk 0x8000UL 2362 #define USB32DEV_PROT_INTR_LDM_TX_Pos 16UL 2363 #define USB32DEV_PROT_INTR_LDM_TX_Msk 0x10000UL 2364 #define USB32DEV_PROT_INTR_LDM_DL_TX_Pos 17UL 2365 #define USB32DEV_PROT_INTR_LDM_DL_TX_Msk 0x20000UL 2366 #define USB32DEV_PROT_INTR_LDM_RX_Pos 18UL 2367 #define USB32DEV_PROT_INTR_LDM_RX_Msk 0x40000UL 2368 #define USB32DEV_PROT_INTR_LDM_DL_RX_Pos 19UL 2369 #define USB32DEV_PROT_INTR_LDM_DL_RX_Msk 0x80000UL 2370 #define USB32DEV_PROT_INTR_LDM_RESP_TIMEOUT_1_Pos 20UL 2371 #define USB32DEV_PROT_INTR_LDM_RESP_TIMEOUT_1_Msk 0x100000UL 2372 #define USB32DEV_PROT_INTR_LDM_RESP_TIMEOUT_2_Pos 21UL 2373 #define USB32DEV_PROT_INTR_LDM_RESP_TIMEOUT_2_Msk 0x200000UL 2374 #define USB32DEV_PROT_INTR_LDM_RESP_TIMEOUT_3_Pos 22UL 2375 #define USB32DEV_PROT_INTR_LDM_RESP_TIMEOUT_3_Msk 0x400000UL 2376 #define USB32DEV_PROT_INTR_SET_ADDR_Pos 23UL 2377 #define USB32DEV_PROT_INTR_SET_ADDR_Msk 0x800000UL 2378 #define USB32DEV_PROT_INTR_DEFERRED_SET_Pos 24UL 2379 #define USB32DEV_PROT_INTR_DEFERRED_SET_Msk 0x1000000UL 2380 #define USB32DEV_PROT_INTR_DEFERRED_CLEAR_Pos 25UL 2381 #define USB32DEV_PROT_INTR_DEFERRED_CLEAR_Msk 0x2000000UL 2382 #define USB32DEV_PROT_INTR_LDM_STATE_CHANGE_Pos 26UL 2383 #define USB32DEV_PROT_INTR_LDM_STATE_CHANGE_Msk 0x4000000UL 2384 #define USB32DEV_PROT_INTR_T1_SCH_FULL_Pos 27UL 2385 #define USB32DEV_PROT_INTR_T1_SCH_FULL_Msk 0x8000000UL 2386 #define USB32DEV_PROT_INTR_T2_SCH_FULL_Pos 28UL 2387 #define USB32DEV_PROT_INTR_T2_SCH_FULL_Msk 0x10000000UL 2388 /* USB32DEV_PROT.PROT_INTR_SET */ 2389 #define USB32DEV_PROT_INTR_SET_LMP_RCV_EV_Pos 0UL 2390 #define USB32DEV_PROT_INTR_SET_LMP_RCV_EV_Msk 0x1UL 2391 #define USB32DEV_PROT_INTR_SET_LMP_UNKNOWN_EV_Pos 1UL 2392 #define USB32DEV_PROT_INTR_SET_LMP_UNKNOWN_EV_Msk 0x2UL 2393 #define USB32DEV_PROT_INTR_SET_LMP_PORT_CAP_EV_Pos 2UL 2394 #define USB32DEV_PROT_INTR_SET_LMP_PORT_CAP_EV_Msk 0x4UL 2395 #define USB32DEV_PROT_INTR_SET_LMP_PORT_CFG_EV_Pos 3UL 2396 #define USB32DEV_PROT_INTR_SET_LMP_PORT_CFG_EV_Msk 0x8UL 2397 #define USB32DEV_PROT_INTR_SET_TIMEOUT_PORT_CAP_EV_Pos 4UL 2398 #define USB32DEV_PROT_INTR_SET_TIMEOUT_PORT_CAP_EV_Msk 0x10UL 2399 #define USB32DEV_PROT_INTR_SET_TIMEOUT_PORT_CFG_EV_Pos 5UL 2400 #define USB32DEV_PROT_INTR_SET_TIMEOUT_PORT_CFG_EV_Msk 0x20UL 2401 #define USB32DEV_PROT_INTR_SET_TIMEOUT_PING_EV_Pos 6UL 2402 #define USB32DEV_PROT_INTR_SET_TIMEOUT_PING_EV_Msk 0x40UL 2403 #define USB32DEV_PROT_INTR_SET_ITP_EV_Pos 8UL 2404 #define USB32DEV_PROT_INTR_SET_ITP_EV_Msk 0x100UL 2405 #define USB32DEV_PROT_INTR_SET_SUTOK_EV_Pos 9UL 2406 #define USB32DEV_PROT_INTR_SET_SUTOK_EV_Msk 0x200UL 2407 #define USB32DEV_PROT_INTR_SET_HOST_ERR_EV_Pos 10UL 2408 #define USB32DEV_PROT_INTR_SET_HOST_ERR_EV_Msk 0x400UL 2409 #define USB32DEV_PROT_INTR_SET_STATUS_STAGE_Pos 11UL 2410 #define USB32DEV_PROT_INTR_SET_STATUS_STAGE_Msk 0x800UL 2411 #define USB32DEV_PROT_INTR_SET_LMP_INVALID_PORT_CAP_EV_Pos 12UL 2412 #define USB32DEV_PROT_INTR_SET_LMP_INVALID_PORT_CAP_EV_Msk 0x1000UL 2413 #define USB32DEV_PROT_INTR_SET_LMP_INVALID_PORT_CFG_EV_Pos 13UL 2414 #define USB32DEV_PROT_INTR_SET_LMP_INVALID_PORT_CFG_EV_Msk 0x2000UL 2415 #define USB32DEV_PROT_INTR_SET_EP0_STALLED_EV_Pos 14UL 2416 #define USB32DEV_PROT_INTR_SET_EP0_STALLED_EV_Msk 0x4000UL 2417 #define USB32DEV_PROT_INTR_SET_SET_ADDR0_EV_Pos 15UL 2418 #define USB32DEV_PROT_INTR_SET_SET_ADDR0_EV_Msk 0x8000UL 2419 #define USB32DEV_PROT_INTR_SET_LDM_TX_Pos 16UL 2420 #define USB32DEV_PROT_INTR_SET_LDM_TX_Msk 0x10000UL 2421 #define USB32DEV_PROT_INTR_SET_LDM_DL_TX_Pos 17UL 2422 #define USB32DEV_PROT_INTR_SET_LDM_DL_TX_Msk 0x20000UL 2423 #define USB32DEV_PROT_INTR_SET_LDM_RX_Pos 18UL 2424 #define USB32DEV_PROT_INTR_SET_LDM_RX_Msk 0x40000UL 2425 #define USB32DEV_PROT_INTR_SET_LDM_DL_RX_Pos 19UL 2426 #define USB32DEV_PROT_INTR_SET_LDM_DL_RX_Msk 0x80000UL 2427 #define USB32DEV_PROT_INTR_SET_RESP_TIMEOUT_1_Pos 20UL 2428 #define USB32DEV_PROT_INTR_SET_RESP_TIMEOUT_1_Msk 0x100000UL 2429 #define USB32DEV_PROT_INTR_SET_RESP_TIMEOUT_2_Pos 21UL 2430 #define USB32DEV_PROT_INTR_SET_RESP_TIMEOUT_2_Msk 0x200000UL 2431 #define USB32DEV_PROT_INTR_SET_RESP_TIMEOUT_3_Pos 22UL 2432 #define USB32DEV_PROT_INTR_SET_RESP_TIMEOUT_3_Msk 0x400000UL 2433 #define USB32DEV_PROT_INTR_SET_SET_ADDR_Pos 23UL 2434 #define USB32DEV_PROT_INTR_SET_SET_ADDR_Msk 0x800000UL 2435 #define USB32DEV_PROT_INTR_SET_DEFERRED_SET_Pos 24UL 2436 #define USB32DEV_PROT_INTR_SET_DEFERRED_SET_Msk 0x1000000UL 2437 #define USB32DEV_PROT_INTR_SET_DEFERRED_CLEAR_Pos 25UL 2438 #define USB32DEV_PROT_INTR_SET_DEFERRED_CLEAR_Msk 0x2000000UL 2439 #define USB32DEV_PROT_INTR_SET_LDM_STATE_CHANGE_Pos 26UL 2440 #define USB32DEV_PROT_INTR_SET_LDM_STATE_CHANGE_Msk 0x4000000UL 2441 #define USB32DEV_PROT_INTR_SET_T1_SCH_FULL_Pos 27UL 2442 #define USB32DEV_PROT_INTR_SET_T1_SCH_FULL_Msk 0x8000000UL 2443 #define USB32DEV_PROT_INTR_SET_T2_SCH_FULL_Pos 28UL 2444 #define USB32DEV_PROT_INTR_SET_T2_SCH_FULL_Msk 0x10000000UL 2445 /* USB32DEV_PROT.PROT_INTR_MASK */ 2446 #define USB32DEV_PROT_INTR_MASK_LMP_RCV_MASK_Pos 0UL 2447 #define USB32DEV_PROT_INTR_MASK_LMP_RCV_MASK_Msk 0x1UL 2448 #define USB32DEV_PROT_INTR_MASK_LMP_UNKNOWN_MASK_Pos 1UL 2449 #define USB32DEV_PROT_INTR_MASK_LMP_UNKNOWN_MASK_Msk 0x2UL 2450 #define USB32DEV_PROT_INTR_MASK_LMP_PORT_CAP_MASK_Pos 2UL 2451 #define USB32DEV_PROT_INTR_MASK_LMP_PORT_CAP_MASK_Msk 0x4UL 2452 #define USB32DEV_PROT_INTR_MASK_LMP_PORT_CFG_MASK_Pos 3UL 2453 #define USB32DEV_PROT_INTR_MASK_LMP_PORT_CFG_MASK_Msk 0x8UL 2454 #define USB32DEV_PROT_INTR_MASK_TIMEOUT_PORT_CAP_MASK_Pos 4UL 2455 #define USB32DEV_PROT_INTR_MASK_TIMEOUT_PORT_CAP_MASK_Msk 0x10UL 2456 #define USB32DEV_PROT_INTR_MASK_TIMEOUT_PORT_CFG_MASK_Pos 5UL 2457 #define USB32DEV_PROT_INTR_MASK_TIMEOUT_PORT_CFG_MASK_Msk 0x20UL 2458 #define USB32DEV_PROT_INTR_MASK_TIMEOUT_PING_MASK_Pos 6UL 2459 #define USB32DEV_PROT_INTR_MASK_TIMEOUT_PING_MASK_Msk 0x40UL 2460 #define USB32DEV_PROT_INTR_MASK_ITP_MASK_Pos 8UL 2461 #define USB32DEV_PROT_INTR_MASK_ITP_MASK_Msk 0x100UL 2462 #define USB32DEV_PROT_INTR_MASK_SUTOK_MASK_Pos 9UL 2463 #define USB32DEV_PROT_INTR_MASK_SUTOK_MASK_Msk 0x200UL 2464 #define USB32DEV_PROT_INTR_MASK_HOST_ERR_MASK_Pos 10UL 2465 #define USB32DEV_PROT_INTR_MASK_HOST_ERR_MASK_Msk 0x400UL 2466 #define USB32DEV_PROT_INTR_MASK_STATUS_STAGE_MASK_Pos 11UL 2467 #define USB32DEV_PROT_INTR_MASK_STATUS_STAGE_MASK_Msk 0x800UL 2468 #define USB32DEV_PROT_INTR_MASK_LMP_INVALID_PORT_CAP_MASK_Pos 12UL 2469 #define USB32DEV_PROT_INTR_MASK_LMP_INVALID_PORT_CAP_MASK_Msk 0x1000UL 2470 #define USB32DEV_PROT_INTR_MASK_LMP_INVALID_PORT_CFG_MASK_Pos 13UL 2471 #define USB32DEV_PROT_INTR_MASK_LMP_INVALID_PORT_CFG_MASK_Msk 0x2000UL 2472 #define USB32DEV_PROT_INTR_MASK_EP0_STALLED_MASK_Pos 14UL 2473 #define USB32DEV_PROT_INTR_MASK_EP0_STALLED_MASK_Msk 0x4000UL 2474 #define USB32DEV_PROT_INTR_MASK_SET_ADDR0_MASK_Pos 15UL 2475 #define USB32DEV_PROT_INTR_MASK_SET_ADDR0_MASK_Msk 0x8000UL 2476 #define USB32DEV_PROT_INTR_MASK_LDM_TX_MASK_Pos 16UL 2477 #define USB32DEV_PROT_INTR_MASK_LDM_TX_MASK_Msk 0x10000UL 2478 #define USB32DEV_PROT_INTR_MASK_LDM_DL_TX_MASK_Pos 17UL 2479 #define USB32DEV_PROT_INTR_MASK_LDM_DL_TX_MASK_Msk 0x20000UL 2480 #define USB32DEV_PROT_INTR_MASK_LDM_RX_MASK_Pos 18UL 2481 #define USB32DEV_PROT_INTR_MASK_LDM_RX_MASK_Msk 0x40000UL 2482 #define USB32DEV_PROT_INTR_MASK_LDM_DL_RX_MASK_Pos 19UL 2483 #define USB32DEV_PROT_INTR_MASK_LDM_DL_RX_MASK_Msk 0x80000UL 2484 #define USB32DEV_PROT_INTR_MASK_RESP_TIMEOUT_1_MASK_Pos 20UL 2485 #define USB32DEV_PROT_INTR_MASK_RESP_TIMEOUT_1_MASK_Msk 0x100000UL 2486 #define USB32DEV_PROT_INTR_MASK_RESP_TIMEOUT_2_MASK_Pos 21UL 2487 #define USB32DEV_PROT_INTR_MASK_RESP_TIMEOUT_2_MASK_Msk 0x200000UL 2488 #define USB32DEV_PROT_INTR_MASK_RESP_TIMEOUT_3_MASK_Pos 22UL 2489 #define USB32DEV_PROT_INTR_MASK_RESP_TIMEOUT_3_MASK_Msk 0x400000UL 2490 #define USB32DEV_PROT_INTR_MASK_SET_ADDR_MASK_Pos 23UL 2491 #define USB32DEV_PROT_INTR_MASK_SET_ADDR_MASK_Msk 0x800000UL 2492 #define USB32DEV_PROT_INTR_MASK_DEFERRED_SET_MASK_Pos 24UL 2493 #define USB32DEV_PROT_INTR_MASK_DEFERRED_SET_MASK_Msk 0x1000000UL 2494 #define USB32DEV_PROT_INTR_MASK_DEFERRED_CLEAR_MASK_Pos 25UL 2495 #define USB32DEV_PROT_INTR_MASK_DEFERRED_CLEAR_MASK_Msk 0x2000000UL 2496 #define USB32DEV_PROT_INTR_MASK_LDM_STATE_CHANGE_MASK_Pos 26UL 2497 #define USB32DEV_PROT_INTR_MASK_LDM_STATE_CHANGE_MASK_Msk 0x4000000UL 2498 #define USB32DEV_PROT_INTR_MASK_T1_SCH_FULL_MASK_Pos 27UL 2499 #define USB32DEV_PROT_INTR_MASK_T1_SCH_FULL_MASK_Msk 0x8000000UL 2500 #define USB32DEV_PROT_INTR_MASK_T2_SCH_FULL_MASK_Pos 28UL 2501 #define USB32DEV_PROT_INTR_MASK_T2_SCH_FULL_MASK_Msk 0x10000000UL 2502 /* USB32DEV_PROT.PROT_INTR_MASKED */ 2503 #define USB32DEV_PROT_INTR_MASKED_LMP_RCV_MASKED_Pos 0UL 2504 #define USB32DEV_PROT_INTR_MASKED_LMP_RCV_MASKED_Msk 0x1UL 2505 #define USB32DEV_PROT_INTR_MASKED_LMP_UNKNOWN_MASKED_Pos 1UL 2506 #define USB32DEV_PROT_INTR_MASKED_LMP_UNKNOWN_MASKED_Msk 0x2UL 2507 #define USB32DEV_PROT_INTR_MASKED_LMP_PORT_CAP_MASKED_Pos 2UL 2508 #define USB32DEV_PROT_INTR_MASKED_LMP_PORT_CAP_MASKED_Msk 0x4UL 2509 #define USB32DEV_PROT_INTR_MASKED_LMP_PORT_CFG_MASKED_Pos 3UL 2510 #define USB32DEV_PROT_INTR_MASKED_LMP_PORT_CFG_MASKED_Msk 0x8UL 2511 #define USB32DEV_PROT_INTR_MASKED_TIMEOUT_PORT_CAP_MASKED_Pos 4UL 2512 #define USB32DEV_PROT_INTR_MASKED_TIMEOUT_PORT_CAP_MASKED_Msk 0x10UL 2513 #define USB32DEV_PROT_INTR_MASKED_TIMEOUT_PORT_CFG_MASKED_Pos 5UL 2514 #define USB32DEV_PROT_INTR_MASKED_TIMEOUT_PORT_CFG_MASKED_Msk 0x20UL 2515 #define USB32DEV_PROT_INTR_MASKED_TIMEOUT_PING_MASKED_Pos 6UL 2516 #define USB32DEV_PROT_INTR_MASKED_TIMEOUT_PING_MASKED_Msk 0x40UL 2517 #define USB32DEV_PROT_INTR_MASKED_ITP_MASKED_Pos 8UL 2518 #define USB32DEV_PROT_INTR_MASKED_ITP_MASKED_Msk 0x100UL 2519 #define USB32DEV_PROT_INTR_MASKED_SUTOK_MASKED_Pos 9UL 2520 #define USB32DEV_PROT_INTR_MASKED_SUTOK_MASKED_Msk 0x200UL 2521 #define USB32DEV_PROT_INTR_MASKED_HOST_ERR_MASKED_Pos 10UL 2522 #define USB32DEV_PROT_INTR_MASKED_HOST_ERR_MASKED_Msk 0x400UL 2523 #define USB32DEV_PROT_INTR_MASKED_STATUS_STAGE_MASKED_Pos 11UL 2524 #define USB32DEV_PROT_INTR_MASKED_STATUS_STAGE_MASKED_Msk 0x800UL 2525 #define USB32DEV_PROT_INTR_MASKED_LMP_INVALID_PORT_CAP_MASKED_Pos 12UL 2526 #define USB32DEV_PROT_INTR_MASKED_LMP_INVALID_PORT_CAP_MASKED_Msk 0x1000UL 2527 #define USB32DEV_PROT_INTR_MASKED_LMP_INVALID_PORT_CFG_MASKED_Pos 13UL 2528 #define USB32DEV_PROT_INTR_MASKED_LMP_INVALID_PORT_CFG_MASKED_Msk 0x2000UL 2529 #define USB32DEV_PROT_INTR_MASKED_EP0_STALLED_MASKED_Pos 14UL 2530 #define USB32DEV_PROT_INTR_MASKED_EP0_STALLED_MASKED_Msk 0x4000UL 2531 #define USB32DEV_PROT_INTR_MASKED_SET_ADDR0_MASKED_Pos 15UL 2532 #define USB32DEV_PROT_INTR_MASKED_SET_ADDR0_MASKED_Msk 0x8000UL 2533 #define USB32DEV_PROT_INTR_MASKED_LDM_TX_MASKED_Pos 16UL 2534 #define USB32DEV_PROT_INTR_MASKED_LDM_TX_MASKED_Msk 0x10000UL 2535 #define USB32DEV_PROT_INTR_MASKED_LDM_DL_TX_MASKED_Pos 17UL 2536 #define USB32DEV_PROT_INTR_MASKED_LDM_DL_TX_MASKED_Msk 0x20000UL 2537 #define USB32DEV_PROT_INTR_MASKED_LDM_RX_MASKED_Pos 18UL 2538 #define USB32DEV_PROT_INTR_MASKED_LDM_RX_MASKED_Msk 0x40000UL 2539 #define USB32DEV_PROT_INTR_MASKED_LDM_DL_RX_MASKED_Pos 19UL 2540 #define USB32DEV_PROT_INTR_MASKED_LDM_DL_RX_MASKED_Msk 0x80000UL 2541 #define USB32DEV_PROT_INTR_MASKED_RESP_TIMEOUT_1_MASKED_Pos 20UL 2542 #define USB32DEV_PROT_INTR_MASKED_RESP_TIMEOUT_1_MASKED_Msk 0x100000UL 2543 #define USB32DEV_PROT_INTR_MASKED_RESP_TIMEOUT_2_MASKED_Pos 21UL 2544 #define USB32DEV_PROT_INTR_MASKED_RESP_TIMEOUT_2_MASKED_Msk 0x200000UL 2545 #define USB32DEV_PROT_INTR_MASKED_RESP_TIMEOUT_3_MASKED_Pos 22UL 2546 #define USB32DEV_PROT_INTR_MASKED_RESP_TIMEOUT_3_MASKED_Msk 0x400000UL 2547 #define USB32DEV_PROT_INTR_MASKED_SET_ADDR_MASKED_Pos 23UL 2548 #define USB32DEV_PROT_INTR_MASKED_SET_ADDR_MASKED_Msk 0x800000UL 2549 #define USB32DEV_PROT_INTR_MASKED_DEFERRED_SET_MASKED_Pos 24UL 2550 #define USB32DEV_PROT_INTR_MASKED_DEFERRED_SET_MASKED_Msk 0x1000000UL 2551 #define USB32DEV_PROT_INTR_MASKED_DEFERRED_CLEAR_MASKED_Pos 25UL 2552 #define USB32DEV_PROT_INTR_MASKED_DEFERRED_CLEAR_MASKED_Msk 0x2000000UL 2553 #define USB32DEV_PROT_INTR_MASKED_LDM_STATE_CHANGE_MASKED_Pos 26UL 2554 #define USB32DEV_PROT_INTR_MASKED_LDM_STATE_CHANGE_MASKED_Msk 0x4000000UL 2555 #define USB32DEV_PROT_INTR_MASKED_T1_SCH_FULL_MASKED_Pos 27UL 2556 #define USB32DEV_PROT_INTR_MASKED_T1_SCH_FULL_MASKED_Msk 0x8000000UL 2557 #define USB32DEV_PROT_INTR_MASKED_T2_SCH_FULL_MASKED_Pos 28UL 2558 #define USB32DEV_PROT_INTR_MASKED_T2_SCH_FULL_MASKED_Msk 0x10000000UL 2559 /* USB32DEV_PROT.PROT_EP_INTR */ 2560 #define USB32DEV_PROT_EP_INTR_EP_IN_Pos 0UL 2561 #define USB32DEV_PROT_EP_INTR_EP_IN_Msk 0xFFFFUL 2562 #define USB32DEV_PROT_EP_INTR_EP_OUT_Pos 16UL 2563 #define USB32DEV_PROT_EP_INTR_EP_OUT_Msk 0xFFFF0000UL 2564 /* USB32DEV_PROT.PROT_EP_INTR_SET */ 2565 #define USB32DEV_PROT_EP_INTR_SET_EP_IN_Pos 0UL 2566 #define USB32DEV_PROT_EP_INTR_SET_EP_IN_Msk 0xFFFFUL 2567 #define USB32DEV_PROT_EP_INTR_SET_EP_OUT_Pos 16UL 2568 #define USB32DEV_PROT_EP_INTR_SET_EP_OUT_Msk 0xFFFF0000UL 2569 /* USB32DEV_PROT.PROT_EP_INTR_MASK */ 2570 #define USB32DEV_PROT_EP_INTR_MASK_EP_IN_MASK_Pos 0UL 2571 #define USB32DEV_PROT_EP_INTR_MASK_EP_IN_MASK_Msk 0xFFFFUL 2572 #define USB32DEV_PROT_EP_INTR_MASK_EP_OUT_MASK_Pos 16UL 2573 #define USB32DEV_PROT_EP_INTR_MASK_EP_OUT_MASK_Msk 0xFFFF0000UL 2574 /* USB32DEV_PROT.PROT_EP_INTR_MASKED */ 2575 #define USB32DEV_PROT_EP_INTR_MASKED_EP_IN_MASKED_Pos 0UL 2576 #define USB32DEV_PROT_EP_INTR_MASKED_EP_IN_MASKED_Msk 0xFFFFUL 2577 #define USB32DEV_PROT_EP_INTR_MASKED_EP_OUT_MASKED_Pos 16UL 2578 #define USB32DEV_PROT_EP_INTR_MASKED_EP_OUT_MASKED_Msk 0xFFFF0000UL 2579 /* USB32DEV_PROT.PROT_DEVICE_NOTIF_FUNC_WAKE */ 2580 #define USB32DEV_PROT_DEVICE_NOTIF_FUNC_WAKE_INTERFACE_Pos 0UL 2581 #define USB32DEV_PROT_DEVICE_NOTIF_FUNC_WAKE_INTERFACE_Msk 0xFFUL 2582 #define USB32DEV_PROT_DEVICE_NOTIF_FUNC_WAKE_REQUEST_Pos 31UL 2583 #define USB32DEV_PROT_DEVICE_NOTIF_FUNC_WAKE_REQUEST_Msk 0x80000000UL 2584 /* USB32DEV_PROT.PROT_DEVICE_NOTIF_LTM */ 2585 #define USB32DEV_PROT_DEVICE_NOTIF_LTM_BELT_LATENCY_Pos 0UL 2586 #define USB32DEV_PROT_DEVICE_NOTIF_LTM_BELT_LATENCY_Msk 0x3FFUL 2587 #define USB32DEV_PROT_DEVICE_NOTIF_LTM_BELT_SCALE_Pos 10UL 2588 #define USB32DEV_PROT_DEVICE_NOTIF_LTM_BELT_SCALE_Msk 0xC00UL 2589 #define USB32DEV_PROT_DEVICE_NOTIF_LTM_REQUEST_Pos 31UL 2590 #define USB32DEV_PROT_DEVICE_NOTIF_LTM_REQUEST_Msk 0x80000000UL 2591 /* USB32DEV_PROT.PROT_DEVICE_NOTIF_BIAM */ 2592 #define USB32DEV_PROT_DEVICE_NOTIF_BIAM_BIA_Pos 0UL 2593 #define USB32DEV_PROT_DEVICE_NOTIF_BIAM_BIA_Msk 0xFFFFUL 2594 #define USB32DEV_PROT_DEVICE_NOTIF_BIAM_REQUEST_Pos 31UL 2595 #define USB32DEV_PROT_DEVICE_NOTIF_BIAM_REQUEST_Msk 0x80000000UL 2596 /* USB32DEV_PROT.PROT_LMP_PORT_CAPABILITY_TIMER */ 2597 #define USB32DEV_PROT_LMP_PORT_CAPABILITY_TIMER_RX_TIMEOUT_Pos 0UL 2598 #define USB32DEV_PROT_LMP_PORT_CAPABILITY_TIMER_RX_TIMEOUT_Msk 0x7FFFUL 2599 #define USB32DEV_PROT_LMP_PORT_CAPABILITY_TIMER_RX_DISABLE_Pos 15UL 2600 #define USB32DEV_PROT_LMP_PORT_CAPABILITY_TIMER_RX_DISABLE_Msk 0x8000UL 2601 #define USB32DEV_PROT_LMP_PORT_CAPABILITY_TIMER_TX_TIMEOUT_Pos 16UL 2602 #define USB32DEV_PROT_LMP_PORT_CAPABILITY_TIMER_TX_TIMEOUT_Msk 0x7FFF0000UL 2603 #define USB32DEV_PROT_LMP_PORT_CAPABILITY_TIMER_TX_DISABLE_Pos 31UL 2604 #define USB32DEV_PROT_LMP_PORT_CAPABILITY_TIMER_TX_DISABLE_Msk 0x80000000UL 2605 /* USB32DEV_PROT.PROT_LMP_PORT_CONFIGURATION_TIMER */ 2606 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TIMER_RX_TIMEOUT_Pos 0UL 2607 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TIMER_RX_TIMEOUT_Msk 0x7FFFUL 2608 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TIMER_RX_DISABLE_Pos 15UL 2609 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TIMER_RX_DISABLE_Msk 0x8000UL 2610 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TIMER_TX_TIMEOUT_Pos 16UL 2611 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TIMER_TX_TIMEOUT_Msk 0x7FFF0000UL 2612 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TIMER_TX_DISABLE_Pos 31UL 2613 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TIMER_TX_DISABLE_Msk 0x80000000UL 2614 /* USB32DEV_PROT.PROT_PING_TIMEOUT */ 2615 #define USB32DEV_PROT_PING_TIMEOUT_PING_TIMEOUT_Pos 0UL 2616 #define USB32DEV_PROT_PING_TIMEOUT_PING_TIMEOUT_Msk 0xFFFFFFUL 2617 #define USB32DEV_PROT_PING_TIMEOUT_PING_DISABLE_Pos 31UL 2618 #define USB32DEV_PROT_PING_TIMEOUT_PING_DISABLE_Msk 0x80000000UL 2619 /* USB32DEV_PROT.PROT_FRAMECNT */ 2620 #define USB32DEV_PROT_FRAMECNT_SS_MICROFRAME_Pos 0UL 2621 #define USB32DEV_PROT_FRAMECNT_SS_MICROFRAME_Msk 0x3FFFUL 2622 #define USB32DEV_PROT_FRAMECNT_DELTA_Pos 14UL 2623 #define USB32DEV_PROT_FRAMECNT_DELTA_Msk 0x7FFC000UL 2624 /* USB32DEV_PROT.PROT_ITP_CORRECTION */ 2625 #define USB32DEV_PROT_ITP_CORRECTION_CORRECTION_Pos 0UL 2626 #define USB32DEV_PROT_ITP_CORRECTION_CORRECTION_Msk 0x3FFFUL 2627 /* USB32DEV_PROT.PROT_SETUPDAT0 */ 2628 #define USB32DEV_PROT_SETUPDAT0_SETUP_REQUEST_TYPE_Pos 0UL 2629 #define USB32DEV_PROT_SETUPDAT0_SETUP_REQUEST_TYPE_Msk 0xFFUL 2630 #define USB32DEV_PROT_SETUPDAT0_SETUP_REQUEST_Pos 8UL 2631 #define USB32DEV_PROT_SETUPDAT0_SETUP_REQUEST_Msk 0xFF00UL 2632 #define USB32DEV_PROT_SETUPDAT0_SETUP_VALUE_Pos 16UL 2633 #define USB32DEV_PROT_SETUPDAT0_SETUP_VALUE_Msk 0xFFFF0000UL 2634 /* USB32DEV_PROT.PROT_SETUPDAT1 */ 2635 #define USB32DEV_PROT_SETUPDAT1_SETUP_INDEX_Pos 0UL 2636 #define USB32DEV_PROT_SETUPDAT1_SETUP_INDEX_Msk 0xFFFFUL 2637 #define USB32DEV_PROT_SETUPDAT1_SETUP_LENGTH_Pos 16UL 2638 #define USB32DEV_PROT_SETUPDAT1_SETUP_LENGTH_Msk 0xFFFF0000UL 2639 /* USB32DEV_PROT.PROT_SEQ_NUM */ 2640 #define USB32DEV_PROT_SEQ_NUM_INGRESS_EP_NUM_Pos 0UL 2641 #define USB32DEV_PROT_SEQ_NUM_INGRESS_EP_NUM_Msk 0xFUL 2642 #define USB32DEV_PROT_SEQ_NUM_INGRESS_READ_SEQ_NUM_Pos 4UL 2643 #define USB32DEV_PROT_SEQ_NUM_INGRESS_READ_SEQ_NUM_Msk 0x1F0UL 2644 #define USB32DEV_PROT_SEQ_NUM_INGRESS_WRITE_SEQ_NUM_Pos 9UL 2645 #define USB32DEV_PROT_SEQ_NUM_INGRESS_WRITE_SEQ_NUM_Msk 0x3E00UL 2646 #define USB32DEV_PROT_SEQ_NUM_EGRESS_EP_NUM_Pos 16UL 2647 #define USB32DEV_PROT_SEQ_NUM_EGRESS_EP_NUM_Msk 0xF0000UL 2648 #define USB32DEV_PROT_SEQ_NUM_EGRESS_READ_SEQ_NUM_Pos 20UL 2649 #define USB32DEV_PROT_SEQ_NUM_EGRESS_READ_SEQ_NUM_Msk 0x1F00000UL 2650 #define USB32DEV_PROT_SEQ_NUM_EGRESS_WRITE_SEQ_NUM_Pos 25UL 2651 #define USB32DEV_PROT_SEQ_NUM_EGRESS_WRITE_SEQ_NUM_Msk 0x3E000000UL 2652 /* USB32DEV_PROT.PROT_LMP_RECEIVED */ 2653 #define USB32DEV_PROT_LMP_RECEIVED_U2_INACTIVITY_TIMEOUT_Pos 0UL 2654 #define USB32DEV_PROT_LMP_RECEIVED_U2_INACTIVITY_TIMEOUT_Msk 0xFFUL 2655 #define USB32DEV_PROT_LMP_RECEIVED_FORCE_LINKPM_ACCEPT_Pos 8UL 2656 #define USB32DEV_PROT_LMP_RECEIVED_FORCE_LINKPM_ACCEPT_Msk 0x100UL 2657 /* USB32DEV_PROT.PROT_LMP_OVERRIDE */ 2658 #define USB32DEV_PROT_LMP_OVERRIDE_U2_INACTIVITY_TIMEOUT_Pos 0UL 2659 #define USB32DEV_PROT_LMP_OVERRIDE_U2_INACTIVITY_TIMEOUT_Msk 0xFFUL 2660 #define USB32DEV_PROT_LMP_OVERRIDE_FORCE_LINKPM_ACCEPT_Pos 8UL 2661 #define USB32DEV_PROT_LMP_OVERRIDE_FORCE_LINKPM_ACCEPT_Msk 0x100UL 2662 #define USB32DEV_PROT_LMP_OVERRIDE_INACITIVITY_TIMEOUT_OVR_Pos 29UL 2663 #define USB32DEV_PROT_LMP_OVERRIDE_INACITIVITY_TIMEOUT_OVR_Msk 0x20000000UL 2664 #define USB32DEV_PROT_LMP_OVERRIDE_LINKPM_ACCEPT_OVR_Pos 30UL 2665 #define USB32DEV_PROT_LMP_OVERRIDE_LINKPM_ACCEPT_OVR_Msk 0x40000000UL 2666 #define USB32DEV_PROT_LMP_OVERRIDE_LMP_SEND_Pos 31UL 2667 #define USB32DEV_PROT_LMP_OVERRIDE_LMP_SEND_Msk 0x80000000UL 2668 /* USB32DEV_PROT.PROT_LMP_PORT_CAPABILITIES_RX */ 2669 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_RX_LINK_SPEED_Pos 0UL 2670 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_RX_LINK_SPEED_Msk 0x7FUL 2671 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_RX_NUM_HP_BUFFERS_Pos 7UL 2672 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_RX_NUM_HP_BUFFERS_Msk 0x7F80UL 2673 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_RX_DIRECTION_Pos 15UL 2674 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_RX_DIRECTION_Msk 0x18000UL 2675 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_RX_TIEBREAKER_Pos 17UL 2676 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_RX_TIEBREAKER_Msk 0x1E0000UL 2677 /* USB32DEV_PROT.PROT_LMP_PORT_CAPABILITIES_TX */ 2678 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_LINK_SPEED_Pos 0UL 2679 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_LINK_SPEED_Msk 0x7FUL 2680 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_NUM_HP_BUFFERS_Pos 7UL 2681 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_NUM_HP_BUFFERS_Msk 0x7F80UL 2682 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_DIRECTION_Pos 15UL 2683 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_DIRECTION_Msk 0x18000UL 2684 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_TIEBREAKER_Pos 17UL 2685 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_TIEBREAKER_Msk 0x1E0000UL 2686 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_LMP_SEND_Pos 31UL 2687 #define USB32DEV_PROT_LMP_PORT_CAPABILITIES_TX_LMP_SEND_Msk 0x80000000UL 2688 /* USB32DEV_PROT.PROT_LMP_PORT_CONFIGURATION_RX */ 2689 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_RX_LINK_SPEED_Pos 0UL 2690 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_RX_LINK_SPEED_Msk 0x7FUL 2691 /* USB32DEV_PROT.PROT_LMP_PORT_CONFIGURATION_TX */ 2692 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TX_LINK_SPEED_Pos 0UL 2693 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TX_LINK_SPEED_Msk 0x7FUL 2694 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TX_LMP_SEND_Pos 31UL 2695 #define USB32DEV_PROT_LMP_PORT_CONFIGURATION_TX_LMP_SEND_Msk 0x80000000UL 2696 /* USB32DEV_PROT.PROT_STREAM_ERROR_DISABLE */ 2697 #define USB32DEV_PROT_STREAM_ERROR_DISABLE_TYPE_Pos 0UL 2698 #define USB32DEV_PROT_STREAM_ERROR_DISABLE_TYPE_Msk 0x3FUL 2699 /* USB32DEV_PROT.PROT_STREAM_ERROR_STATUS */ 2700 #define USB32DEV_PROT_STREAM_ERROR_STATUS_ID_Pos 0UL 2701 #define USB32DEV_PROT_STREAM_ERROR_STATUS_ID_Msk 0xFFFFUL 2702 #define USB32DEV_PROT_STREAM_ERROR_STATUS_EP_NUM_Pos 16UL 2703 #define USB32DEV_PROT_STREAM_ERROR_STATUS_EP_NUM_Msk 0xF0000UL 2704 #define USB32DEV_PROT_STREAM_ERROR_STATUS_EP_IO_Pos 20UL 2705 #define USB32DEV_PROT_STREAM_ERROR_STATUS_EP_IO_Msk 0x100000UL 2706 #define USB32DEV_PROT_STREAM_ERROR_STATUS_ERROR_TYPE_Pos 21UL 2707 #define USB32DEV_PROT_STREAM_ERROR_STATUS_ERROR_TYPE_Msk 0x7E00000UL 2708 #define USB32DEV_PROT_STREAM_ERROR_STATUS_ERROR_STATE_Pos 27UL 2709 #define USB32DEV_PROT_STREAM_ERROR_STATUS_ERROR_STATE_Msk 0x38000000UL 2710 #define USB32DEV_PROT_STREAM_ERROR_STATUS_ERROR_DETECTED_Pos 31UL 2711 #define USB32DEV_PROT_STREAM_ERROR_STATUS_ERROR_DETECTED_Msk 0x80000000UL 2712 /* USB32DEV_PROT.PROT_LMP_PACKET_RX */ 2713 #define USB32DEV_PROT_LMP_PACKET_RX_LMP_PACKET_Pos 0UL 2714 #define USB32DEV_PROT_LMP_PACKET_RX_LMP_PACKET_Msk 0xFFFFFFFFUL 2715 /* USB32DEV_PROT.PROT_LMP_PACKET_TX */ 2716 #define USB32DEV_PROT_LMP_PACKET_TX_LMP_PACKET_Pos 0UL 2717 #define USB32DEV_PROT_LMP_PACKET_TX_LMP_PACKET_Msk 0xFFFFFFFFUL 2718 /* USB32DEV_PROT.PROT_EPI_INTR */ 2719 #define USB32DEV_PROT_EPI_INTR_COMMIT_Pos 0UL 2720 #define USB32DEV_PROT_EPI_INTR_COMMIT_Msk 0x1UL 2721 #define USB32DEV_PROT_EPI_INTR_RETRY_Pos 1UL 2722 #define USB32DEV_PROT_EPI_INTR_RETRY_Msk 0x2UL 2723 #define USB32DEV_PROT_EPI_INTR_FLOWCONTROL_Pos 2UL 2724 #define USB32DEV_PROT_EPI_INTR_FLOWCONTROL_Msk 0x4UL 2725 #define USB32DEV_PROT_EPI_INTR_ZERO_Pos 4UL 2726 #define USB32DEV_PROT_EPI_INTR_ZERO_Msk 0x10UL 2727 #define USB32DEV_PROT_EPI_INTR_SHORT_Pos 5UL 2728 #define USB32DEV_PROT_EPI_INTR_SHORT_Msk 0x20UL 2729 #define USB32DEV_PROT_EPI_INTR_OOSERR_Pos 6UL 2730 #define USB32DEV_PROT_EPI_INTR_OOSERR_Msk 0x40UL 2731 #define USB32DEV_PROT_EPI_INTR_DBTERM_Pos 8UL 2732 #define USB32DEV_PROT_EPI_INTR_DBTERM_Msk 0x100UL 2733 #define USB32DEV_PROT_EPI_INTR_STREAM_ERROR_Pos 9UL 2734 #define USB32DEV_PROT_EPI_INTR_STREAM_ERROR_Msk 0x200UL 2735 #define USB32DEV_PROT_EPI_INTR_FIRST_ACK_NUMP_0_Pos 10UL 2736 #define USB32DEV_PROT_EPI_INTR_FIRST_ACK_NUMP_0_Msk 0x400UL 2737 #define USB32DEV_PROT_EPI_INTR_STREAM_ST_CHG_Pos 16UL 2738 #define USB32DEV_PROT_EPI_INTR_STREAM_ST_CHG_Msk 0x10000UL 2739 #define USB32DEV_PROT_EPI_INTR_FLOWCONTROL_EXIT_Pos 17UL 2740 #define USB32DEV_PROT_EPI_INTR_FLOWCONTROL_EXIT_Msk 0x20000UL 2741 #define USB32DEV_PROT_EPI_INTR_SPARE_REG_Pos 18UL 2742 #define USB32DEV_PROT_EPI_INTR_SPARE_REG_Msk 0x40000UL 2743 /* USB32DEV_PROT.PROT_EPI_INTR_SET */ 2744 #define USB32DEV_PROT_EPI_INTR_SET_COMMIT_Pos 0UL 2745 #define USB32DEV_PROT_EPI_INTR_SET_COMMIT_Msk 0x1UL 2746 #define USB32DEV_PROT_EPI_INTR_SET_RETRY_Pos 1UL 2747 #define USB32DEV_PROT_EPI_INTR_SET_RETRY_Msk 0x2UL 2748 #define USB32DEV_PROT_EPI_INTR_SET_FLOWCONTROL_Pos 2UL 2749 #define USB32DEV_PROT_EPI_INTR_SET_FLOWCONTROL_Msk 0x4UL 2750 #define USB32DEV_PROT_EPI_INTR_SET_ZERO_Pos 4UL 2751 #define USB32DEV_PROT_EPI_INTR_SET_ZERO_Msk 0x10UL 2752 #define USB32DEV_PROT_EPI_INTR_SET_SHORT_Pos 5UL 2753 #define USB32DEV_PROT_EPI_INTR_SET_SHORT_Msk 0x20UL 2754 #define USB32DEV_PROT_EPI_INTR_SET_OOSERR_Pos 6UL 2755 #define USB32DEV_PROT_EPI_INTR_SET_OOSERR_Msk 0x40UL 2756 #define USB32DEV_PROT_EPI_INTR_SET_DBTERM_Pos 8UL 2757 #define USB32DEV_PROT_EPI_INTR_SET_DBTERM_Msk 0x100UL 2758 #define USB32DEV_PROT_EPI_INTR_SET_STREAM_ERROR_Pos 9UL 2759 #define USB32DEV_PROT_EPI_INTR_SET_STREAM_ERROR_Msk 0x200UL 2760 #define USB32DEV_PROT_EPI_INTR_SET_FIRST_ACK_NUMP_0_Pos 10UL 2761 #define USB32DEV_PROT_EPI_INTR_SET_FIRST_ACK_NUMP_0_Msk 0x400UL 2762 #define USB32DEV_PROT_EPI_INTR_SET_STREAM_ST_CHG_Pos 16UL 2763 #define USB32DEV_PROT_EPI_INTR_SET_STREAM_ST_CHG_Msk 0x10000UL 2764 #define USB32DEV_PROT_EPI_INTR_SET_FLOWCONTROL_EXIT_Pos 17UL 2765 #define USB32DEV_PROT_EPI_INTR_SET_FLOWCONTROL_EXIT_Msk 0x20000UL 2766 #define USB32DEV_PROT_EPI_INTR_SET_SPARE_REG_Pos 18UL 2767 #define USB32DEV_PROT_EPI_INTR_SET_SPARE_REG_Msk 0x40000UL 2768 /* USB32DEV_PROT.PROT_EPI_INTR_MASK */ 2769 #define USB32DEV_PROT_EPI_INTR_MASK_COMMIT_MASK_Pos 0UL 2770 #define USB32DEV_PROT_EPI_INTR_MASK_COMMIT_MASK_Msk 0x1UL 2771 #define USB32DEV_PROT_EPI_INTR_MASK_RETRY_MASK_Pos 1UL 2772 #define USB32DEV_PROT_EPI_INTR_MASK_RETRY_MASK_Msk 0x2UL 2773 #define USB32DEV_PROT_EPI_INTR_MASK_FLOWCONTROL_MASK_Pos 2UL 2774 #define USB32DEV_PROT_EPI_INTR_MASK_FLOWCONTROL_MASK_Msk 0x4UL 2775 #define USB32DEV_PROT_EPI_INTR_MASK_ZERO_MASK_Pos 4UL 2776 #define USB32DEV_PROT_EPI_INTR_MASK_ZERO_MASK_Msk 0x10UL 2777 #define USB32DEV_PROT_EPI_INTR_MASK_SHORT_MASK_Pos 5UL 2778 #define USB32DEV_PROT_EPI_INTR_MASK_SHORT_MASK_Msk 0x20UL 2779 #define USB32DEV_PROT_EPI_INTR_MASK_OOSERR_MASK_Pos 6UL 2780 #define USB32DEV_PROT_EPI_INTR_MASK_OOSERR_MASK_Msk 0x40UL 2781 #define USB32DEV_PROT_EPI_INTR_MASK_DBTERM_MASK_Pos 8UL 2782 #define USB32DEV_PROT_EPI_INTR_MASK_DBTERM_MASK_Msk 0x100UL 2783 #define USB32DEV_PROT_EPI_INTR_MASK_STREAM_ERROR_MASK_Pos 9UL 2784 #define USB32DEV_PROT_EPI_INTR_MASK_STREAM_ERROR_MASK_Msk 0x200UL 2785 #define USB32DEV_PROT_EPI_INTR_MASK_FIRST_ACK_NUMP_0_MASK_Pos 10UL 2786 #define USB32DEV_PROT_EPI_INTR_MASK_FIRST_ACK_NUMP_0_MASK_Msk 0x400UL 2787 #define USB32DEV_PROT_EPI_INTR_MASK_STREAM_ST_CHG_MASK_Pos 16UL 2788 #define USB32DEV_PROT_EPI_INTR_MASK_STREAM_ST_CHG_MASK_Msk 0x10000UL 2789 #define USB32DEV_PROT_EPI_INTR_MASK_FLOWCONTROL_EXIT_MASK_Pos 17UL 2790 #define USB32DEV_PROT_EPI_INTR_MASK_FLOWCONTROL_EXIT_MASK_Msk 0x20000UL 2791 #define USB32DEV_PROT_EPI_INTR_MASK_SPARE_REG_MASK_Pos 18UL 2792 #define USB32DEV_PROT_EPI_INTR_MASK_SPARE_REG_MASK_Msk 0x40000UL 2793 /* USB32DEV_PROT.PROT_EPI_INTR_MASKED */ 2794 #define USB32DEV_PROT_EPI_INTR_MASKED_COMMIT_MASKED_Pos 0UL 2795 #define USB32DEV_PROT_EPI_INTR_MASKED_COMMIT_MASKED_Msk 0x1UL 2796 #define USB32DEV_PROT_EPI_INTR_MASKED_RETRY_MASKED_Pos 1UL 2797 #define USB32DEV_PROT_EPI_INTR_MASKED_RETRY_MASKED_Msk 0x2UL 2798 #define USB32DEV_PROT_EPI_INTR_MASKED_FLOWCONTROL_MASKED_Pos 2UL 2799 #define USB32DEV_PROT_EPI_INTR_MASKED_FLOWCONTROL_MASKED_Msk 0x4UL 2800 #define USB32DEV_PROT_EPI_INTR_MASKED_ZERO_MASKED_Pos 4UL 2801 #define USB32DEV_PROT_EPI_INTR_MASKED_ZERO_MASKED_Msk 0x10UL 2802 #define USB32DEV_PROT_EPI_INTR_MASKED_SHORT_MASKED_Pos 5UL 2803 #define USB32DEV_PROT_EPI_INTR_MASKED_SHORT_MASKED_Msk 0x20UL 2804 #define USB32DEV_PROT_EPI_INTR_MASKED_OOSERR_MASKED_Pos 6UL 2805 #define USB32DEV_PROT_EPI_INTR_MASKED_OOSERR_MASKED_Msk 0x40UL 2806 #define USB32DEV_PROT_EPI_INTR_MASKED_DBTERM_MASKED_Pos 8UL 2807 #define USB32DEV_PROT_EPI_INTR_MASKED_DBTERM_MASKED_Msk 0x100UL 2808 #define USB32DEV_PROT_EPI_INTR_MASKED_STREAM_ERROR_MASKED_Pos 9UL 2809 #define USB32DEV_PROT_EPI_INTR_MASKED_STREAM_ERROR_MASKED_Msk 0x200UL 2810 #define USB32DEV_PROT_EPI_INTR_MASKED_FIRST_ACK_NUMP_0_MASKED_Pos 10UL 2811 #define USB32DEV_PROT_EPI_INTR_MASKED_FIRST_ACK_NUMP_0_MASKED_Msk 0x400UL 2812 #define USB32DEV_PROT_EPI_INTR_MASKED_STREAM_ST_CHG_MASKED_Pos 16UL 2813 #define USB32DEV_PROT_EPI_INTR_MASKED_STREAM_ST_CHG_MASKED_Msk 0x10000UL 2814 #define USB32DEV_PROT_EPI_INTR_MASKED_FLOWCONTROL_EXIT_MASKED_Pos 17UL 2815 #define USB32DEV_PROT_EPI_INTR_MASKED_FLOWCONTROL_EXIT_MASKED_Msk 0x20000UL 2816 #define USB32DEV_PROT_EPI_INTR_MASKED_SPARE_REG_MASKED_Pos 18UL 2817 #define USB32DEV_PROT_EPI_INTR_MASKED_SPARE_REG_MASKED_Msk 0x40000UL 2818 /* USB32DEV_PROT.PROT_EPI_CS1 */ 2819 #define USB32DEV_PROT_EPI_CS1_VALID_Pos 0UL 2820 #define USB32DEV_PROT_EPI_CS1_VALID_Msk 0x1UL 2821 #define USB32DEV_PROT_EPI_CS1_NRDY_Pos 1UL 2822 #define USB32DEV_PROT_EPI_CS1_NRDY_Msk 0x2UL 2823 #define USB32DEV_PROT_EPI_CS1_STALL_Pos 2UL 2824 #define USB32DEV_PROT_EPI_CS1_STALL_Msk 0x4UL 2825 #define USB32DEV_PROT_EPI_CS1_STREAM_EN_Pos 3UL 2826 #define USB32DEV_PROT_EPI_CS1_STREAM_EN_Msk 0x8UL 2827 #define USB32DEV_PROT_EPI_CS1_EP_RESET_Pos 4UL 2828 #define USB32DEV_PROT_EPI_CS1_EP_RESET_Msk 0x10UL 2829 #define USB32DEV_PROT_EPI_CS1_ERDY_FLOWCONTROL_Pos 8UL 2830 #define USB32DEV_PROT_EPI_CS1_ERDY_FLOWCONTROL_Msk 0x100UL 2831 /* USB32DEV_PROT.PROT_EPI_CS2 */ 2832 #define USB32DEV_PROT_EPI_CS2_EPI_TYPE_Pos 0UL 2833 #define USB32DEV_PROT_EPI_CS2_EPI_TYPE_Msk 0x3UL 2834 #define USB32DEV_PROT_EPI_CS2_SPARE_Pos 2UL 2835 #define USB32DEV_PROT_EPI_CS2_SPARE_Msk 0xFCUL 2836 #define USB32DEV_PROT_EPI_CS2_MAXBURST_Pos 8UL 2837 #define USB32DEV_PROT_EPI_CS2_MAXBURST_Msk 0xF00UL 2838 #define USB32DEV_PROT_EPI_CS2_ISOINPKS_Pos 17UL 2839 #define USB32DEV_PROT_EPI_CS2_ISOINPKS_Msk 0x1FE0000UL 2840 #define USB32DEV_PROT_EPI_CS2_BINTERVAL_Pos 25UL 2841 #define USB32DEV_PROT_EPI_CS2_BINTERVAL_Msk 0x1E000000UL 2842 /* USB32DEV_PROT.PROT_EPI_UNMAPPED_STREAM */ 2843 #define USB32DEV_PROT_EPI_UNMAPPED_STREAM_SPSM_STATE_Pos 16UL 2844 #define USB32DEV_PROT_EPI_UNMAPPED_STREAM_SPSM_STATE_Msk 0xF0000UL 2845 #define USB32DEV_PROT_EPI_UNMAPPED_STREAM_COMMAND_Pos 30UL 2846 #define USB32DEV_PROT_EPI_UNMAPPED_STREAM_COMMAND_Msk 0x40000000UL 2847 /* USB32DEV_PROT.PROT_EPI_MAPPED_STREAM */ 2848 #define USB32DEV_PROT_EPI_MAPPED_STREAM_STREAM_ID_Pos 0UL 2849 #define USB32DEV_PROT_EPI_MAPPED_STREAM_STREAM_ID_Msk 0xFFFFUL 2850 #define USB32DEV_PROT_EPI_MAPPED_STREAM_EP_NUMBER_Pos 16UL 2851 #define USB32DEV_PROT_EPI_MAPPED_STREAM_EP_NUMBER_Msk 0xF0000UL 2852 #define USB32DEV_PROT_EPI_MAPPED_STREAM_UNMAPPED_Pos 29UL 2853 #define USB32DEV_PROT_EPI_MAPPED_STREAM_UNMAPPED_Msk 0x20000000UL 2854 #define USB32DEV_PROT_EPI_MAPPED_STREAM_UNMAP_Pos 30UL 2855 #define USB32DEV_PROT_EPI_MAPPED_STREAM_UNMAP_Msk 0x40000000UL 2856 #define USB32DEV_PROT_EPI_MAPPED_STREAM_ENABLE_Pos 31UL 2857 #define USB32DEV_PROT_EPI_MAPPED_STREAM_ENABLE_Msk 0x80000000UL 2858 /* USB32DEV_PROT.PROT_EPO_INTR */ 2859 #define USB32DEV_PROT_EPO_INTR_COMMIT_Pos 0UL 2860 #define USB32DEV_PROT_EPO_INTR_COMMIT_Msk 0x1UL 2861 #define USB32DEV_PROT_EPO_INTR_RETRY_Pos 1UL 2862 #define USB32DEV_PROT_EPO_INTR_RETRY_Msk 0x2UL 2863 #define USB32DEV_PROT_EPO_INTR_FLOWCONTROL_Pos 2UL 2864 #define USB32DEV_PROT_EPO_INTR_FLOWCONTROL_Msk 0x4UL 2865 #define USB32DEV_PROT_EPO_INTR_ZERO_Pos 4UL 2866 #define USB32DEV_PROT_EPO_INTR_ZERO_Msk 0x10UL 2867 #define USB32DEV_PROT_EPO_INTR_SHORT_Pos 5UL 2868 #define USB32DEV_PROT_EPO_INTR_SHORT_Msk 0x20UL 2869 #define USB32DEV_PROT_EPO_INTR_OOSERR_Pos 6UL 2870 #define USB32DEV_PROT_EPO_INTR_OOSERR_Msk 0x40UL 2871 #define USB32DEV_PROT_EPO_INTR_STREAM_ERROR_Pos 9UL 2872 #define USB32DEV_PROT_EPO_INTR_STREAM_ERROR_Msk 0x200UL 2873 #define USB32DEV_PROT_EPO_INTR_PP_ZERO_Pos 11UL 2874 #define USB32DEV_PROT_EPO_INTR_PP_ZERO_Msk 0x800UL 2875 #define USB32DEV_PROT_EPO_INTR_EOB_ONE_Pos 12UL 2876 #define USB32DEV_PROT_EPO_INTR_EOB_ONE_Msk 0x1000UL 2877 #define USB32DEV_PROT_EPO_INTR_STREAM_ST_CHG_Pos 16UL 2878 #define USB32DEV_PROT_EPO_INTR_STREAM_ST_CHG_Msk 0x10000UL 2879 #define USB32DEV_PROT_EPO_INTR_FLOWCONTROL_EXIT_Pos 17UL 2880 #define USB32DEV_PROT_EPO_INTR_FLOWCONTROL_EXIT_Msk 0x20000UL 2881 #define USB32DEV_PROT_EPO_INTR_SPARE_REG_Pos 18UL 2882 #define USB32DEV_PROT_EPO_INTR_SPARE_REG_Msk 0x40000UL 2883 /* USB32DEV_PROT.PROT_EPO_INTR_SET */ 2884 #define USB32DEV_PROT_EPO_INTR_SET_COMMIT_Pos 0UL 2885 #define USB32DEV_PROT_EPO_INTR_SET_COMMIT_Msk 0x1UL 2886 #define USB32DEV_PROT_EPO_INTR_SET_RETRY_Pos 1UL 2887 #define USB32DEV_PROT_EPO_INTR_SET_RETRY_Msk 0x2UL 2888 #define USB32DEV_PROT_EPO_INTR_SET_FLOWCONTROL_Pos 2UL 2889 #define USB32DEV_PROT_EPO_INTR_SET_FLOWCONTROL_Msk 0x4UL 2890 #define USB32DEV_PROT_EPO_INTR_SET_ZERO_Pos 4UL 2891 #define USB32DEV_PROT_EPO_INTR_SET_ZERO_Msk 0x10UL 2892 #define USB32DEV_PROT_EPO_INTR_SET_SHORT_Pos 5UL 2893 #define USB32DEV_PROT_EPO_INTR_SET_SHORT_Msk 0x20UL 2894 #define USB32DEV_PROT_EPO_INTR_SET_OOSERR_Pos 6UL 2895 #define USB32DEV_PROT_EPO_INTR_SET_OOSERR_Msk 0x40UL 2896 #define USB32DEV_PROT_EPO_INTR_SET_STREAM_ERROR_Pos 9UL 2897 #define USB32DEV_PROT_EPO_INTR_SET_STREAM_ERROR_Msk 0x200UL 2898 #define USB32DEV_PROT_EPO_INTR_SET_PP_ZERO_Pos 11UL 2899 #define USB32DEV_PROT_EPO_INTR_SET_PP_ZERO_Msk 0x800UL 2900 #define USB32DEV_PROT_EPO_INTR_SET_EOB_ONE_Pos 12UL 2901 #define USB32DEV_PROT_EPO_INTR_SET_EOB_ONE_Msk 0x1000UL 2902 #define USB32DEV_PROT_EPO_INTR_SET_STREAM_ST_CHG_Pos 16UL 2903 #define USB32DEV_PROT_EPO_INTR_SET_STREAM_ST_CHG_Msk 0x10000UL 2904 #define USB32DEV_PROT_EPO_INTR_SET_FLOWCONTROL_EXIT_Pos 17UL 2905 #define USB32DEV_PROT_EPO_INTR_SET_FLOWCONTROL_EXIT_Msk 0x20000UL 2906 #define USB32DEV_PROT_EPO_INTR_SET_SPARE_REG_Pos 18UL 2907 #define USB32DEV_PROT_EPO_INTR_SET_SPARE_REG_Msk 0x40000UL 2908 /* USB32DEV_PROT.PROT_EPO_INTR_MASK */ 2909 #define USB32DEV_PROT_EPO_INTR_MASK_COMMIT_MASK_Pos 0UL 2910 #define USB32DEV_PROT_EPO_INTR_MASK_COMMIT_MASK_Msk 0x1UL 2911 #define USB32DEV_PROT_EPO_INTR_MASK_RETRY_MASK_Pos 1UL 2912 #define USB32DEV_PROT_EPO_INTR_MASK_RETRY_MASK_Msk 0x2UL 2913 #define USB32DEV_PROT_EPO_INTR_MASK_FLOWCONTROL_MASK_Pos 2UL 2914 #define USB32DEV_PROT_EPO_INTR_MASK_FLOWCONTROL_MASK_Msk 0x4UL 2915 #define USB32DEV_PROT_EPO_INTR_MASK_ZERO_MASK_Pos 4UL 2916 #define USB32DEV_PROT_EPO_INTR_MASK_ZERO_MASK_Msk 0x10UL 2917 #define USB32DEV_PROT_EPO_INTR_MASK_SHORT_MASK_Pos 5UL 2918 #define USB32DEV_PROT_EPO_INTR_MASK_SHORT_MASK_Msk 0x20UL 2919 #define USB32DEV_PROT_EPO_INTR_MASK_OOSERR_MASK_Pos 6UL 2920 #define USB32DEV_PROT_EPO_INTR_MASK_OOSERR_MASK_Msk 0x40UL 2921 #define USB32DEV_PROT_EPO_INTR_MASK_STREAM_ERROR_MASK_Pos 9UL 2922 #define USB32DEV_PROT_EPO_INTR_MASK_STREAM_ERROR_MASK_Msk 0x200UL 2923 #define USB32DEV_PROT_EPO_INTR_MASK_PP_ZERO_MASK_Pos 11UL 2924 #define USB32DEV_PROT_EPO_INTR_MASK_PP_ZERO_MASK_Msk 0x800UL 2925 #define USB32DEV_PROT_EPO_INTR_MASK_EOB_ONE_MASK_Pos 12UL 2926 #define USB32DEV_PROT_EPO_INTR_MASK_EOB_ONE_MASK_Msk 0x1000UL 2927 #define USB32DEV_PROT_EPO_INTR_MASK_STREAM_ST_CHG_MASK_Pos 16UL 2928 #define USB32DEV_PROT_EPO_INTR_MASK_STREAM_ST_CHG_MASK_Msk 0x10000UL 2929 #define USB32DEV_PROT_EPO_INTR_MASK_FLOWCONTROL_EXIT_MASK_Pos 17UL 2930 #define USB32DEV_PROT_EPO_INTR_MASK_FLOWCONTROL_EXIT_MASK_Msk 0x20000UL 2931 #define USB32DEV_PROT_EPO_INTR_MASK_SPARE_REG_MASK_Pos 18UL 2932 #define USB32DEV_PROT_EPO_INTR_MASK_SPARE_REG_MASK_Msk 0x40000UL 2933 /* USB32DEV_PROT.PROT_EPO_INTR_MASKED */ 2934 #define USB32DEV_PROT_EPO_INTR_MASKED_COMMIT_MASKED_Pos 0UL 2935 #define USB32DEV_PROT_EPO_INTR_MASKED_COMMIT_MASKED_Msk 0x1UL 2936 #define USB32DEV_PROT_EPO_INTR_MASKED_RETRY_MASKED_Pos 1UL 2937 #define USB32DEV_PROT_EPO_INTR_MASKED_RETRY_MASKED_Msk 0x2UL 2938 #define USB32DEV_PROT_EPO_INTR_MASKED_FLOWCONTROL_MASKED_Pos 2UL 2939 #define USB32DEV_PROT_EPO_INTR_MASKED_FLOWCONTROL_MASKED_Msk 0x4UL 2940 #define USB32DEV_PROT_EPO_INTR_MASKED_ZERO_MASKED_Pos 4UL 2941 #define USB32DEV_PROT_EPO_INTR_MASKED_ZERO_MASKED_Msk 0x10UL 2942 #define USB32DEV_PROT_EPO_INTR_MASKED_SHORT_MASKED_Pos 5UL 2943 #define USB32DEV_PROT_EPO_INTR_MASKED_SHORT_MASKED_Msk 0x20UL 2944 #define USB32DEV_PROT_EPO_INTR_MASKED_OOSERR_MASKED_Pos 6UL 2945 #define USB32DEV_PROT_EPO_INTR_MASKED_OOSERR_MASKED_Msk 0x40UL 2946 #define USB32DEV_PROT_EPO_INTR_MASKED_STREAM_ERROR_MASKED_Pos 9UL 2947 #define USB32DEV_PROT_EPO_INTR_MASKED_STREAM_ERROR_MASKED_Msk 0x200UL 2948 #define USB32DEV_PROT_EPO_INTR_MASKED_PP_ZERO_MASKED_Pos 11UL 2949 #define USB32DEV_PROT_EPO_INTR_MASKED_PP_ZERO_MASKED_Msk 0x800UL 2950 #define USB32DEV_PROT_EPO_INTR_MASKED_EOB_ONE_MASKED_Pos 12UL 2951 #define USB32DEV_PROT_EPO_INTR_MASKED_EOB_ONE_MASKED_Msk 0x1000UL 2952 #define USB32DEV_PROT_EPO_INTR_MASKED_STREAM_ST_CHG_MASKED_Pos 16UL 2953 #define USB32DEV_PROT_EPO_INTR_MASKED_STREAM_ST_CHG_MASKED_Msk 0x10000UL 2954 #define USB32DEV_PROT_EPO_INTR_MASKED_FLOWCONTROL_EXIT_MASKED_Pos 17UL 2955 #define USB32DEV_PROT_EPO_INTR_MASKED_FLOWCONTROL_EXIT_MASKED_Msk 0x20000UL 2956 #define USB32DEV_PROT_EPO_INTR_MASKED_SPARE_REG_MASKED_Pos 18UL 2957 #define USB32DEV_PROT_EPO_INTR_MASKED_SPARE_REG_MASKED_Msk 0x40000UL 2958 /* USB32DEV_PROT.PROT_EPO_CS1 */ 2959 #define USB32DEV_PROT_EPO_CS1_VALID_Pos 0UL 2960 #define USB32DEV_PROT_EPO_CS1_VALID_Msk 0x1UL 2961 #define USB32DEV_PROT_EPO_CS1_NRDY_Pos 1UL 2962 #define USB32DEV_PROT_EPO_CS1_NRDY_Msk 0x2UL 2963 #define USB32DEV_PROT_EPO_CS1_STALL_Pos 2UL 2964 #define USB32DEV_PROT_EPO_CS1_STALL_Msk 0x4UL 2965 #define USB32DEV_PROT_EPO_CS1_STREAM_EN_Pos 3UL 2966 #define USB32DEV_PROT_EPO_CS1_STREAM_EN_Msk 0x8UL 2967 #define USB32DEV_PROT_EPO_CS1_EP_RESET_Pos 4UL 2968 #define USB32DEV_PROT_EPO_CS1_EP_RESET_Msk 0x10UL 2969 #define USB32DEV_PROT_EPO_CS1_EN_PP_ZERO_DET_Pos 6UL 2970 #define USB32DEV_PROT_EPO_CS1_EN_PP_ZERO_DET_Msk 0x40UL 2971 #define USB32DEV_PROT_EPO_CS1_EN_EOB_ONE_DET_Pos 7UL 2972 #define USB32DEV_PROT_EPO_CS1_EN_EOB_ONE_DET_Msk 0x80UL 2973 #define USB32DEV_PROT_EPO_CS1_ERDY_FLOWCONTROL_Pos 8UL 2974 #define USB32DEV_PROT_EPO_CS1_ERDY_FLOWCONTROL_Msk 0x100UL 2975 /* USB32DEV_PROT.PROT_EPO_CS2 */ 2976 #define USB32DEV_PROT_EPO_CS2_EPO_TYPE_Pos 0UL 2977 #define USB32DEV_PROT_EPO_CS2_EPO_TYPE_Msk 0x3UL 2978 #define USB32DEV_PROT_EPO_CS2_SPARE_Pos 2UL 2979 #define USB32DEV_PROT_EPO_CS2_SPARE_Msk 0xFCUL 2980 #define USB32DEV_PROT_EPO_CS2_MAXBURST_Pos 8UL 2981 #define USB32DEV_PROT_EPO_CS2_MAXBURST_Msk 0xF00UL 2982 #define USB32DEV_PROT_EPO_CS2_ISOINPKS_Pos 17UL 2983 #define USB32DEV_PROT_EPO_CS2_ISOINPKS_Msk 0x1FE0000UL 2984 /* USB32DEV_PROT.PROT_EPO_UNMAPPED_STREAM */ 2985 #define USB32DEV_PROT_EPO_UNMAPPED_STREAM_SPSM_STATE_Pos 16UL 2986 #define USB32DEV_PROT_EPO_UNMAPPED_STREAM_SPSM_STATE_Msk 0xF0000UL 2987 #define USB32DEV_PROT_EPO_UNMAPPED_STREAM_COMMAND_Pos 30UL 2988 #define USB32DEV_PROT_EPO_UNMAPPED_STREAM_COMMAND_Msk 0x40000000UL 2989 /* USB32DEV_PROT.PROT_EPO_MAPPED_STREAM */ 2990 #define USB32DEV_PROT_EPO_MAPPED_STREAM_STREAM_ID_Pos 0UL 2991 #define USB32DEV_PROT_EPO_MAPPED_STREAM_STREAM_ID_Msk 0xFFFFUL 2992 #define USB32DEV_PROT_EPO_MAPPED_STREAM_EP_NUMBER_Pos 16UL 2993 #define USB32DEV_PROT_EPO_MAPPED_STREAM_EP_NUMBER_Msk 0xF0000UL 2994 #define USB32DEV_PROT_EPO_MAPPED_STREAM_UNMAPPED_Pos 29UL 2995 #define USB32DEV_PROT_EPO_MAPPED_STREAM_UNMAPPED_Msk 0x20000000UL 2996 #define USB32DEV_PROT_EPO_MAPPED_STREAM_UNMAP_Pos 30UL 2997 #define USB32DEV_PROT_EPO_MAPPED_STREAM_UNMAP_Msk 0x40000000UL 2998 #define USB32DEV_PROT_EPO_MAPPED_STREAM_ENABLE_Pos 31UL 2999 #define USB32DEV_PROT_EPO_MAPPED_STREAM_ENABLE_Msk 0x80000000UL 3000 /* USB32DEV_PROT.PROT_SUBLINK_DEV_NNOTIFICATION */ 3001 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_EN_SUBLINK_Pos 0UL 3002 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_EN_SUBLINK_Msk 0x1UL 3003 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_EN_SUBLINK_SET_ADDR0_Pos 1UL 3004 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_EN_SUBLINK_SET_ADDR0_Msk 0x2UL 3005 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_LSE_Pos 2UL 3006 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_LSE_Msk 0xCUL 3007 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_ST_Pos 4UL 3008 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_ST_Msk 0x30UL 3009 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_LANES_Pos 6UL 3010 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_LANES_Msk 0x3C0UL 3011 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_LP_Pos 10UL 3012 #define USB32DEV_PROT_SUBLINK_DEV_NNOTIFICATION_LP_Msk 0xC00UL 3013 /* USB32DEV_PROT.PROT_SUBLINK_LSM */ 3014 #define USB32DEV_PROT_SUBLINK_LSM_RX_LSM_Pos 0UL 3015 #define USB32DEV_PROT_SUBLINK_LSM_RX_LSM_Msk 0xFFFFUL 3016 #define USB32DEV_PROT_SUBLINK_LSM_TX_LSM_Pos 16UL 3017 #define USB32DEV_PROT_SUBLINK_LSM_TX_LSM_Msk 0xFFFF0000UL 3018 /* USB32DEV_PROT.PROT_PTM_CONFIG */ 3019 #define USB32DEV_PROT_PTM_CONFIG_LDM_ENABLE_Pos 0UL 3020 #define USB32DEV_PROT_PTM_CONFIG_LDM_ENABLE_Msk 0x1UL 3021 #define USB32DEV_PROT_PTM_CONFIG_COUNTER_CFG_Pos 1UL 3022 #define USB32DEV_PROT_PTM_CONFIG_COUNTER_CFG_Msk 0x2UL 3023 #define USB32DEV_PROT_PTM_CONFIG_WAIT_ITP_Pos 2UL 3024 #define USB32DEV_PROT_PTM_CONFIG_WAIT_ITP_Msk 0x4UL 3025 #define USB32DEV_PROT_PTM_CONFIG_START_Pos 8UL 3026 #define USB32DEV_PROT_PTM_CONFIG_START_Msk 0x100UL 3027 #define USB32DEV_PROT_PTM_CONFIG_STATE_CHANGE_SEL_Pos 9UL 3028 #define USB32DEV_PROT_PTM_CONFIG_STATE_CHANGE_SEL_Msk 0xE00UL 3029 #define USB32DEV_PROT_PTM_CONFIG_LMP_SEND_Pos 31UL 3030 #define USB32DEV_PROT_PTM_CONFIG_LMP_SEND_Msk 0x80000000UL 3031 /* USB32DEV_PROT.PROT_FW_PTM_COUNTER */ 3032 #define USB32DEV_PROT_FW_PTM_COUNTER_LOAD_Pos 0UL 3033 #define USB32DEV_PROT_FW_PTM_COUNTER_LOAD_Msk 0x1UL 3034 #define USB32DEV_PROT_FW_PTM_COUNTER_VALUE_Pos 1UL 3035 #define USB32DEV_PROT_FW_PTM_COUNTER_VALUE_Msk 0xFFFFFFEUL 3036 /* USB32DEV_PROT.PROT_HW_PTM_COUNTER */ 3037 #define USB32DEV_PROT_HW_PTM_COUNTER_READ_Pos 0UL 3038 #define USB32DEV_PROT_HW_PTM_COUNTER_READ_Msk 0x1UL 3039 #define USB32DEV_PROT_HW_PTM_COUNTER_BIC_Pos 1UL 3040 #define USB32DEV_PROT_HW_PTM_COUNTER_BIC_Msk 0x7FFEUL 3041 #define USB32DEV_PROT_HW_PTM_COUNTER_DC_Pos 15UL 3042 #define USB32DEV_PROT_HW_PTM_COUNTER_DC_Msk 0xFFF8000UL 3043 /* USB32DEV_PROT.PROT_PTM_STATUS */ 3044 #define USB32DEV_PROT_PTM_STATUS_LDM_REQ_STATE_Pos 0UL 3045 #define USB32DEV_PROT_PTM_STATUS_LDM_REQ_STATE_Msk 0x7UL 3046 #define USB32DEV_PROT_PTM_STATUS_LDMS_TX_Pos 3UL 3047 #define USB32DEV_PROT_PTM_STATUS_LDMS_TX_Msk 0x18UL 3048 /* USB32DEV_PROT.PROT_PTM_T1 */ 3049 #define USB32DEV_PROT_PTM_T1_TIME_Pos 0UL 3050 #define USB32DEV_PROT_PTM_T1_TIME_Msk 0x7FFFFFFUL 3051 /* USB32DEV_PROT.PROT_PTM_T4 */ 3052 #define USB32DEV_PROT_PTM_T4_TIME_Pos 0UL 3053 #define USB32DEV_PROT_PTM_T4_TIME_Msk 0x7FFFFFFUL 3054 /* USB32DEV_PROT.PROT_LMP_LDM_RESPONSE */ 3055 #define USB32DEV_PROT_LMP_LDM_RESPONSE_LDM_TYPE_Pos 0UL 3056 #define USB32DEV_PROT_LMP_LDM_RESPONSE_LDM_TYPE_Msk 0x7UL 3057 #define USB32DEV_PROT_LMP_LDM_RESPONSE_LDMS_RX_Pos 3UL 3058 #define USB32DEV_PROT_LMP_LDM_RESPONSE_LDMS_RX_Msk 0x18UL 3059 #define USB32DEV_PROT_LMP_LDM_RESPONSE_LDM_RESP_DELAY_Pos 15UL 3060 #define USB32DEV_PROT_LMP_LDM_RESPONSE_LDM_RESP_DELAY_Msk 0x1FFF8000UL 3061 /* USB32DEV_PROT.PROT_EPI_ENHANCE */ 3062 #define USB32DEV_PROT_EPI_ENHANCE_EN_TERM_NUMP0_RTY1_Pos 0UL 3063 #define USB32DEV_PROT_EPI_ENHANCE_EN_TERM_NUMP0_RTY1_Msk 0x1UL 3064 #define USB32DEV_PROT_EPI_ENHANCE_EN_EOB_ZLP_Pos 1UL 3065 #define USB32DEV_PROT_EPI_ENHANCE_EN_EOB_ZLP_Msk 0x2UL 3066 #define USB32DEV_PROT_EPI_ENHANCE_EN_EOB_SHORT_Pos 31UL 3067 #define USB32DEV_PROT_EPI_ENHANCE_EN_EOB_SHORT_Msk 0x80000000UL 3068 /* USB32DEV_PROT.PROT_ENHANCE */ 3069 #define USB32DEV_PROT_ENHANCE_EN_DPH_ERR_DET_Pos 0UL 3070 #define USB32DEV_PROT_ENHANCE_EN_DPH_ERR_DET_Msk 0x1UL 3071 #define USB32DEV_PROT_ENHANCE_DISABLE_STREAM_ERDY_Pos 1UL 3072 #define USB32DEV_PROT_ENHANCE_DISABLE_STREAM_ERDY_Msk 0x2UL 3073 #define USB32DEV_PROT_ENHANCE_STREAM_ERDY_ONLY_DISABLED_ST_Pos 2UL 3074 #define USB32DEV_PROT_ENHANCE_STREAM_ERDY_ONLY_DISABLED_ST_Msk 0x4UL 3075 #define USB32DEV_PROT_ENHANCE_EN_REJECTED_ERDY_Pos 3UL 3076 #define USB32DEV_PROT_ENHANCE_EN_REJECTED_ERDY_Msk 0x8UL 3077 #define USB32DEV_PROT_ENHANCE_DISABLE_SI_MODE_Pos 4UL 3078 #define USB32DEV_PROT_ENHANCE_DISABLE_SI_MODE_Msk 0x10UL 3079 #define USB32DEV_PROT_ENHANCE_EN_EGRS_ISO_SEQ_MATCH_Pos 5UL 3080 #define USB32DEV_PROT_ENHANCE_EN_EGRS_ISO_SEQ_MATCH_Msk 0x20UL 3081 #define USB32DEV_PROT_ENHANCE_ITP_RST_SEQ_NUM_CONDITION_Pos 6UL 3082 #define USB32DEV_PROT_ENHANCE_ITP_RST_SEQ_NUM_CONDITION_Msk 0x3C0UL 3083 #define USB32DEV_PROT_ENHANCE_ITP_PTM_INTR_CONDITION_Pos 10UL 3084 #define USB32DEV_PROT_ENHANCE_ITP_PTM_INTR_CONDITION_Msk 0x3C00UL 3085 #define USB32DEV_PROT_ENHANCE_INGRESS_FULL_COUNTER_Pos 14UL 3086 #define USB32DEV_PROT_ENHANCE_INGRESS_FULL_COUNTER_Msk 0x1C000UL 3087 #define USB32DEV_PROT_ENHANCE_STREAM_READ_DIR_Pos 17UL 3088 #define USB32DEV_PROT_ENHANCE_STREAM_READ_DIR_Msk 0x20000UL 3089 #define USB32DEV_PROT_ENHANCE_STREAM_READ_END_POINT_Pos 18UL 3090 #define USB32DEV_PROT_ENHANCE_STREAM_READ_END_POINT_Msk 0x3C0000UL 3091 #define USB32DEV_PROT_ENHANCE_STREAM_READ_STATE_Pos 22UL 3092 #define USB32DEV_PROT_ENHANCE_STREAM_READ_STATE_Msk 0x3FC00000UL 3093 #define USB32DEV_PROT_ENHANCE_RESET_SCH_TYPE1_Pos 30UL 3094 #define USB32DEV_PROT_ENHANCE_RESET_SCH_TYPE1_Msk 0x40000000UL 3095 #define USB32DEV_PROT_ENHANCE_RESET_SCH_TYPE2_Pos 31UL 3096 #define USB32DEV_PROT_ENHANCE_RESET_SCH_TYPE2_Msk 0x80000000UL 3097 3098 3099 /* USB32DEV_PHYSS_USB40PHY_TOP.TOP_CTRL_0 */ 3100 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_PWR_GOOD_CORE_RX_Pos 1UL 3101 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_PWR_GOOD_CORE_RX_Msk 0x2UL 3102 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_PWR_GOOD_CORE_PLL_Pos 2UL 3103 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_PWR_GOOD_CORE_PLL_Msk 0x4UL 3104 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_VBUS_Pos 3UL 3105 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_VBUS_Msk 0x8UL 3106 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_PLL_RSTB_Pos 4UL 3107 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_PLL_RSTB_Msk 0x10UL 3108 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_LFPS_CLK_DIV_Pos 8UL 3109 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_LFPS_CLK_DIV_Msk 0xF00UL 3110 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_TX_SHIFT_CLK_DIV_Pos 12UL 3111 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_TX_SHIFT_CLK_DIV_Msk 0xF000UL 3112 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_PHYSS_EN_Pos 16UL 3113 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_PHYSS_EN_Msk 0x10000UL 3114 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_RX_EQ_TRAINING_FLAG_Pos 17UL 3115 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_REG_RX_EQ_TRAINING_FLAG_Msk 0x20000UL 3116 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_PCLK_EN_Pos 19UL 3117 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_PCLK_EN_Msk 0x80000UL 3118 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_RATE_CHANGE_DONE_Pos 20UL 3119 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_RATE_CHANGE_DONE_Msk 0x100000UL 3120 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_RATE_Pos 21UL 3121 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_RATE_Msk 0x600000UL 3122 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_PLL_VCCD_LEVELSHIFT_EN_Pos 24UL 3123 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_PLL_VCCD_LEVELSHIFT_EN_Msk 0x1000000UL 3124 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_PLL_VHS_LEVELSHIFT_EN_Pos 25UL 3125 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_PLL_VHS_LEVELSHIFT_EN_Msk 0x2000000UL 3126 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_GEN1_BERT_EN_Pos 28UL 3127 #define USB32DEV_PHYSS_USB40PHY_TOP_CTRL_0_GEN1_BERT_EN_Msk 0x10000000UL 3128 /* USB32DEV_PHYSS_USB40PHY_TOP.PCS_CTRL_0 */ 3129 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN2_HDR_CORRECTION_DISABLE_Pos 0UL 3130 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN2_HDR_CORRECTION_DISABLE_Msk 0x1UL 3131 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN2_SKP_CORRECTION_DISABLE_Pos 1UL 3132 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN2_SKP_CORRECTION_DISABLE_Msk 0x2UL 3133 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN2_SDS_CORRECTION_DISABLE_Pos 2UL 3134 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN2_SDS_CORRECTION_DISABLE_Msk 0x4UL 3135 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_CLEAR_ERR_CNTR_Pos 3UL 3136 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_CLEAR_ERR_CNTR_Msk 0x8UL 3137 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_ONEZERO_CNT_Pos 4UL 3138 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_ONEZERO_CNT_Msk 0xF0UL 3139 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_TX_SER_EN_DLY_Pos 11UL 3140 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_TX_SER_EN_DLY_Msk 0x3800UL 3141 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN1_EB_HALF_DEPTH_Pos 24UL 3142 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN1_EB_HALF_DEPTH_Msk 0xF000000UL 3143 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN2_EB_HALF_DEPTH_Pos 28UL 3144 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_CTRL_0_GEN2_EB_HALF_DEPTH_Msk 0xF0000000UL 3145 /* USB32DEV_PHYSS_USB40PHY_TOP.PCS_STATUS */ 3146 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_REG_PCS_RX_ALIGNED_Pos 0UL 3147 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_REG_PCS_RX_ALIGNED_Msk 0x1UL 3148 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_REG_PCS_RX_MATCHED_CNT_Pos 1UL 3149 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_REG_PCS_RX_MATCHED_CNT_Msk 0xFEUL 3150 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_REG_PIPE_RATE_Pos 8UL 3151 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_REG_PIPE_RATE_Msk 0x300UL 3152 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_ALIGNER_STATE_Pos 12UL 3153 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_ALIGNER_STATE_Msk 0x7000UL 3154 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_CDR_LOCK_TO_REFERENCE_Pos 15UL 3155 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_STATUS_CDR_LOCK_TO_REFERENCE_Msk 0x8000UL 3156 /* USB32DEV_PHYSS_USB40PHY_TOP.PCS_SPARE */ 3157 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_SPARE_REG_DFT_Pos 0UL 3158 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_SPARE_REG_DFT_Msk 0xFFFUL 3159 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_SPARE_REG_SPARE0_Pos 12UL 3160 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_SPARE_REG_SPARE0_Msk 0xFFF000UL 3161 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_SPARE_REG_SPARE1_Pos 24UL 3162 #define USB32DEV_PHYSS_USB40PHY_TOP_PCS_SPARE_REG_SPARE1_Msk 0xFF000000UL 3163 /* USB32DEV_PHYSS_USB40PHY_TOP.ERR_STATUS */ 3164 #define USB32DEV_PHYSS_USB40PHY_TOP_ERR_STATUS_HDR_ERR_CORRECTED_CNT_Pos 0UL 3165 #define USB32DEV_PHYSS_USB40PHY_TOP_ERR_STATUS_HDR_ERR_CORRECTED_CNT_Msk 0xFFFFUL 3166 #define USB32DEV_PHYSS_USB40PHY_TOP_ERR_STATUS_SKP_ERR_CORRECTED_CNT_Pos 16UL 3167 #define USB32DEV_PHYSS_USB40PHY_TOP_ERR_STATUS_SKP_ERR_CORRECTED_CNT_Msk 0x3FF0000UL 3168 #define USB32DEV_PHYSS_USB40PHY_TOP_ERR_STATUS_SDS_ERR_CORRECTED_CNT_Pos 26UL 3169 #define USB32DEV_PHYSS_USB40PHY_TOP_ERR_STATUS_SDS_ERR_CORRECTED_CNT_Msk 0x3C000000UL 3170 /* USB32DEV_PHYSS_USB40PHY_TOP.PIPE_OVERRIDE_0 */ 3171 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_PIPE_ENCDEC_BYPASS_OVRD_EN_Pos 0UL 3172 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_PIPE_ENCDEC_BYPASS_OVRD_EN_Msk 0x1UL 3173 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_PIPE_ENCDEC_BYPASS_OVRD_VALUE_Pos 1UL 3174 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_PIPE_ENCDEC_BYPASS_OVRD_VALUE_Msk 0x2UL 3175 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_EB_MODE_OVRD_EN_Pos 5UL 3176 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_EB_MODE_OVRD_EN_Msk 0x20UL 3177 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_EB_MODE_OVRD_VALUE_Pos 6UL 3178 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_EB_MODE_OVRD_VALUE_Msk 0x40UL 3179 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_DETECTRX_OVRD_EN_Pos 7UL 3180 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_DETECTRX_OVRD_EN_Msk 0x80UL 3181 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_DETECTRX_OVRD_VALUE_Pos 8UL 3182 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_DETECTRX_OVRD_VALUE_Msk 0x100UL 3183 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_ELECTIDLE_OVRD_EN_Pos 9UL 3184 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_ELECTIDLE_OVRD_EN_Msk 0x200UL 3185 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_ELECTIDLE_OVRD_VALUE_Pos 10UL 3186 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_ELECTIDLE_OVRD_VALUE_Msk 0x400UL 3187 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_ONE_ZEROS_OVRD_EN_Pos 11UL 3188 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_ONE_ZEROS_OVRD_EN_Msk 0x800UL 3189 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_ONE_ZEROS_OVRD_VALUE_Pos 12UL 3190 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_TX_ONE_ZEROS_OVRD_VALUE_Msk 0x1000UL 3191 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_RX_POLARITY_OVRD_EN_Pos 13UL 3192 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_RX_POLARITY_OVRD_EN_Msk 0x2000UL 3193 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_RX_POLARITY_OVRD_VALUE_Pos 14UL 3194 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_RX_POLARITY_OVRD_VALUE_Msk 0x4000UL 3195 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_RX_EQ_TRAINING_OVRD_EN_Pos 15UL 3196 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_RX_EQ_TRAINING_OVRD_EN_Msk 0x8000UL 3197 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_RX_EQ_TRAINING_OVRD_VALUE_Pos 16UL 3198 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_RX_EQ_TRAINING_OVRD_VALUE_Msk 0x10000UL 3199 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_POWER_DOWN_OVRD_EN_Pos 17UL 3200 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_POWER_DOWN_OVRD_EN_Msk 0x20000UL 3201 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_POWER_DOWN_OVRD_VALUE_Pos 18UL 3202 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_POWER_DOWN_OVRD_VALUE_Msk 0x1C0000UL 3203 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_BLOCK_ALIGN_CONTROL_OVRD_EN_Pos 30UL 3204 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_BLOCK_ALIGN_CONTROL_OVRD_EN_Msk 0x40000000UL 3205 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_BLOCK_ALIGN_CONTROL_OVRD_VALUE_Pos 31UL 3206 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_OVERRIDE_0_REG_PIPE_BLOCK_ALIGN_CONTROL_OVRD_VALUE_Msk 0x80000000UL 3207 /* USB32DEV_PHYSS_USB40PHY_TOP.PIPE_STATUS */ 3208 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_RXVALID_Pos 0UL 3209 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_RXVALID_Msk 0x1UL 3210 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_PHY_STATUS_Pos 1UL 3211 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_PHY_STATUS_Msk 0x2UL 3212 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_RX_ELECIDLE_Pos 2UL 3213 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_RX_ELECIDLE_Msk 0x4UL 3214 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_RX_STATUS_Pos 3UL 3215 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_RX_STATUS_Msk 0x38UL 3216 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_POWER_PRESENT_Pos 6UL 3217 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_REG_PIPE_POWER_PRESENT_Msk 0x40UL 3218 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_RX_TERMINATION_Pos 7UL 3219 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_RX_TERMINATION_Msk 0x80UL 3220 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_RX_STANDBY_Pos 8UL 3221 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_RX_STANDBY_Msk 0x100UL 3222 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_PHY_IN_P0_Pos 9UL 3223 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_PHY_IN_P0_Msk 0x200UL 3224 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_PHY_IN_P1_Pos 10UL 3225 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_PHY_IN_P1_Msk 0x400UL 3226 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_PHY_IN_P2_Pos 11UL 3227 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_PHY_IN_P2_Msk 0x800UL 3228 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_PHY_IN_P3_Pos 12UL 3229 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_STATUS_PHY_IN_P3_Msk 0x1000UL 3230 /* USB32DEV_PHYSS_USB40PHY_TOP.INTR0 */ 3231 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RATE_CHANGE_Pos 0UL 3232 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RATE_CHANGE_Msk 0x1UL 3233 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_P0_CHANGE_Pos 1UL 3234 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_P0_CHANGE_Msk 0x2UL 3235 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_P1_CHANGE_Pos 2UL 3236 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_P1_CHANGE_Msk 0x4UL 3237 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_P2_CHANGE_Pos 3UL 3238 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_P2_CHANGE_Msk 0x8UL 3239 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_P3_CHANGE_Pos 4UL 3240 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_P3_CHANGE_Msk 0x10UL 3241 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_TX_SFT_REG_WDONE_Pos 5UL 3242 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_TX_SFT_REG_WDONE_Msk 0x20UL 3243 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_PLL_LOCKED_Pos 6UL 3244 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_PLL_LOCKED_Msk 0x40UL 3245 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_POWER_GOOD_RXA_Pos 7UL 3246 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_POWER_GOOD_RXA_Msk 0x80UL 3247 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_POWER_GOOD_RXCK_Pos 8UL 3248 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_POWER_GOOD_RXCK_Msk 0x100UL 3249 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_POWER_GOOD_RXD_Pos 9UL 3250 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_POWER_GOOD_RXD_Msk 0x200UL 3251 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_OSA_ERROR_Pos 10UL 3252 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_OSA_ERROR_Msk 0x400UL 3253 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_OSA_ALL_DONE_Pos 11UL 3254 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_OSA_ALL_DONE_Msk 0x800UL 3255 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_EQ_START_Pos 12UL 3256 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_EQ_START_Msk 0x1000UL 3257 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_EYE_HIGHT_DONE_Pos 13UL 3258 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_EYE_HIGHT_DONE_Msk 0x2000UL 3259 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_EYE_MON_DONE_Pos 14UL 3260 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_RX_EYE_MON_DONE_Msk 0x4000UL 3261 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PLL_LOCKED_Pos 15UL 3262 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PLL_LOCKED_Msk 0x8000UL 3263 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PLL_PWR_GOOD_LCPLL_Pos 16UL 3264 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PLL_PWR_GOOD_LCPLL_Msk 0x10000UL 3265 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PLL_PWR_GOOD_REF_Pos 17UL 3266 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PLL_PWR_GOOD_REF_Msk 0x20000UL 3267 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PLL_PWR_GOOD_DIG_Pos 18UL 3268 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PLL_PWR_GOOD_DIG_Msk 0x40000UL 3269 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_RX_ALIGNER_LOCK_Pos 19UL 3270 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_RX_ALIGNER_LOCK_Msk 0x80000UL 3271 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_RX_DETECTED_Pos 20UL 3272 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_RX_DETECTED_Msk 0x100000UL 3273 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_DECODE_ERR_Pos 21UL 3274 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_DECODE_ERR_Msk 0x200000UL 3275 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_EB_OVERFLOW_Pos 22UL 3276 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_EB_OVERFLOW_Msk 0x400000UL 3277 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_EB_UNDERFLOW_Pos 23UL 3278 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_PCS_EB_UNDERFLOW_Msk 0x800000UL 3279 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_LOOPBACK_LOCK_Pos 24UL 3280 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_LOOPBACK_LOCK_Msk 0x1000000UL 3281 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_LOOPBACK_DONE_Pos 25UL 3282 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_LOOPBACK_DONE_Msk 0x2000000UL 3283 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_TX_IMP_CAL_DONE_Pos 26UL 3284 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_REG_INT_TX_IMP_CAL_DONE_Msk 0x4000000UL 3285 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SAR_DONE_Pos 27UL 3286 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SAR_DONE_Msk 0x8000000UL 3287 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_RX_TERMINATION_CHANGE_Pos 28UL 3288 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_RX_TERMINATION_CHANGE_Msk 0x10000000UL 3289 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_RX_STANDBY_CHANGE_Pos 29UL 3290 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_RX_STANDBY_CHANGE_Msk 0x20000000UL 3291 /* USB32DEV_PHYSS_USB40PHY_TOP.INTR0_SET */ 3292 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RATE_CHANGE_Pos 0UL 3293 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RATE_CHANGE_Msk 0x1UL 3294 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_P0_CHANGE_Pos 1UL 3295 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_P0_CHANGE_Msk 0x2UL 3296 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_P1_CHANGE_Pos 2UL 3297 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_P1_CHANGE_Msk 0x4UL 3298 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_P2_CHANGE_Pos 3UL 3299 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_P2_CHANGE_Msk 0x8UL 3300 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_P3_CHANGE_Pos 4UL 3301 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_P3_CHANGE_Msk 0x10UL 3302 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_TX_SFT_REG_WDONE_Pos 5UL 3303 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_TX_SFT_REG_WDONE_Msk 0x20UL 3304 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_PLL_LOCKED_Pos 6UL 3305 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_PLL_LOCKED_Msk 0x40UL 3306 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_POWER_GOOD_RXA_Pos 7UL 3307 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_POWER_GOOD_RXA_Msk 0x80UL 3308 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_POWER_GOOD_RXCK_Pos 8UL 3309 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_POWER_GOOD_RXCK_Msk 0x100UL 3310 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_POWER_GOOD_RXD_Pos 9UL 3311 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_POWER_GOOD_RXD_Msk 0x200UL 3312 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_OSA_ERROR_Pos 10UL 3313 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_OSA_ERROR_Msk 0x400UL 3314 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_OSA_ALL_DONE_Pos 11UL 3315 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_OSA_ALL_DONE_Msk 0x800UL 3316 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_EQ_START_Pos 12UL 3317 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_EQ_START_Msk 0x1000UL 3318 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_EYE_HIGHT_DONE_Pos 13UL 3319 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_EYE_HIGHT_DONE_Msk 0x2000UL 3320 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_EYE_MON_DONE_Pos 14UL 3321 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_RX_EYE_MON_DONE_Msk 0x4000UL 3322 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PLL_LOCKED_Pos 15UL 3323 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PLL_LOCKED_Msk 0x8000UL 3324 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PLL_PWR_GOOD_LCPLL_Pos 16UL 3325 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PLL_PWR_GOOD_LCPLL_Msk 0x10000UL 3326 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PLL_PWR_GOOD_REF_Pos 17UL 3327 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PLL_PWR_GOOD_REF_Msk 0x20000UL 3328 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PLL_PWR_GOOD_DIG_Pos 18UL 3329 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PLL_PWR_GOOD_DIG_Msk 0x40000UL 3330 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_RX_ALIGNER_LOCK_Pos 19UL 3331 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_RX_ALIGNER_LOCK_Msk 0x80000UL 3332 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_RX_DETECTED_Pos 20UL 3333 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_RX_DETECTED_Msk 0x100000UL 3334 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_DECODE_ERR_Pos 21UL 3335 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_DECODE_ERR_Msk 0x200000UL 3336 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_EB_OVERFLOW_Pos 22UL 3337 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_EB_OVERFLOW_Msk 0x400000UL 3338 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_EB_UNDERFLOW_Pos 23UL 3339 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_PCS_EB_UNDERFLOW_Msk 0x800000UL 3340 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_LOOPBACK_LOCK_Pos 24UL 3341 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_LOOPBACK_LOCK_Msk 0x1000000UL 3342 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_LOOPBACK_DONE_Pos 25UL 3343 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_LOOPBACK_DONE_Msk 0x2000000UL 3344 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_TX_IMP_CAL_DONE_Pos 26UL 3345 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_REG_INT_TX_IMP_CAL_DONE_Msk 0x4000000UL 3346 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_SAR_DONE_Pos 27UL 3347 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_SAR_DONE_Msk 0x8000000UL 3348 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_RX_TERMINATION_CHANGE_Pos 28UL 3349 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_RX_TERMINATION_CHANGE_Msk 0x10000000UL 3350 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_RX_STANDBY_CHANGE_Pos 29UL 3351 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_SET_RX_STANDBY_CHANGE_Msk 0x20000000UL 3352 /* USB32DEV_PHYSS_USB40PHY_TOP.INTR0_MASK */ 3353 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RATE_CHANGE_MASK_Pos 0UL 3354 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RATE_CHANGE_MASK_Msk 0x1UL 3355 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_P0_CHANGE_MASK_Pos 1UL 3356 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_P0_CHANGE_MASK_Msk 0x2UL 3357 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_P1_CHANGE_MASK_Pos 2UL 3358 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_P1_CHANGE_MASK_Msk 0x4UL 3359 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_P2_CHANGE_MASK_Pos 3UL 3360 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_P2_CHANGE_MASK_Msk 0x8UL 3361 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_P3_CHANGE_MASK_Pos 4UL 3362 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_P3_CHANGE_MASK_Msk 0x10UL 3363 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_TX_SFT_REG_WDONE_MASK_Pos 5UL 3364 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_TX_SFT_REG_WDONE_MASK_Msk 0x20UL 3365 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_PLL_LOCKED_MASK_Pos 6UL 3366 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_PLL_LOCKED_MASK_Msk 0x40UL 3367 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_POWER_GOOD_RXA_MASK_Pos 7UL 3368 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_POWER_GOOD_RXA_MASK_Msk 0x80UL 3369 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_POWER_GOOD_RXCK_MASK_Pos 8UL 3370 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_POWER_GOOD_RXCK_MASK_Msk 0x100UL 3371 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_POWER_GOOD_RXD_MASK_Pos 9UL 3372 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_POWER_GOOD_RXD_MASK_Msk 0x200UL 3373 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_OSA_ERROR_MASK_Pos 10UL 3374 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_OSA_ERROR_MASK_Msk 0x400UL 3375 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_OSA_ALL_DONE_MASK_Pos 11UL 3376 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_OSA_ALL_DONE_MASK_Msk 0x800UL 3377 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_EQ_START_MASK_Pos 12UL 3378 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_EQ_START_MASK_Msk 0x1000UL 3379 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_EYE_HIGHT_DONE_MASK_Pos 13UL 3380 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_EYE_HIGHT_DONE_MASK_Msk 0x2000UL 3381 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_EYE_MON_DONE_MASK_Pos 14UL 3382 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_RX_EYE_MON_DONE_MASK_Msk 0x4000UL 3383 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PLL_LOCKED_MASK_Pos 15UL 3384 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PLL_LOCKED_MASK_Msk 0x8000UL 3385 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PLL_PWR_GOOD_LCPLL_MASK_Pos 16UL 3386 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PLL_PWR_GOOD_LCPLL_MASK_Msk 0x10000UL 3387 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PLL_PWR_GOOD_REF_MASK_Pos 17UL 3388 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PLL_PWR_GOOD_REF_MASK_Msk 0x20000UL 3389 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PLL_PWR_GOOD_DIG_MASK_Pos 18UL 3390 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PLL_PWR_GOOD_DIG_MASK_Msk 0x40000UL 3391 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_RX_ALIGNER_LOCK_MASK_Pos 19UL 3392 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_RX_ALIGNER_LOCK_MASK_Msk 0x80000UL 3393 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_RX_DETECTED_MASK_Pos 20UL 3394 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_RX_DETECTED_MASK_Msk 0x100000UL 3395 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_DECODE_ERR_MASK_Pos 21UL 3396 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_DECODE_ERR_MASK_Msk 0x200000UL 3397 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_EB_OVERFLOW_MASK_Pos 22UL 3398 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_EB_OVERFLOW_MASK_Msk 0x400000UL 3399 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_EB_UNDERFLOW_MASK_Pos 23UL 3400 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_PCS_EB_UNDERFLOW_MASK_Msk 0x800000UL 3401 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_LOOPBACK_LOCK_MASK_Pos 24UL 3402 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_LOOPBACK_LOCK_MASK_Msk 0x1000000UL 3403 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_LOOPBACK_DONE_MASK_Pos 25UL 3404 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_LOOPBACK_DONE_MASK_Msk 0x2000000UL 3405 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_TX_IMP_CAL_DONE_Pos 26UL 3406 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_REG_INT_TX_IMP_CAL_DONE_Msk 0x4000000UL 3407 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_SAR_DONE_Pos 27UL 3408 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_SAR_DONE_Msk 0x8000000UL 3409 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_RX_TERMINATION_CHANGE_Pos 28UL 3410 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_RX_TERMINATION_CHANGE_Msk 0x10000000UL 3411 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_RX_STANDBY_CHANGE_Pos 29UL 3412 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASK_RX_STANDBY_CHANGE_Msk 0x20000000UL 3413 /* USB32DEV_PHYSS_USB40PHY_TOP.INTR0_MASKED */ 3414 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RATE_CHANGE_MASKD_Pos 0UL 3415 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RATE_CHANGE_MASKD_Msk 0x1UL 3416 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_P0_CHANGE_MASKD_Pos 1UL 3417 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_P0_CHANGE_MASKD_Msk 0x2UL 3418 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_P1_CHANGE_MASKD_Pos 2UL 3419 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_P1_CHANGE_MASKD_Msk 0x4UL 3420 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_P2_CHANGE_MASKD_Pos 3UL 3421 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_P2_CHANGE_MASKD_Msk 0x8UL 3422 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_P3_CHANGE_MASKD_Pos 4UL 3423 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_P3_CHANGE_MASKD_Msk 0x10UL 3424 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_TX_SFT_REG_WDONE_MASKD_Pos 5UL 3425 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_TX_SFT_REG_WDONE_MASKD_Msk 0x20UL 3426 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_PLL_LOCKED_MASKD_Pos 6UL 3427 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_PLL_LOCKED_MASKD_Msk 0x40UL 3428 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_POWER_GOOD_RXA_MASKD_Pos 7UL 3429 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_POWER_GOOD_RXA_MASKD_Msk 0x80UL 3430 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_POWER_GOOD_RXCK_MASKD_Pos 8UL 3431 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_POWER_GOOD_RXCK_MASKD_Msk 0x100UL 3432 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_POWER_GOOD_RXD_MASKD_Pos 9UL 3433 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_POWER_GOOD_RXD_MASKD_Msk 0x200UL 3434 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_OSA_ERROR_MASKD_Pos 10UL 3435 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_OSA_ERROR_MASKD_Msk 0x400UL 3436 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_OSA_ALL_DONE_MASKD_Pos 11UL 3437 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_OSA_ALL_DONE_MASKD_Msk 0x800UL 3438 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_EQ_START_MASKD_Pos 12UL 3439 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_EQ_START_MASKD_Msk 0x1000UL 3440 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_EYE_HIGHT_DONE_MASKD_Pos 13UL 3441 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_EYE_HIGHT_DONE_MASKD_Msk 0x2000UL 3442 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_EYE_MON_DONE_MASKD_Pos 14UL 3443 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_RX_EYE_MON_DONE_MASKD_Msk 0x4000UL 3444 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PLL_LOCKED_MASKD_Pos 15UL 3445 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PLL_LOCKED_MASKD_Msk 0x8000UL 3446 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PLL_PWR_GOOD_LCPLL_MASKD_Pos 16UL 3447 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PLL_PWR_GOOD_LCPLL_MASKD_Msk 0x10000UL 3448 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PLL_PWR_GOOD_REF_MASKD_Pos 17UL 3449 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PLL_PWR_GOOD_REF_MASKD_Msk 0x20000UL 3450 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PLL_PWR_GOOD_DIG_MASKD_Pos 18UL 3451 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PLL_PWR_GOOD_DIG_MASKD_Msk 0x40000UL 3452 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_RX_ALIGNER_LOCK_MASKD_Pos 19UL 3453 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_RX_ALIGNER_LOCK_MASKD_Msk 0x80000UL 3454 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_RX_DETECTED_MASKD_Pos 20UL 3455 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_RX_DETECTED_MASKD_Msk 0x100000UL 3456 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_DECODE_ERR_MASKD_Pos 21UL 3457 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_DECODE_ERR_MASKD_Msk 0x200000UL 3458 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_EB_OVERFLOW_MASKD_Pos 22UL 3459 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_EB_OVERFLOW_MASKD_Msk 0x400000UL 3460 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_EB_UNDERFLOW_MASKD_Pos 23UL 3461 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_PCS_EB_UNDERFLOW_MASKD_Msk 0x800000UL 3462 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_LOOPBACK_LOCK_MASKD_Pos 24UL 3463 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_LOOPBACK_LOCK_MASKD_Msk 0x1000000UL 3464 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_LOOPBACK_DONE_MASKD_Pos 25UL 3465 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_LOOPBACK_DONE_MASKD_Msk 0x2000000UL 3466 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_TX_IMP_CAL_DONE_Pos 26UL 3467 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_REG_INT_TX_IMP_CAL_DONE_Msk 0x4000000UL 3468 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_SAR_DONE_Pos 27UL 3469 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_SAR_DONE_Msk 0x8000000UL 3470 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_RX_TERMINATION_CHANGE_Pos 28UL 3471 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_RX_TERMINATION_CHANGE_Msk 0x10000000UL 3472 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_RX_STANDBY_CHANGE_Pos 29UL 3473 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR0_MASKED_RX_STANDBY_CHANGE_Msk 0x20000000UL 3474 /* USB32DEV_PHYSS_USB40PHY_TOP.INTR1 */ 3475 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR1_REG_INT_RX_LFPSDET_OUT_Pos 0UL 3476 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR1_REG_INT_RX_LFPSDET_OUT_Msk 0x1UL 3477 /* USB32DEV_PHYSS_USB40PHY_TOP.INTR1_SET */ 3478 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR1_SET_REG_INT_RX_LFPSDET_OUT_Pos 0UL 3479 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR1_SET_REG_INT_RX_LFPSDET_OUT_Msk 0x1UL 3480 /* USB32DEV_PHYSS_USB40PHY_TOP.INTR1_MASK */ 3481 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR1_MASK_REG_INT_RX_LFPSDET_OUT_MASK_Pos 0UL 3482 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR1_MASK_REG_INT_RX_LFPSDET_OUT_MASK_Msk 0x1UL 3483 /* USB32DEV_PHYSS_USB40PHY_TOP.INTR1_MASKED */ 3484 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR1_MASKED_REG_INT_RX_LFPSDET_OUT_MASKD_Pos 0UL 3485 #define USB32DEV_PHYSS_USB40PHY_TOP_INTR1_MASKED_REG_INT_RX_LFPSDET_OUT_MASKD_Msk 0x1UL 3486 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CTRL_0 */ 3487 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_EN_Pos 0UL 3488 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_EN_Msk 0x1UL 3489 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_DRV_EN_Pos 1UL 3490 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_DRV_EN_Msk 0x2UL 3491 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_CML2CMOS_EN_Pos 2UL 3492 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_CML2CMOS_EN_Msk 0x4UL 3493 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_TX_SERIALIZER_RST_Pos 3UL 3494 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_TX_SERIALIZER_RST_Msk 0x8UL 3495 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VCPREG_EN_Pos 4UL 3496 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VCPREG_EN_Msk 0x10UL 3497 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VCPREG_SEL_Pos 5UL 3498 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VCPREG_SEL_Msk 0x1E0UL 3499 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_CPCLK_SEL_Pos 9UL 3500 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_CPCLK_SEL_Msk 0x200UL 3501 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VREG_CLK_EN_Pos 10UL 3502 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VREG_CLK_EN_Msk 0x400UL 3503 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VREG_CLK_SEL_Pos 11UL 3504 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VREG_CLK_SEL_Msk 0x7800UL 3505 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VREG_DRV_EN_Pos 15UL 3506 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VREG_DRV_EN_Msk 0x8000UL 3507 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VREG_DRV_SEL_Pos 16UL 3508 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_VREG_DRV_SEL_Msk 0xF0000UL 3509 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_PULL_DN_Pos 20UL 3510 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_PULL_DN_Msk 0x100000UL 3511 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_LOOPBK_EN_Pos 21UL 3512 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_LOOPBK_EN_Msk 0x200000UL 3513 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_DCD_CTRL_Pos 22UL 3514 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_DCD_CTRL_Msk 0x3C00000UL 3515 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_DETECTRX_TRIM_Pos 26UL 3516 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_DETECTRX_TRIM_Msk 0xC000000UL 3517 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_ELECIDLE_DRV_Pos 28UL 3518 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_0_REG_TX_AFE_TX_ELECIDLE_DRV_Msk 0x30000000UL 3519 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CTRL_1 */ 3520 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_TX_ICAL_TRIM_Pos 0UL 3521 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_TX_ICAL_TRIM_Msk 0x3FUL 3522 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_BURNIN_EN_Pos 7UL 3523 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_BURNIN_EN_Msk 0x80UL 3524 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_TX_ADFT_EN_Pos 8UL 3525 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_TX_ADFT_EN_Msk 0x100UL 3526 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_TX_ADFT_Pos 9UL 3527 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_TX_ADFT_Msk 0x3E00UL 3528 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_TX_DDFT_Pos 14UL 3529 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CTRL_1_REG_TX_AFE_TX_DDFT_Msk 0x7C000UL 3530 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_RXDETECT_CNT */ 3531 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_RXDETECT_CNT_RXDETECT_WAIT_CNT_Pos 0UL 3532 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_RXDETECT_CNT_RXDETECT_WAIT_CNT_Msk 0xFFUL 3533 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_RXDETECT_CNT_PULLUP_ASSERT_DLY_Pos 8UL 3534 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_RXDETECT_CNT_PULLUP_ASSERT_DLY_Msk 0xFF00UL 3535 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_OVERRIDE_0 */ 3536 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_PULL_UP_OVRD_EN_Pos 0UL 3537 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_PULL_UP_OVRD_EN_Msk 0x1UL 3538 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_PULL_UP_OVRD_VALUE_Pos 1UL 3539 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_PULL_UP_OVRD_VALUE_Msk 0x2UL 3540 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_SER_EN_OVRD_EN_Pos 2UL 3541 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_SER_EN_OVRD_EN_Msk 0x4UL 3542 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_SER_EN_OVRD_VALUE_Pos 3UL 3543 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_SER_EN_OVRD_VALUE_Msk 0x8UL 3544 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_HSCLK_DRV_EN_OVRD_EN_Pos 4UL 3545 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_HSCLK_DRV_EN_OVRD_EN_Msk 0x10UL 3546 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_HSCLK_DRV_EN_OVRD_VALUE_Pos 5UL 3547 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_HSCLK_DRV_EN_OVRD_VALUE_Msk 0x20UL 3548 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_TX_AFE_SER_RESET_OVRD_EN_Pos 6UL 3549 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_TX_AFE_SER_RESET_OVRD_EN_Msk 0x40UL 3550 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_TX_AFE_SER_RESET_OVRD_VALUE_Pos 7UL 3551 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_TX_AFE_SER_RESET_OVRD_VALUE_Msk 0x80UL 3552 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_DETECTRX_OVRD_EN_Pos 8UL 3553 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_DETECTRX_OVRD_EN_Msk 0x100UL 3554 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_DETECTRX_OVRD_VALUE_Pos 9UL 3555 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_DETECTRX_OVRD_VALUE_Msk 0x200UL 3556 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_ELECIDLE_OVRD_EN_Pos 10UL 3557 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_ELECIDLE_OVRD_EN_Msk 0x400UL 3558 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_ELECIDLE_OVRD_VALUE_Pos 11UL 3559 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_ELECIDLE_OVRD_VALUE_Msk 0x800UL 3560 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_LFPS_OVRD_EN_Pos 12UL 3561 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_LFPS_OVRD_EN_Msk 0x1000UL 3562 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_LFPS_OVRD_VALUE_Pos 13UL 3563 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_LFPS_OVRD_VALUE_Msk 0x2000UL 3564 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_ZTRIM_OVRD_EN_Pos 16UL 3565 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_ZTRIM_OVRD_EN_Msk 0x10000UL 3566 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_ZTRIM_OVRD_VALUE_Pos 17UL 3567 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_OVERRIDE_0_REG_TX_AFE_TX_ZTRIM_OVRD_VALUE_Msk 0x3E0000UL 3568 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_DEBUG */ 3569 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_DEBUG_REG_TX_AFE_DDFT_OUT1_Pos 0UL 3570 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_DEBUG_REG_TX_AFE_DDFT_OUT1_Msk 0x1UL 3571 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_DEBUG_REG_TX_AFE_DDFT_OUT2_Pos 1UL 3572 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_DEBUG_REG_TX_AFE_DDFT_OUT2_Msk 0x2UL 3573 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_STATUS */ 3574 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_STATUS_ZCAL_STATUS_Pos 0UL 3575 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_STATUS_ZCAL_STATUS_Msk 0x1UL 3576 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_STATUS_ZCAL_CODE_Pos 1UL 3577 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_STATUS_ZCAL_CODE_Msk 0x3EUL 3578 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_STATUS_ZCAL_COMP_OUT_Pos 6UL 3579 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_STATUS_ZCAL_COMP_OUT_Msk 0x40UL 3580 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_STATUS_TX_DETECTRX_OUT_Pos 7UL 3581 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_STATUS_TX_DETECTRX_OUT_Msk 0x80UL 3582 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_ZTRIM */ 3583 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_EN_Pos 0UL 3584 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_EN_Msk 0x1UL 3585 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_MODE_Pos 1UL 3586 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_MODE_Msk 0x2UL 3587 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_COMP_WAIT_Pos 2UL 3588 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_COMP_WAIT_Msk 0xCUL 3589 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_START_CODE_Pos 4UL 3590 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_START_CODE_Msk 0x1F0UL 3591 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_FINAL_CODE_Pos 9UL 3592 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_FINAL_CODE_Msk 0x3E00UL 3593 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_CURR_STATE_Pos 16UL 3594 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_ZTRIM_ZCAL_CURR_STATE_Msk 0x70000UL 3595 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG */ 3596 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_REG_TX_CFG_WRITE_DONE_Pos 0UL 3597 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_REG_TX_CFG_WRITE_DONE_Msk 0x1UL 3598 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG_SFT_W_0 */ 3599 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_0_REG_TX_CFG_SFT_W_0_Pos 0UL 3600 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_0_REG_TX_CFG_SFT_W_0_Msk 0x3FFFFFUL 3601 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG_SFT_W_1 */ 3602 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_1_REG_TX_CFG_SFT_W_1_Pos 0UL 3603 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_1_REG_TX_CFG_SFT_W_1_Msk 0x3FFFFFUL 3604 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG_SFT_W_2 */ 3605 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_2_REG_TX_CFG_SFT_W_2_Pos 0UL 3606 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_2_REG_TX_CFG_SFT_W_2_Msk 0x3FFFFFUL 3607 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG_SFT_W_3 */ 3608 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_3_REG_TX_CFG_SFT_W_3_Pos 0UL 3609 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_3_REG_TX_CFG_SFT_W_3_Msk 0x3FFFFFUL 3610 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG_SFT_W_4 */ 3611 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_4_REG_TX_CFG_SFT_W_4_Pos 0UL 3612 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_4_REG_TX_CFG_SFT_W_4_Msk 0x3FFFFFUL 3613 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG_SFT_W_5 */ 3614 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_5_REG_TX_CFG_SFT_W_5_Pos 0UL 3615 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_5_REG_TX_CFG_SFT_W_5_Msk 0x3FFFFFUL 3616 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG_SFT_W_6 */ 3617 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_6_REG_TX_CFG_SFT_W_6_Pos 0UL 3618 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_6_REG_TX_CFG_SFT_W_6_Msk 0x3FFFFFUL 3619 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG_SFT_W_7 */ 3620 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_7_REG_TX_CFG_SFT_W_7_Pos 0UL 3621 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_W_7_REG_TX_CFG_SFT_W_7_Msk 0x3FFFFFUL 3622 /* USB32DEV_PHYSS_USB40PHY_TOP.TX_AFE_CFG_SFT_R */ 3623 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_R_REG_TX_CFG_SFT_R_Pos 0UL 3624 #define USB32DEV_PHYSS_USB40PHY_TOP_TX_AFE_CFG_SFT_R_REG_TX_CFG_SFT_R_Msk 0xFFUL 3625 /* USB32DEV_PHYSS_USB40PHY_TOP.ADC */ 3626 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_DAC_CNTRL_Pos 0UL 3627 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_DAC_CNTRL_Msk 0xFFUL 3628 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_MID_VAL_Pos 8UL 3629 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_MID_VAL_Msk 0xFF00UL 3630 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_LDO_TRIM_Pos 16UL 3631 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_LDO_TRIM_Msk 0xF0000UL 3632 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_LDO_EN_Pos 20UL 3633 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_LDO_EN_Msk 0x100000UL 3634 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_ISO_N_Pos 21UL 3635 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_ISO_N_Msk 0x200000UL 3636 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_PD_LV_Pos 22UL 3637 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_PD_LV_Msk 0x400000UL 3638 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_DFT_MUXSEL_Pos 23UL 3639 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_DFT_MUXSEL_Msk 0x800000UL 3640 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_VSEL_Pos 24UL 3641 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_VSEL_Msk 0x7000000UL 3642 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_VREF_DAC_SEL_Pos 27UL 3643 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_VREF_DAC_SEL_Msk 0x18000000UL 3644 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_SAR_EN_Pos 29UL 3645 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_SAR_EN_Msk 0x20000000UL 3646 /* USB32DEV_PHYSS_USB40PHY_TOP.ADC_STATUS */ 3647 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_STATUS_CMP_OUT_Pos 0UL 3648 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_STATUS_CMP_OUT_Msk 0x1UL 3649 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_STATUS_SAR_OUT_Pos 8UL 3650 #define USB32DEV_PHYSS_USB40PHY_TOP_ADC_STATUS_SAR_OUT_Msk 0xFF00UL 3651 /* USB32DEV_PHYSS_USB40PHY_TOP.PHYSS_LOOPBACK_CTRL_0 */ 3652 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_EN_Pos 0UL 3653 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_EN_Msk 0x1UL 3654 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_NO_AFE_Pos 1UL 3655 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_NO_AFE_Msk 0x2UL 3656 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_START_PTTN_Pos 2UL 3657 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_START_PTTN_Msk 0x4UL 3658 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_NO_8B_10B_Pos 3UL 3659 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_NO_8B_10B_Msk 0x8UL 3660 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_PTTN_Pos 4UL 3661 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_PTTN_Msk 0x70UL 3662 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_NO_RX_Pos 8UL 3663 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_LOOPBACK_NO_RX_Msk 0x100UL 3664 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_TX_ONE_ZERO_Pos 9UL 3665 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_TX_ONE_ZERO_Msk 0x200UL 3666 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_SAMPLE_RX_AFE_OUT_Pos 10UL 3667 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_CTRL_0_SAMPLE_RX_AFE_OUT_Msk 0x400UL 3668 /* USB32DEV_PHYSS_USB40PHY_TOP.PHYSS_LOOPBACK_DEBUG_0 */ 3669 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_DEBUG_0_RX_AFE_DATA_0_Pos 0UL 3670 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_DEBUG_0_RX_AFE_DATA_0_Msk 0xFFFFFFFFUL 3671 /* USB32DEV_PHYSS_USB40PHY_TOP.PHYSS_LOOPBACK_DEBUG_1 */ 3672 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_DEBUG_1_RX_AFE_DATA_1_Pos 0UL 3673 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_DEBUG_1_RX_AFE_DATA_1_Msk 0xFFFFFFFFUL 3674 /* USB32DEV_PHYSS_USB40PHY_TOP.PHYSS_LOOPBACK_STATUS_1 */ 3675 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_ERR_COUNT_Pos 0UL 3676 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_ERR_COUNT_Msk 0xFFFFUL 3677 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_STATUS_Pos 16UL 3678 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_STATUS_Msk 0x30000UL 3679 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_DONE_Pos 18UL 3680 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_DONE_Msk 0x40000UL 3681 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_GEN_STATE_Pos 20UL 3682 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_GEN_STATE_Msk 0x300000UL 3683 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_CHK_STATE_Pos 22UL 3684 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_STATUS_1_LOOPBACK_CHK_STATE_Msk 0xC00000UL 3685 /* USB32DEV_PHYSS_USB40PHY_TOP.PHYSS_LOOPBACK_USER_0 */ 3686 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_USER_0_REG_LOOPBACK_USER_0_Pos 0UL 3687 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_USER_0_REG_LOOPBACK_USER_0_Msk 0xFFFFFFFFUL 3688 /* USB32DEV_PHYSS_USB40PHY_TOP.PHYSS_LOOPBACK_USER_1 */ 3689 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_USER_1_REG_LOOPBACK_USER_1_Pos 0UL 3690 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_LOOPBACK_USER_1_REG_LOOPBACK_USER_1_Msk 0xFFFFFFFFUL 3691 /* USB32DEV_PHYSS_USB40PHY_TOP.PHYSS_DDFT_MUX_SEL */ 3692 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_DDFT0_SEL_Pos 0UL 3693 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_DDFT0_SEL_Msk 0x3FUL 3694 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_DDFT0_POLARITY_Pos 7UL 3695 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_DDFT0_POLARITY_Msk 0x80UL 3696 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_DDFT1_SEL_Pos 8UL 3697 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_DDFT1_SEL_Msk 0x3F00UL 3698 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_DDFT1_POLARITY_Pos 15UL 3699 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_DDFT1_POLARITY_Msk 0x8000UL 3700 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_HS_DDFT_EN_Pos 16UL 3701 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_HS_DDFT_EN_Msk 0x10000UL 3702 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_HS_DDFT0_SEL_Pos 17UL 3703 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_HS_DDFT0_SEL_Msk 0x3E0000UL 3704 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_HS_DDFT1_SEL_Pos 22UL 3705 #define USB32DEV_PHYSS_USB40PHY_TOP_PHYSS_DDFT_MUX_SEL_HS_DDFT1_SEL_Msk 0x7C00000UL 3706 /* USB32DEV_PHYSS_USB40PHY_TOP.PIPE_RX_CTRL */ 3707 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_RESERVED_CFG_Pos 0UL 3708 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_RESERVED_CFG_Msk 0xFFFFUL 3709 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_HS_ERROR_DEBOUNCE_Pos 16UL 3710 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_HS_ERROR_DEBOUNCE_Msk 0x1F0000UL 3711 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_HS_DATA_ALIGN_Pos 21UL 3712 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_HS_DATA_ALIGN_Msk 0x3E00000UL 3713 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_FORCE_REALIGN_Pos 26UL 3714 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_FORCE_REALIGN_Msk 0x4000000UL 3715 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_CDR_L2R_ON_POWER_MODE_Pos 27UL 3716 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_CDR_L2R_ON_POWER_MODE_Msk 0x8000000UL 3717 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_VCC_SEL_LFPS_DETECT_Pos 28UL 3718 #define USB32DEV_PHYSS_USB40PHY_TOP_PIPE_RX_CTRL_VCC_SEL_LFPS_DETECT_Msk 0x10000000UL 3719 /* USB32DEV_PHYSS_USB40PHY_TOP.LOW_POWER_CTRL */ 3720 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_LFPS_FILTER_Pos 0UL 3721 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_LFPS_FILTER_Msk 0xFFFFUL 3722 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_HW_CTRL_DELAY_Pos 16UL 3723 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_HW_CTRL_DELAY_Msk 0x1F0000UL 3724 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_LFPS_MASK_ON_TX_DATA_Pos 21UL 3725 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_LFPS_MASK_ON_TX_DATA_Msk 0x200000UL 3726 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_DISABLE_LFPS_FILTER_Pos 22UL 3727 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_DISABLE_LFPS_FILTER_Msk 0x400000UL 3728 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_LFPS_FILTER_MODE_Pos 23UL 3729 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_LFPS_FILTER_MODE_Msk 0x800000UL 3730 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_FORCE_CDR_LOCK_TO_DATA_Pos 24UL 3731 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_FORCE_CDR_LOCK_TO_DATA_Msk 0x1000000UL 3732 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_FORCE_CDR_LOCK_TO_REFERENCE_Pos 25UL 3733 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_FORCE_CDR_LOCK_TO_REFERENCE_Msk 0x2000000UL 3734 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_BYPASS_FILTER_U3_WAKEUP_Pos 26UL 3735 #define USB32DEV_PHYSS_USB40PHY_TOP_LOW_POWER_CTRL_BYPASS_FILTER_U3_WAKEUP_Msk 0x4000000UL 3736 /* USB32DEV_PHYSS_USB40PHY_TOP.CDR_SW_CTRL */ 3737 #define USB32DEV_PHYSS_USB40PHY_TOP_CDR_SW_CTRL_L2D_START_DELAY_Pos 0UL 3738 #define USB32DEV_PHYSS_USB40PHY_TOP_CDR_SW_CTRL_L2D_START_DELAY_Msk 0xFFFFFUL 3739 #define USB32DEV_PHYSS_USB40PHY_TOP_CDR_SW_CTRL_L2R_START_DELAY_Pos 20UL 3740 #define USB32DEV_PHYSS_USB40PHY_TOP_CDR_SW_CTRL_L2R_START_DELAY_Msk 0xFF00000UL 3741 3742 3743 /* USB32DEV_PHYSS_USB40PHY_RX.RX_SDM_CFG0 */ 3744 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG0_DIVF_INTEGER_Pos 0UL 3745 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG0_DIVF_INTEGER_Msk 0xFFUL 3746 /* USB32DEV_PHYSS_USB40PHY_RX.RX_SDM_CFG1 */ 3747 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG1_DIVF_FRAC_MSB_Pos 0UL 3748 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG1_DIVF_FRAC_MSB_Msk 0xFFFFUL 3749 /* USB32DEV_PHYSS_USB40PHY_RX.RX_SDM_CFG2 */ 3750 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG2_DIVF_FRAC_LSB_Pos 0UL 3751 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG2_DIVF_FRAC_LSB_Msk 0x3UL 3752 /* USB32DEV_PHYSS_USB40PHY_RX.RX_SDM_CFG3 */ 3753 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG3_SDM_ENABLE_Pos 0UL 3754 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG3_SDM_ENABLE_Msk 0x1UL 3755 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG3_DITHER_EN_Pos 1UL 3756 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG3_DITHER_EN_Msk 0x2UL 3757 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG3_DITHER_GAIN_Pos 2UL 3758 #define USB32DEV_PHYSS_USB40PHY_RX_SDM_CFG3_DITHER_GAIN_Msk 0x1CUL 3759 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DFE_CFG0 */ 3760 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG0_OVRD_VGATAP_Pos 0UL 3761 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG0_OVRD_VGATAP_Msk 0x1FUL 3762 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG0_OVRD_VGATAP_EN_Pos 7UL 3763 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG0_OVRD_VGATAP_EN_Msk 0x80UL 3764 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG0_OVRD_DFETAP1_Pos 8UL 3765 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG0_OVRD_DFETAP1_Msk 0x7F00UL 3766 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG0_OVRD_DFETAP1_EN_Pos 15UL 3767 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG0_OVRD_DFETAP1_EN_Msk 0x8000UL 3768 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DFE_CFG1 */ 3769 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG1_OVRD_DFETAP2_Pos 0UL 3770 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG1_OVRD_DFETAP2_Msk 0x7FUL 3771 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG1_OVRD_DFETAP2_EN_Pos 7UL 3772 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG1_OVRD_DFETAP2_EN_Msk 0x80UL 3773 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG1_OVRD_DFETAP3_Pos 8UL 3774 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG1_OVRD_DFETAP3_Msk 0x7F00UL 3775 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG1_OVRD_DFETAP3_EN_Pos 15UL 3776 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG1_OVRD_DFETAP3_EN_Msk 0x8000UL 3777 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DFE_CFG2 */ 3778 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_DFE_SLICEPOINTVALUE_Pos 0UL 3779 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_DFE_SLICEPOINTVALUE_Msk 0x3FUL 3780 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_DFE_SLICEPOINTSIGN1_Pos 6UL 3781 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_DFE_SLICEPOINTSIGN1_Msk 0x40UL 3782 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_DFE_SLICEPOINTSIGN2_Pos 7UL 3783 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_DFE_SLICEPOINTSIGN2_Msk 0x80UL 3784 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_VGA_MU_Pos 8UL 3785 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_VGA_MU_Msk 0xF00UL 3786 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_DFE_MU_Pos 12UL 3787 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG2_DFE_MU_Msk 0xF000UL 3788 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DFE_CFG3 */ 3789 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_BAL_AVRG_Pos 0UL 3790 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_BAL_AVRG_Msk 0x7UL 3791 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_VGA_BALANCE_SCALE_Pos 3UL 3792 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_VGA_BALANCE_SCALE_Msk 0x18UL 3793 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_BALANCE_SCALE_Pos 5UL 3794 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_BALANCE_SCALE_Msk 0x60UL 3795 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_VGA_POLARITY_Pos 7UL 3796 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_VGA_POLARITY_Msk 0x80UL 3797 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_POLARITY_Pos 8UL 3798 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_POLARITY_Msk 0x100UL 3799 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_VGA_ADAPT_EN_Pos 9UL 3800 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_VGA_ADAPT_EN_Msk 0x200UL 3801 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_ENABLE_Pos 10UL 3802 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_ENABLE_Msk 0x400UL 3803 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_VGA_FREEZE_Pos 11UL 3804 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_VGA_FREEZE_Msk 0x800UL 3805 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_FREEZE_Pos 12UL 3806 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_FREEZE_Msk 0x1000UL 3807 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_QUALIFIER_INV_Pos 13UL 3808 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_QUALIFIER_INV_Msk 0x2000UL 3809 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_RESETB_Pos 14UL 3810 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG3_DFE_RESETB_Msk 0x4000UL 3811 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DFE_STAT0 */ 3812 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT0_VGATAP_Pos 0UL 3813 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT0_VGATAP_Msk 0x1FUL 3814 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT0_DFETAP1_Pos 8UL 3815 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT0_DFETAP1_Msk 0x7F00UL 3816 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DFE_STAT1 */ 3817 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT1_DFETAP2_Pos 0UL 3818 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT1_DFETAP2_Msk 0x7FUL 3819 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT1_DFETAP3_Pos 8UL 3820 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT1_DFETAP3_Msk 0x7F00UL 3821 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DFE_STAT2 */ 3822 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT2_ERRSLIC1DELTA_Pos 0UL 3823 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT2_ERRSLIC1DELTA_Msk 0x7FUL 3824 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT2_ERRSLIC2DELTA_Pos 8UL 3825 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_STAT2_ERRSLIC2DELTA_Msk 0x7F00UL 3826 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_CFG0 */ 3827 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG0_OVRD_EDGSLICE1OS_Pos 0UL 3828 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG0_OVRD_EDGSLICE1OS_Msk 0x7FUL 3829 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG0_OVRD_EDGSLICE1OS_EN_Pos 7UL 3830 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG0_OVRD_EDGSLICE1OS_EN_Msk 0x80UL 3831 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG0_OVRD_EDGSLICE2OS_Pos 8UL 3832 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG0_OVRD_EDGSLICE2OS_Msk 0x7F00UL 3833 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG0_OVRD_EDGSLICE2OS_EN_Pos 15UL 3834 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG0_OVRD_EDGSLICE2OS_EN_Msk 0x8000UL 3835 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_CFG1 */ 3836 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG1_OVRD_DATSLICE1OS_Pos 0UL 3837 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG1_OVRD_DATSLICE1OS_Msk 0x7FUL 3838 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG1_OVRD_DATSLICE1OS_EN_Pos 7UL 3839 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG1_OVRD_DATSLICE1OS_EN_Msk 0x80UL 3840 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG1_OVRD_DATSLICE2OS_Pos 8UL 3841 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG1_OVRD_DATSLICE2OS_Msk 0x7F00UL 3842 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG1_OVRD_DATSLICE2OS_EN_Pos 15UL 3843 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG1_OVRD_DATSLICE2OS_EN_Msk 0x8000UL 3844 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_CFG2 */ 3845 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG2_OVRD_ERRSLICE1OS_Pos 0UL 3846 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG2_OVRD_ERRSLICE1OS_Msk 0x7FUL 3847 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG2_OVRD_ERRSLICE1OS_EN_Pos 7UL 3848 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG2_OVRD_ERRSLICE1OS_EN_Msk 0x80UL 3849 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG2_OVRD_ERRSLICE2OS_Pos 8UL 3850 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG2_OVRD_ERRSLICE2OS_Msk 0x7F00UL 3851 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG2_OVRD_ERRSLICE2OS_EN_Pos 15UL 3852 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG2_OVRD_ERRSLICE2OS_EN_Msk 0x8000UL 3853 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_CFG3 */ 3854 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG3_OVRD_ROAMSLICE1OS_Pos 0UL 3855 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG3_OVRD_ROAMSLICE1OS_Msk 0x7FUL 3856 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG3_OVRD_ROAMSLICE1OS_EN_Pos 7UL 3857 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG3_OVRD_ROAMSLICE1OS_EN_Msk 0x80UL 3858 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG3_OVRD_ROAMSLICE2OS_Pos 8UL 3859 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG3_OVRD_ROAMSLICE2OS_Msk 0x7F00UL 3860 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG3_OVRD_ROAMSLICE2OS_EN_Pos 15UL 3861 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG3_OVRD_ROAMSLICE2OS_EN_Msk 0x8000UL 3862 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_CFG4 */ 3863 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG4_OVRD_AFEOSDAC_Pos 0UL 3864 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG4_OVRD_AFEOSDAC_Msk 0x7FUL 3865 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG4_OVRD_AFEOSDAC_EN_Pos 7UL 3866 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG4_OVRD_AFEOSDAC_EN_Msk 0x80UL 3867 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_CFG5 */ 3868 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_DFE_START_Pos 0UL 3869 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_DFE_START_Msk 0x1UL 3870 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_AFE_START_Pos 1UL 3871 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_AFE_START_Msk 0x2UL 3872 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_RESETB_Pos 2UL 3873 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_RESETB_Msk 0x4UL 3874 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_ALL_DONE_OVRD_Pos 3UL 3875 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_ALL_DONE_OVRD_Msk 0x8UL 3876 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_ERROR_BITS_MASK_Pos 4UL 3877 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_ERROR_BITS_MASK_Msk 0xF0UL 3878 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_DFE_POLARITY_Pos 8UL 3879 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_DFE_POLARITY_Msk 0x100UL 3880 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_AFE_POLARITY_Pos 9UL 3881 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_CFG5_OSA_AFE_POLARITY_Msk 0x200UL 3882 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_STAT0 */ 3883 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT0_EDGSLICE1OS_Pos 0UL 3884 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT0_EDGSLICE1OS_Msk 0x7FUL 3885 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT0_EDGSLICE2OS_Pos 8UL 3886 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT0_EDGSLICE2OS_Msk 0x7F00UL 3887 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_STAT1 */ 3888 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT1_DATSLICE1OS_Pos 0UL 3889 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT1_DATSLICE1OS_Msk 0x7FUL 3890 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT1_DATSLICE2OS_Pos 8UL 3891 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT1_DATSLICE2OS_Msk 0x7F00UL 3892 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_STAT2 */ 3893 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT2_ERRSLICE1OS_Pos 0UL 3894 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT2_ERRSLICE1OS_Msk 0x7FUL 3895 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT2_ERRSLICE2OS_Pos 8UL 3896 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT2_ERRSLICE2OS_Msk 0x7F00UL 3897 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_STAT3 */ 3898 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT3_ROAMSLICE1OS_Pos 0UL 3899 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT3_ROAMSLICE1OS_Msk 0x7FUL 3900 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT3_ROAMSLICE2OS_Pos 8UL 3901 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT3_ROAMSLICE2OS_Msk 0x7F00UL 3902 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_STAT4 */ 3903 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT4_AFEOSDAC_Pos 0UL 3904 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT4_AFEOSDAC_Msk 0x7FUL 3905 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_STAT5 */ 3906 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_DFE_DONE_Pos 0UL 3907 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_DFE_DONE_Msk 0x1UL 3908 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_AFE_DONE_Pos 1UL 3909 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_AFE_DONE_Msk 0x2UL 3910 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_ALL_DONE_Pos 2UL 3911 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_ALL_DONE_Msk 0x4UL 3912 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_DFE_ERROR_Pos 4UL 3913 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_DFE_ERROR_Msk 0x10UL 3914 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_AFE_ERROR_Pos 5UL 3915 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_AFE_ERROR_Msk 0x20UL 3916 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_ERROR_Pos 6UL 3917 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT5_OSA_ERROR_Msk 0x40UL 3918 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_STAT6 */ 3919 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT6_OSA_ERR_BITS0_Pos 0UL 3920 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT6_OSA_ERR_BITS0_Msk 0xFFFFUL 3921 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_STAT7 */ 3922 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT7_OSA_ERR_BITS1_Pos 0UL 3923 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT7_OSA_ERR_BITS1_Msk 0xFFFFUL 3924 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSA_STAT8 */ 3925 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT8_OSA_ERR_BITS2_Pos 0UL 3926 #define USB32DEV_PHYSS_USB40PHY_RX_OSA_STAT8_OSA_ERR_BITS2_Msk 0xFUL 3927 /* USB32DEV_PHYSS_USB40PHY_RX.RX_CTLE_CFG0 */ 3928 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_CTLE_EYEHT_EN_Pos 0UL 3929 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_CTLE_EYEHT_EN_Msk 0x1UL 3930 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_EYEHT_START_CNT_Pos 1UL 3931 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_EYEHT_START_CNT_Msk 0x2UL 3932 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_CTLE_STG1_CMADJ_Pos 8UL 3933 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_CTLE_STG1_CMADJ_Msk 0x700UL 3934 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_CTLE_CAP_FZERO_EN_Pos 11UL 3935 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_CTLE_CAP_FZERO_EN_Msk 0x800UL 3936 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_CTLE_CAP_GAIN_ADJ_Pos 12UL 3937 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG0_CTLE_CAP_GAIN_ADJ_Msk 0x1000UL 3938 /* USB32DEV_PHYSS_USB40PHY_RX.RX_CTLE_CFG1 */ 3939 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG1RES_Pos 0UL 3940 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG1RES_Msk 0xFUL 3941 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG1CAP_Pos 4UL 3942 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG1CAP_Msk 0x70UL 3943 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG1BOOST_Pos 7UL 3944 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG1BOOST_Msk 0x80UL 3945 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG2RES_Pos 8UL 3946 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG2RES_Msk 0xF00UL 3947 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG2CAP_Pos 12UL 3948 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG2CAP_Msk 0x7000UL 3949 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG2BOOST_Pos 15UL 3950 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_CFG1_CTLE_STG2BOOST_Msk 0x8000UL 3951 /* USB32DEV_PHYSS_USB40PHY_RX.RX_CTLE_STAT0 */ 3952 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_STAT0_EYEHT_ERR_CNT_Pos 0UL 3953 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_STAT0_EYEHT_ERR_CNT_Msk 0xFFFFUL 3954 /* USB32DEV_PHYSS_USB40PHY_RX.RX_CTLE_STAT1 */ 3955 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_STAT1_EYEHT_CNT_DONE_Pos 0UL 3956 #define USB32DEV_PHYSS_USB40PHY_RX_CTLE_STAT1_EYEHT_CNT_DONE_Msk 0x1UL 3957 /* USB32DEV_PHYSS_USB40PHY_RX.RX_EM_CFG0 */ 3958 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EYE_WORD_CNT_Pos 0UL 3959 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EYE_WORD_CNT_Msk 0x7UL 3960 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_DATA_SAMPLE_DELAY_Pos 3UL 3961 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_DATA_SAMPLE_DELAY_Msk 0x38UL 3962 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_ROAM_SAMPLE_DELAY_Pos 6UL 3963 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_ROAM_SAMPLE_DELAY_Msk 0x1C0UL 3964 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EM_CTRL_UNUSED_Pos 9UL 3965 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EM_CTRL_UNUSED_Msk 0xE00UL 3966 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EN_EYE_ODD_Pos 12UL 3967 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EN_EYE_ODD_Msk 0x1000UL 3968 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EN_EYE_EVEN_Pos 13UL 3969 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EN_EYE_EVEN_Msk 0x2000UL 3970 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_START_COUNT_Pos 14UL 3971 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_START_COUNT_Msk 0x4000UL 3972 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EN_EYEMON_Pos 15UL 3973 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG0_EN_EYEMON_Msk 0x8000UL 3974 /* USB32DEV_PHYSS_USB40PHY_RX.RX_EM_CFG1 */ 3975 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_ROAM_SLICEPOINT_Pos 0UL 3976 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_ROAM_SLICEPOINT_Msk 0x3FUL 3977 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_ROAM_SLICEPOINTSIGN1_Pos 6UL 3978 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_ROAM_SLICEPOINTSIGN1_Msk 0x40UL 3979 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_ROAM_SLICEPOINTSIGN2_Pos 7UL 3980 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_ROAM_SLICEPOINTSIGN2_Msk 0x80UL 3981 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_PIROAMPSEL_Pos 8UL 3982 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_PIROAMPSEL_Msk 0x7F00UL 3983 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_PIROAMPSEL_EN_Pos 15UL 3984 #define USB32DEV_PHYSS_USB40PHY_RX_EM_CFG1_PIROAMPSEL_EN_Msk 0x8000UL 3985 /* USB32DEV_PHYSS_USB40PHY_RX.RX_EM_STAT0 */ 3986 #define USB32DEV_PHYSS_USB40PHY_RX_EM_STAT0_EYE_ERROR_Pos 0UL 3987 #define USB32DEV_PHYSS_USB40PHY_RX_EM_STAT0_EYE_ERROR_Msk 0xFFFFUL 3988 /* USB32DEV_PHYSS_USB40PHY_RX.RX_EM_STAT1 */ 3989 #define USB32DEV_PHYSS_USB40PHY_RX_EM_STAT1_EYE_DONE_Pos 0UL 3990 #define USB32DEV_PHYSS_USB40PHY_RX_EM_STAT1_EYE_DONE_Msk 0x1UL 3991 #define USB32DEV_PHYSS_USB40PHY_RX_EM_STAT1_RX_ROAMSLIC1OS_Pos 2UL 3992 #define USB32DEV_PHYSS_USB40PHY_RX_EM_STAT1_RX_ROAMSLIC1OS_Msk 0x1FCUL 3993 #define USB32DEV_PHYSS_USB40PHY_RX_EM_STAT1_RX_ROAMSLIC2OS_Pos 9UL 3994 #define USB32DEV_PHYSS_USB40PHY_RX_EM_STAT1_RX_ROAMSLIC2OS_Msk 0xFE00UL 3995 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DFEA_CFG0 */ 3996 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFEMAINADJ_Pos 0UL 3997 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFEMAINADJ_Msk 0x7UL 3998 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFE_PDB_Pos 3UL 3999 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFE_PDB_Msk 0x8UL 4000 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP1ADJ_Pos 4UL 4001 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP1ADJ_Msk 0x70UL 4002 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP1_PDB_Pos 7UL 4003 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP1_PDB_Msk 0x80UL 4004 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP2ADJ_Pos 8UL 4005 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP2ADJ_Msk 0x700UL 4006 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP2_PDB_Pos 11UL 4007 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP2_PDB_Msk 0x800UL 4008 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP3ADJ_Pos 12UL 4009 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP3ADJ_Msk 0x7000UL 4010 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP3_PDB_Pos 15UL 4011 #define USB32DEV_PHYSS_USB40PHY_RX_DFEA_CFG0_DFETAP3_PDB_Msk 0x8000UL 4012 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSAA_CFG0 */ 4013 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJEDGESLIC1_Pos 0UL 4014 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJEDGESLIC1_Msk 0x7UL 4015 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJEDGESLIC2_Pos 3UL 4016 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJEDGESLIC2_Msk 0x38UL 4017 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJDATSLIC1_Pos 6UL 4018 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJDATSLIC1_Msk 0x1C0UL 4019 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJDATSLIC2_Pos 9UL 4020 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJDATSLIC2_Msk 0xE00UL 4021 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJERRSLIC1_Pos 12UL 4022 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG0_ADJERRSLIC1_Msk 0x7000UL 4023 /* USB32DEV_PHYSS_USB40PHY_RX.RX_OSAA_CFG1 */ 4024 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG1_ADJERRSLIC2_Pos 0UL 4025 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG1_ADJERRSLIC2_Msk 0x7UL 4026 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG1_ADJROAMSLIC1_Pos 3UL 4027 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG1_ADJROAMSLIC1_Msk 0x38UL 4028 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG1_ADJROAMSLIC2_Pos 6UL 4029 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG1_ADJROAMSLIC2_Msk 0x1C0UL 4030 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG1_AFEOSBIASADJ_Pos 9UL 4031 #define USB32DEV_PHYSS_USB40PHY_RX_OSAA_CFG1_AFEOSBIASADJ_Msk 0xE00UL 4032 /* USB32DEV_PHYSS_USB40PHY_RX.RX_AFE_CFG */ 4033 #define USB32DEV_PHYSS_USB40PHY_RX_AFE_CFG_CMADJ_Pos 0UL 4034 #define USB32DEV_PHYSS_USB40PHY_RX_AFE_CFG_CMADJ_Msk 0x7UL 4035 #define USB32DEV_PHYSS_USB40PHY_RX_AFE_CFG_TERM_EN_Pos 3UL 4036 #define USB32DEV_PHYSS_USB40PHY_RX_AFE_CFG_TERM_EN_Msk 0x8UL 4037 #define USB32DEV_PHYSS_USB40PHY_RX_AFE_CFG_TERM_TRIM_CFG_Pos 4UL 4038 #define USB32DEV_PHYSS_USB40PHY_RX_AFE_CFG_TERM_TRIM_CFG_Msk 0x1F0UL 4039 #define USB32DEV_PHYSS_USB40PHY_RX_AFE_CFG_LPBK_EN_Pos 9UL 4040 #define USB32DEV_PHYSS_USB40PHY_RX_AFE_CFG_LPBK_EN_Msk 0x200UL 4041 /* USB32DEV_PHYSS_USB40PHY_RX.RX_EMA_CFG */ 4042 #define USB32DEV_PHYSS_USB40PHY_RX_EMA_CFG_PICAPSEL_Pos 0UL 4043 #define USB32DEV_PHYSS_USB40PHY_RX_EMA_CFG_PICAPSEL_Msk 0x7UL 4044 #define USB32DEV_PHYSS_USB40PHY_RX_EMA_CFG_PI_PDB_Pos 4UL 4045 #define USB32DEV_PHYSS_USB40PHY_RX_EMA_CFG_PI_PDB_Msk 0x10UL 4046 /* USB32DEV_PHYSS_USB40PHY_RX.RX_REFCKSEL_CFG */ 4047 #define USB32DEV_PHYSS_USB40PHY_RX_REFCKSEL_CFG_LOCK2REF_SEL_Pos 0UL 4048 #define USB32DEV_PHYSS_USB40PHY_RX_REFCKSEL_CFG_LOCK2REF_SEL_Msk 0x1UL 4049 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DIVH_CFG */ 4050 #define USB32DEV_PHYSS_USB40PHY_RX_DIVH_CFG_RECCLK_DIVH_Pos 0UL 4051 #define USB32DEV_PHYSS_USB40PHY_RX_DIVH_CFG_RECCLK_DIVH_Msk 0x1FUL 4052 #define USB32DEV_PHYSS_USB40PHY_RX_DIVH_CFG_RECCLK_EN_Pos 8UL 4053 #define USB32DEV_PHYSS_USB40PHY_RX_DIVH_CFG_RECCLK_EN_Msk 0x100UL 4054 /* USB32DEV_PHYSS_USB40PHY_RX.RX_PFD_CFG */ 4055 #define USB32DEV_PHYSS_USB40PHY_RX_PFD_CFG_PFDDELAY_Pos 0UL 4056 #define USB32DEV_PHYSS_USB40PHY_RX_PFD_CFG_PFDDELAY_Msk 0xFUL 4057 /* USB32DEV_PHYSS_USB40PHY_RX.RX_CP_CFG */ 4058 #define USB32DEV_PHYSS_USB40PHY_RX_CP_CFG_IPUP_ADJ_Pos 0UL 4059 #define USB32DEV_PHYSS_USB40PHY_RX_CP_CFG_IPUP_ADJ_Msk 0x7UL 4060 #define USB32DEV_PHYSS_USB40PHY_RX_CP_CFG_IPDN_ADJ_Pos 4UL 4061 #define USB32DEV_PHYSS_USB40PHY_RX_CP_CFG_IPDN_ADJ_Msk 0x70UL 4062 /* USB32DEV_PHYSS_USB40PHY_RX.RX_LF_CFG */ 4063 #define USB32DEV_PHYSS_USB40PHY_RX_LF_CFG_LPF_ADJ_Pos 0UL 4064 #define USB32DEV_PHYSS_USB40PHY_RX_LF_CFG_LPF_ADJ_Msk 0x3UL 4065 /* USB32DEV_PHYSS_USB40PHY_RX.RX_BIASGEN_CFG0 */ 4066 #define USB32DEV_PHYSS_USB40PHY_RX_BIASGEN_CFG0_AFEBIASSET0_Pos 0UL 4067 #define USB32DEV_PHYSS_USB40PHY_RX_BIASGEN_CFG0_AFEBIASSET0_Msk 0xFFFUL 4068 /* USB32DEV_PHYSS_USB40PHY_RX.RX_BIASGEN_CFG1 */ 4069 #define USB32DEV_PHYSS_USB40PHY_RX_BIASGEN_CFG1_AFEBIASSET1_Pos 0UL 4070 #define USB32DEV_PHYSS_USB40PHY_RX_BIASGEN_CFG1_AFEBIASSET1_Msk 0x3FUL 4071 #define USB32DEV_PHYSS_USB40PHY_RX_BIASGEN_CFG1_CFG_BIAS_Pos 8UL 4072 #define USB32DEV_PHYSS_USB40PHY_RX_BIASGEN_CFG1_CFG_BIAS_Msk 0x3F00UL 4073 #define USB32DEV_PHYSS_USB40PHY_RX_BIASGEN_CFG1_BIAS_PDB_Pos 14UL 4074 #define USB32DEV_PHYSS_USB40PHY_RX_BIASGEN_CFG1_BIAS_PDB_Msk 0x4000UL 4075 /* USB32DEV_PHYSS_USB40PHY_RX.RX_GNRL_CFG */ 4076 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_BUS_BIT_MODE_Pos 0UL 4077 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_BUS_BIT_MODE_Msk 0x3UL 4078 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_DESERRESETB_Pos 2UL 4079 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_DESERRESETB_Msk 0x4UL 4080 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_DATA_RATE_Pos 3UL 4081 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_DATA_RATE_Msk 0x8UL 4082 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_CLKGEN_PDB_Pos 4UL 4083 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_CLKGEN_PDB_Msk 0x10UL 4084 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_LOWPWR_Pos 5UL 4085 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_LOWPWR_Msk 0x20UL 4086 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_ERR_PATH_EN_Pos 6UL 4087 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_ERR_PATH_EN_Msk 0x40UL 4088 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_ROM_PATH_EN_Pos 7UL 4089 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_ROM_PATH_EN_Msk 0x80UL 4090 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_EDGE_DESER_EN_Pos 8UL 4091 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_EDGE_DESER_EN_Msk 0x100UL 4092 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_SUMEVN_PDB_Pos 9UL 4093 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_SUMEVN_PDB_Msk 0x200UL 4094 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_SUMODD_PDB_Pos 10UL 4095 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_SUMODD_PDB_Msk 0x400UL 4096 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_SUMVDD_PULLDOWN_Pos 11UL 4097 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_SUMVDD_PULLDOWN_Msk 0x800UL 4098 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_VCO_ADJ_Pos 12UL 4099 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_VCO_ADJ_Msk 0x1000UL 4100 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_CLKINV_Pos 13UL 4101 #define USB32DEV_PHYSS_USB40PHY_RX_GNRL_CFG_CLKINV_Msk 0x2000UL 4102 /* USB32DEV_PHYSS_USB40PHY_RX.RX_VREG_CFG0 */ 4103 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG0_VCPREGSEL_Pos 0UL 4104 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG0_VCPREGSEL_Msk 0xFUL 4105 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG0_VREGRXASEL_Pos 4UL 4106 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG0_VREGRXASEL_Msk 0xF0UL 4107 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG0_VREGRXCKSEL_Pos 8UL 4108 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG0_VREGRXCKSEL_Msk 0xF00UL 4109 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG0_VREGRXDSEL_Pos 12UL 4110 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG0_VREGRXDSEL_Msk 0xF000UL 4111 /* USB32DEV_PHYSS_USB40PHY_RX.RX_VREG_CFG1 */ 4112 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VCPREG_PDB_Pos 0UL 4113 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VCPREG_PDB_Msk 0x1UL 4114 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VREGRXA_PDB_Pos 1UL 4115 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VREGRXA_PDB_Msk 0x2UL 4116 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VREGRXCK_PDB_Pos 2UL 4117 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VREGRXCK_PDB_Msk 0x4UL 4118 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VREGRXD_PDB_Pos 3UL 4119 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VREGRXD_PDB_Msk 0x8UL 4120 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VCPREG_BPB_Pos 4UL 4121 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_VCPREG_BPB_Msk 0x10UL 4122 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_CPCLK_SEL_Pos 5UL 4123 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_CPCLK_SEL_Msk 0x20UL 4124 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_BURNIN_EN_Pos 6UL 4125 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_CFG1_BURNIN_EN_Msk 0x40UL 4126 /* USB32DEV_PHYSS_USB40PHY_RX.RX_VREG_STAT */ 4127 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_STAT_POWER_GOOD_RXA_Pos 0UL 4128 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_STAT_POWER_GOOD_RXA_Msk 0x1UL 4129 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_STAT_POWER_GOOD_RXCK_Pos 1UL 4130 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_STAT_POWER_GOOD_RXCK_Msk 0x2UL 4131 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_STAT_POWER_GOOD_RXD_Pos 2UL 4132 #define USB32DEV_PHYSS_USB40PHY_RX_VREG_STAT_POWER_GOOD_RXD_Msk 0x4UL 4133 /* USB32DEV_PHYSS_USB40PHY_RX.RX_SD_CFG */ 4134 #define USB32DEV_PHYSS_USB40PHY_RX_SD_CFG_LFPS_VTH_Pos 0UL 4135 #define USB32DEV_PHYSS_USB40PHY_RX_SD_CFG_LFPS_VTH_Msk 0x7UL 4136 #define USB32DEV_PHYSS_USB40PHY_RX_SD_CFG_LFPSDET_PDB_Pos 3UL 4137 #define USB32DEV_PHYSS_USB40PHY_RX_SD_CFG_LFPSDET_PDB_Msk 0x8UL 4138 /* USB32DEV_PHYSS_USB40PHY_RX.RX_SD_STAT */ 4139 #define USB32DEV_PHYSS_USB40PHY_RX_SD_STAT_LFPSDET_OUT_Pos 0UL 4140 #define USB32DEV_PHYSS_USB40PHY_RX_SD_STAT_LFPSDET_OUT_Msk 0x1UL 4141 /* USB32DEV_PHYSS_USB40PHY_RX.RX_LD_CFG */ 4142 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_LOCKIN_Pos 0UL 4143 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_LOCKIN_Msk 0x7UL 4144 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_FLOCKSEL_Pos 4UL 4145 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_FLOCKSEL_Msk 0x30UL 4146 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_LOCKOUTSEL_Pos 6UL 4147 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_LOCKOUTSEL_Msk 0x40UL 4148 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_LUDDISABLE_Pos 7UL 4149 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_LUDDISABLE_Msk 0x80UL 4150 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_FD_OVRD_Pos 8UL 4151 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_FD_OVRD_Msk 0x300UL 4152 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_RESETLOCKB_Pos 10UL 4153 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_RESETLOCKB_Msk 0x400UL 4154 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_LD_RESETB_Pos 11UL 4155 #define USB32DEV_PHYSS_USB40PHY_RX_LD_CFG_LD_RESETB_Msk 0x800UL 4156 /* USB32DEV_PHYSS_USB40PHY_RX.RX_LD_STAT */ 4157 #define USB32DEV_PHYSS_USB40PHY_RX_LD_STAT_PLL_LOCKED_Pos 0UL 4158 #define USB32DEV_PHYSS_USB40PHY_RX_LD_STAT_PLL_LOCKED_Msk 0x1UL 4159 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DFE_CFG4 */ 4160 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG4_INIT_VGATAP_VALUE_Pos 0UL 4161 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG4_INIT_VGATAP_VALUE_Msk 0x1FUL 4162 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG4_TAP_UPDATE_TRSHLD_Pos 5UL 4163 #define USB32DEV_PHYSS_USB40PHY_RX_DFE_CFG4_TAP_UPDATE_TRSHLD_Msk 0xE0UL 4164 /* USB32DEV_PHYSS_USB40PHY_RX.RX_HDWR_ENABLE */ 4165 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_CTLE_HDWR_ENABLE_Pos 0UL 4166 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_CTLE_HDWR_ENABLE_Msk 0x1UL 4167 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_DFE_HDWR_ENABLE_Pos 1UL 4168 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_DFE_HDWR_ENABLE_Msk 0x2UL 4169 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_DESER_HDWR_ENABLE_Pos 2UL 4170 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_DESER_HDWR_ENABLE_Msk 0x4UL 4171 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_CDR_HDWR_ENABLE_Pos 3UL 4172 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_CDR_HDWR_ENABLE_Msk 0x8UL 4173 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_SPARE_HDWR_ENABLE_Pos 4UL 4174 #define USB32DEV_PHYSS_USB40PHY_RX_HDWR_ENABLE_SPARE_HDWR_ENABLE_Msk 0x30UL 4175 /* USB32DEV_PHYSS_USB40PHY_RX.RX_ATEST_CFG */ 4176 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_CNTL_Pos 0UL 4177 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_CNTL_Msk 0xFUL 4178 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_ENABLE_Pos 4UL 4179 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_ENABLE_Msk 0x10UL 4180 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_IB20U_SEL_Pos 5UL 4181 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_IB20U_SEL_Msk 0x20UL 4182 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_DAC_TEST_Pos 8UL 4183 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_DAC_TEST_Msk 0xF00UL 4184 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_DFE_TEST_Pos 12UL 4185 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_DFE_TEST_Msk 0x7000UL 4186 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_VREGDIV_EN_Pos 15UL 4187 #define USB32DEV_PHYSS_USB40PHY_RX_ATEST_CFG_ADFT_VREGDIV_EN_Msk 0x8000UL 4188 /* USB32DEV_PHYSS_USB40PHY_RX.RX_DTEST_CFG */ 4189 #define USB32DEV_PHYSS_USB40PHY_RX_DTEST_CFG_DDFT0_SEL_Pos 0UL 4190 #define USB32DEV_PHYSS_USB40PHY_RX_DTEST_CFG_DDFT0_SEL_Msk 0x3FUL 4191 #define USB32DEV_PHYSS_USB40PHY_RX_DTEST_CFG_DDFT1_SEL_Pos 8UL 4192 #define USB32DEV_PHYSS_USB40PHY_RX_DTEST_CFG_DDFT1_SEL_Msk 0x3F00UL 4193 #define USB32DEV_PHYSS_USB40PHY_RX_DTEST_CFG_DDFT_ENABLE_Pos 15UL 4194 #define USB32DEV_PHYSS_USB40PHY_RX_DTEST_CFG_DDFT_ENABLE_Msk 0x8000UL 4195 /* USB32DEV_PHYSS_USB40PHY_RX.SPARE_CFG */ 4196 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_CFG_SPARE_OUT_Pos 0UL 4197 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_CFG_SPARE_OUT_Msk 0x7UL 4198 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_CFG_SPARE_FT_OUT_Pos 3UL 4199 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_CFG_SPARE_FT_OUT_Msk 0xFFF8UL 4200 /* USB32DEV_PHYSS_USB40PHY_RX.SPARE_STAT */ 4201 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_STAT_SPARE_INPUTS_Pos 0UL 4202 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_STAT_SPARE_INPUTS_Msk 0x7UL 4203 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_STAT_SPARE_FT_IN_Pos 3UL 4204 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_STAT_SPARE_FT_IN_Msk 0xFFF8UL 4205 /* USB32DEV_PHYSS_USB40PHY_RX.SPARE_HV_CFG */ 4206 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_HV_CFG_SPARE_HV_CFG_Pos 0UL 4207 #define USB32DEV_PHYSS_USB40PHY_RX_SPARE_HV_CFG_SPARE_HV_CFG_Msk 0x7UL 4208 4209 4210 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_SDM_CFG */ 4211 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SDM_CFG_SDM_ENABLE_Pos 0UL 4212 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SDM_CFG_SDM_ENABLE_Msk 0x1UL 4213 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SDM_CFG_DITHER_EN_Pos 1UL 4214 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SDM_CFG_DITHER_EN_Msk 0x2UL 4215 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SDM_CFG_DITHER_GAIN_Pos 2UL 4216 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SDM_CFG_DITHER_GAIN_Msk 0x1CUL 4217 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_SSM_CFG0 */ 4218 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG0_DIVF_FRAC_MSB_Pos 0UL 4219 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG0_DIVF_FRAC_MSB_Msk 0xFFUL 4220 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG0_DIVF_INTEGER_Pos 8UL 4221 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG0_DIVF_INTEGER_Msk 0xFF00UL 4222 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_SSM_CFG1 */ 4223 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG1_DIVF_FRAC_LSB_Pos 0UL 4224 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG1_DIVF_FRAC_LSB_Msk 0x3FFUL 4225 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG1_SPREAD_Pos 13UL 4226 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG1_SPREAD_Msk 0xE000UL 4227 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_SSM_CFG2 */ 4228 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG2_SSM_STEP_CNT_Pos 0UL 4229 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG2_SSM_STEP_CNT_Msk 0x1FFUL 4230 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG2_SSM_UPDATE_CNT_Pos 9UL 4231 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG2_SSM_UPDATE_CNT_Msk 0x3E00UL 4232 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG2_SSM_ENABLE_Pos 14UL 4233 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_SSM_CFG2_SSM_ENABLE_Msk 0x4000UL 4234 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_AFC_CFG0 */ 4235 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_VCTL_SET_Pos 0UL 4236 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_VCTL_SET_Msk 0x7UL 4237 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_VCMP_PDB_Pos 3UL 4238 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_VCMP_PDB_Msk 0x8UL 4239 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_VCMP_SEL_Pos 4UL 4240 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_VCMP_SEL_Msk 0xF0UL 4241 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_OVRD_CAPSEL_Pos 8UL 4242 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_OVRD_CAPSEL_Msk 0x7F00UL 4243 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_OVRRIDEN_Pos 15UL 4244 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG0_AFC_OVRRIDEN_Msk 0x8000UL 4245 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_AFC_CFG1 */ 4246 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_VCTL_HI_CNT_Pos 0UL 4247 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_VCTL_HI_CNT_Msk 0x1FUL 4248 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_VCTL_LO_CNT_Pos 5UL 4249 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_VCTL_LO_CNT_Msk 0x3E0UL 4250 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_VCTL_ENABLE_OVERRIDE_Pos 10UL 4251 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_VCTL_ENABLE_OVERRIDE_Msk 0x400UL 4252 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_VCTL_ENABLE_OVERRIDE_VALUE_Pos 11UL 4253 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_VCTL_ENABLE_OVERRIDE_VALUE_Msk 0x800UL 4254 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_SEL_MIN_Pos 12UL 4255 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_SEL_MIN_Msk 0x1000UL 4256 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_SEL_MAX_Pos 13UL 4257 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG1_AFC_SEL_MAX_Msk 0x2000UL 4258 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_AFC_CFG2 */ 4259 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG2_AFC_CLKDIVSEL_Pos 0UL 4260 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG2_AFC_CLKDIVSEL_Msk 0x3FUL 4261 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG2_AFC_PDB_Pos 6UL 4262 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_CFG2_AFC_PDB_Msk 0x40UL 4263 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_AFC_STAT */ 4264 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_STAT_CAPSEL_Pos 0UL 4265 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AFC_STAT_CAPSEL_Msk 0x7FUL 4266 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_AAC_CFG0 */ 4267 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG0_AACREFSEL_Pos 0UL 4268 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG0_AACREFSEL_Msk 0xFUL 4269 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG0_AAC_OVRD_AACSEL_Pos 4UL 4270 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG0_AAC_OVRD_AACSEL_Msk 0x1F0UL 4271 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG0_AAC_OVRRIDEN_Pos 9UL 4272 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG0_AAC_OVRRIDEN_Msk 0x200UL 4273 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_AAC_CFG1 */ 4274 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG1_AAC_CLKDIVSEL_Pos 0UL 4275 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG1_AAC_CLKDIVSEL_Msk 0x3FUL 4276 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG1_AAC_FRZCNT_Pos 6UL 4277 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG1_AAC_FRZCNT_Msk 0x40UL 4278 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG1_AAC_NORECAL_Pos 7UL 4279 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG1_AAC_NORECAL_Msk 0x80UL 4280 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG1_AAC_PDB_Pos 8UL 4281 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_CFG1_AAC_PDB_Msk 0x100UL 4282 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_AAC_STAT */ 4283 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_STAT_AACSEL_Pos 0UL 4284 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_AAC_STAT_AACSEL_Msk 0x1FUL 4285 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_REFCKSEL_CFG */ 4286 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_REFCKSEL_CFG_REFCLKSEL_Pos 0UL 4287 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_REFCKSEL_CFG_REFCLKSEL_Msk 0x7UL 4288 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_DIVR_CFG */ 4289 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVR_CFG_LCDIVR_Pos 0UL 4290 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVR_CFG_LCDIVR_Msk 0xFUL 4291 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_DIVP_CFG */ 4292 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_LCDIVP_Pos 0UL 4293 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_LCDIVP_Msk 0xFUL 4294 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_LCBYPASS_Pos 4UL 4295 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_LCBYPASS_Msk 0x10UL 4296 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_TX0_DIVP_PDB_Pos 5UL 4297 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_TX0_DIVP_PDB_Msk 0x20UL 4298 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_TX1_DIVP_PDB_Pos 6UL 4299 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_TX1_DIVP_PDB_Msk 0x40UL 4300 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_PLL_SYNC_ENABLE_Pos 7UL 4301 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVP_CFG_PLL_SYNC_ENABLE_Msk 0x80UL 4302 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_DIVH_CFG */ 4303 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVH_CFG_HSREF_DIVH_Pos 0UL 4304 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVH_CFG_HSREF_DIVH_Msk 0x1FUL 4305 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVH_CFG_HSREF_EN_Pos 5UL 4306 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DIVH_CFG_HSREF_EN_Msk 0x20UL 4307 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_PFD_CFG */ 4308 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_PFD_CFG_PFDDELAY_Pos 0UL 4309 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_PFD_CFG_PFDDELAY_Msk 0xFUL 4310 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_CP_CFG */ 4311 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_CP_CFG_CFGRCP_Pos 0UL 4312 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_CP_CFG_CFGRCP_Msk 0xFUL 4313 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_CP_CFG_ICPDAC_Pos 4UL 4314 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_CP_CFG_ICPDAC_Msk 0xF0UL 4315 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_CP_CFG_CP_PDB_Pos 8UL 4316 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_CP_CFG_CP_PDB_Msk 0x100UL 4317 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_LF_CFG */ 4318 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LF_CFG_LF_RTUNE_Pos 0UL 4319 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LF_CFG_LF_RTUNE_Msk 0x7UL 4320 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LF_CFG_LF_CTUNE_Pos 3UL 4321 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LF_CFG_LF_CTUNE_Msk 0x18UL 4322 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_VCO_CFG */ 4323 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VCO_CFG_DCVARMODE_Pos 0UL 4324 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VCO_CFG_DCVARMODE_Msk 0xFUL 4325 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VCO_CFG_VCOVARCM1_Pos 4UL 4326 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VCO_CFG_VCOVARCM1_Msk 0xF0UL 4327 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VCO_CFG_VCOVARCM2_Pos 8UL 4328 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VCO_CFG_VCOVARCM2_Msk 0xF00UL 4329 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_BIASGEN_CFG */ 4330 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_BIASGEN_CFG_CFG_BIAS_Pos 0UL 4331 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_BIASGEN_CFG_CFG_BIAS_Msk 0x3FUL 4332 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_BIASGEN_CFG_TERM_TRIM_Pos 8UL 4333 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_BIASGEN_CFG_TERM_TRIM_Msk 0x1F00UL 4334 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_GNRL_CFG */ 4335 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_GNRL_CFG_PLL_PDB_Pos 0UL 4336 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_GNRL_CFG_PLL_PDB_Msk 0x1UL 4337 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_GNRL_CFG_LKDT_RESETB_Pos 1UL 4338 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_GNRL_CFG_LKDT_RESETB_Msk 0x2UL 4339 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_GNRL_CFG_RESETLOCKB_Pos 2UL 4340 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_GNRL_CFG_RESETLOCKB_Msk 0x4UL 4341 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_VREG_CFG1 */ 4342 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG1_VCPREGSEL_Pos 0UL 4343 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG1_VCPREGSEL_Msk 0xFUL 4344 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG1_VREGLCPLLSEL_Pos 4UL 4345 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG1_VREGLCPLLSEL_Msk 0xF0UL 4346 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG1_VREGREFSEL_Pos 8UL 4347 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG1_VREGREFSEL_Msk 0xF00UL 4348 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG1_VREGDIGSEL_Pos 12UL 4349 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG1_VREGDIGSEL_Msk 0xF000UL 4350 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_VREG_CFG2 */ 4351 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VCPREG_PDB_Pos 0UL 4352 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VCPREG_PDB_Msk 0x1UL 4353 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VREGLCPLL_PDB_Pos 1UL 4354 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VREGLCPLL_PDB_Msk 0x2UL 4355 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VREGREF_PDB_Pos 2UL 4356 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VREGREF_PDB_Msk 0x4UL 4357 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VREGDIG_PDB_Pos 3UL 4358 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VREGDIG_PDB_Msk 0x8UL 4359 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VCPREG_BPB_Pos 4UL 4360 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_VCPREG_BPB_Msk 0x10UL 4361 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_CPCLK_SEL_Pos 5UL 4362 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_CPCLK_SEL_Msk 0x20UL 4363 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_BURNIN_Pos 6UL 4364 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_CFG2_BURNIN_Msk 0x40UL 4365 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_VREG_STAT */ 4366 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_STAT_PWR_GOOD_LCPLL_Pos 0UL 4367 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_STAT_PWR_GOOD_LCPLL_Msk 0x1UL 4368 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_STAT_PWR_GOOD_REF_Pos 1UL 4369 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_STAT_PWR_GOOD_REF_Msk 0x2UL 4370 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_STAT_PWR_GOOD_DIG_Pos 2UL 4371 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_VREG_STAT_PWR_GOOD_DIG_Msk 0x4UL 4372 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_LD_CFG */ 4373 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_LOCKOS_Pos 0UL 4374 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_LOCKOS_Msk 0x7UL 4375 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_DLFCNTSEL_Pos 4UL 4376 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_DLFCNTSEL_Msk 0x30UL 4377 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_LUDDIVSEL_Pos 6UL 4378 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_LUDDIVSEL_Msk 0x40UL 4379 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_LUDDISABLE_Pos 7UL 4380 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_LUDDISABLE_Msk 0x80UL 4381 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_CRS_FD_AUXCLK_SEL_Pos 8UL 4382 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_CRS_FD_AUXCLK_SEL_Msk 0x100UL 4383 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_CRS_FD_DISABLE_Pos 9UL 4384 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_CFG_CRS_FD_DISABLE_Msk 0x200UL 4385 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_LD_STAT */ 4386 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_STAT_FLOCK_Pos 0UL 4387 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_LD_STAT_FLOCK_Msk 0x1UL 4388 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_ATEST */ 4389 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_ATEST_ADFT_SEL_Pos 0UL 4390 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_ATEST_ADFT_SEL_Msk 0xFUL 4391 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_ATEST_ADFT_ENABLE_Pos 4UL 4392 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_ATEST_ADFT_ENABLE_Msk 0x10UL 4393 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_ATEST_ADFT_VREGDIV_EN_Pos 5UL 4394 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_ATEST_ADFT_VREGDIV_EN_Msk 0x20UL 4395 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.PLL_DTEST */ 4396 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DTEST_DDFT0_SEL_Pos 0UL 4397 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DTEST_DDFT0_SEL_Msk 0x3FUL 4398 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DTEST_DDFT1_SEL_Pos 8UL 4399 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DTEST_DDFT1_SEL_Msk 0x3F00UL 4400 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DTEST_DDFT_ENABLE_Pos 15UL 4401 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_PLL_DTEST_DDFT_ENABLE_Msk 0x8000UL 4402 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.SPARE_CFG */ 4403 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_SPARE_CFG_SPARE_OUT_Pos 0UL 4404 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_SPARE_CFG_SPARE_OUT_Msk 0x3UL 4405 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_SPARE_CFG_SPARE_FT_OUT_Pos 3UL 4406 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_SPARE_CFG_SPARE_FT_OUT_Msk 0xFFF8UL 4407 /* USB32DEV_PHYSS_USB40PHY_PLL_SYS.SPARE_STAT */ 4408 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_SPARE_STAT_SPARE_INPUTS_Pos 0UL 4409 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_SPARE_STAT_SPARE_INPUTS_Msk 0x7UL 4410 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_SPARE_STAT_SPARE_FT_IN_Pos 3UL 4411 #define USB32DEV_PHYSS_USB40PHY_PLL_SYS_SPARE_STAT_SPARE_FT_IN_Msk 0xFFF8UL 4412 4413 4414 /* USB32DEV_ADAPTER_DMA_SCK.SCK_DSCR */ 4415 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_DSCR_NUMBER_Pos 0UL 4416 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_DSCR_NUMBER_Msk 0xFFFFUL 4417 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_DSCR_COUNT_Pos 16UL 4418 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_DSCR_COUNT_Msk 0xFF0000UL 4419 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_DSCR_LOW_Pos 24UL 4420 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_DSCR_LOW_Msk 0xFF000000UL 4421 /* USB32DEV_ADAPTER_DMA_SCK.SCK_SIZE */ 4422 #define USB32DEV_ADAPTER_DMA_SCK_SIZE_TRANS_SIZE_Pos 0UL 4423 #define USB32DEV_ADAPTER_DMA_SCK_SIZE_TRANS_SIZE_Msk 0xFFFFFFFFUL 4424 /* USB32DEV_ADAPTER_DMA_SCK.SCK_COUNT */ 4425 #define USB32DEV_ADAPTER_DMA_SCK_COUNT_TRANS_COUNT_Pos 0UL 4426 #define USB32DEV_ADAPTER_DMA_SCK_COUNT_TRANS_COUNT_Msk 0xFFFFFFFFUL 4427 /* USB32DEV_ADAPTER_DMA_SCK.SCK_STATUS */ 4428 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_AVL_COUNT_Pos 0UL 4429 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_AVL_COUNT_Msk 0x1FUL 4430 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_AVL_MIN_Pos 5UL 4431 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_AVL_MIN_Msk 0x3E0UL 4432 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_AVL_ENABLE_Pos 10UL 4433 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_AVL_ENABLE_Msk 0x400UL 4434 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SCK_ZLP_ALWAYS_Pos 11UL 4435 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SCK_ZLP_ALWAYS_Msk 0x800UL 4436 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_STATE_Pos 15UL 4437 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_STATE_Msk 0x38000UL 4438 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_ZLP_RCVD_Pos 18UL 4439 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_ZLP_RCVD_Msk 0x40000UL 4440 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSPENDED_Pos 19UL 4441 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSPENDED_Msk 0x80000UL 4442 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_ENABLED_Pos 20UL 4443 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_ENABLED_Msk 0x100000UL 4444 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_TRUNCATE_Pos 21UL 4445 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_TRUNCATE_Msk 0x200000UL 4446 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_EN_PROD_EVENTS_Pos 22UL 4447 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_EN_PROD_EVENTS_Msk 0x400000UL 4448 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_EN_CONS_EVENTS_Pos 23UL 4449 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_EN_CONS_EVENTS_Msk 0x800000UL 4450 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSP_PARTIAL_Pos 24UL 4451 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSP_PARTIAL_Msk 0x1000000UL 4452 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSP_LAST_Pos 25UL 4453 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSP_LAST_Msk 0x2000000UL 4454 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSP_TRANS_Pos 26UL 4455 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSP_TRANS_Msk 0x4000000UL 4456 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSP_EOP_Pos 27UL 4457 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_SUSP_EOP_Msk 0x8000000UL 4458 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_WRAPUP_Pos 28UL 4459 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_WRAPUP_Msk 0x10000000UL 4460 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_UNIT_Pos 29UL 4461 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_UNIT_Msk 0x20000000UL 4462 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_GO_SUSPEND_Pos 30UL 4463 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_GO_SUSPEND_Msk 0x40000000UL 4464 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_GO_ENABLE_Pos 31UL 4465 #define USB32DEV_ADAPTER_DMA_SCK_STATUS_GO_ENABLE_Msk 0x80000000UL 4466 /* USB32DEV_ADAPTER_DMA_SCK.SCK_INTR */ 4467 #define USB32DEV_ADAPTER_DMA_SCK_INTR_PRODUCE_EVENT_Pos 0UL 4468 #define USB32DEV_ADAPTER_DMA_SCK_INTR_PRODUCE_EVENT_Msk 0x1UL 4469 #define USB32DEV_ADAPTER_DMA_SCK_INTR_CONSUME_EVENT_Pos 1UL 4470 #define USB32DEV_ADAPTER_DMA_SCK_INTR_CONSUME_EVENT_Msk 0x2UL 4471 #define USB32DEV_ADAPTER_DMA_SCK_INTR_DSCR_IS_LOW_Pos 2UL 4472 #define USB32DEV_ADAPTER_DMA_SCK_INTR_DSCR_IS_LOW_Msk 0x4UL 4473 #define USB32DEV_ADAPTER_DMA_SCK_INTR_DSCR_NOT_AVL_Pos 3UL 4474 #define USB32DEV_ADAPTER_DMA_SCK_INTR_DSCR_NOT_AVL_Msk 0x8UL 4475 #define USB32DEV_ADAPTER_DMA_SCK_INTR_STALL_Pos 4UL 4476 #define USB32DEV_ADAPTER_DMA_SCK_INTR_STALL_Msk 0x10UL 4477 #define USB32DEV_ADAPTER_DMA_SCK_INTR_SUSPEND_Pos 5UL 4478 #define USB32DEV_ADAPTER_DMA_SCK_INTR_SUSPEND_Msk 0x20UL 4479 #define USB32DEV_ADAPTER_DMA_SCK_INTR_ERROR_Pos 6UL 4480 #define USB32DEV_ADAPTER_DMA_SCK_INTR_ERROR_Msk 0x40UL 4481 #define USB32DEV_ADAPTER_DMA_SCK_INTR_TRANS_DONE_Pos 7UL 4482 #define USB32DEV_ADAPTER_DMA_SCK_INTR_TRANS_DONE_Msk 0x80UL 4483 #define USB32DEV_ADAPTER_DMA_SCK_INTR_PARTIAL_BUF_Pos 8UL 4484 #define USB32DEV_ADAPTER_DMA_SCK_INTR_PARTIAL_BUF_Msk 0x100UL 4485 #define USB32DEV_ADAPTER_DMA_SCK_INTR_LAST_BUF_Pos 9UL 4486 #define USB32DEV_ADAPTER_DMA_SCK_INTR_LAST_BUF_Msk 0x200UL 4487 #define USB32DEV_ADAPTER_DMA_SCK_INTR_EVENT_RCVD_Pos 10UL 4488 #define USB32DEV_ADAPTER_DMA_SCK_INTR_EVENT_RCVD_Msk 0x400UL 4489 /* USB32DEV_ADAPTER_DMA_SCK.SCK_INTR_MASK */ 4490 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_PRODUCE_EVENT_Pos 0UL 4491 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_PRODUCE_EVENT_Msk 0x1UL 4492 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_CONSUME_EVENT_Pos 1UL 4493 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_CONSUME_EVENT_Msk 0x2UL 4494 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_DSCR_IS_LOW_Pos 2UL 4495 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_DSCR_IS_LOW_Msk 0x4UL 4496 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_DSCR_NOT_AVL_Pos 3UL 4497 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_DSCR_NOT_AVL_Msk 0x8UL 4498 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_STALL_Pos 4UL 4499 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_STALL_Msk 0x10UL 4500 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_SUSPEND_Pos 5UL 4501 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_SUSPEND_Msk 0x20UL 4502 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_ERROR_Pos 6UL 4503 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_ERROR_Msk 0x40UL 4504 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_TRANS_DONE_Pos 7UL 4505 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_TRANS_DONE_Msk 0x80UL 4506 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_PARTIAL_BUF_Pos 8UL 4507 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_PARTIAL_BUF_Msk 0x100UL 4508 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_LAST_BUF_Pos 9UL 4509 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_LAST_BUF_Msk 0x200UL 4510 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_EVENT_RCVD_Pos 10UL 4511 #define USB32DEV_ADAPTER_DMA_SCK_INTR_MASK_EVENT_RCVD_Msk 0x400UL 4512 /* USB32DEV_ADAPTER_DMA_SCK.DSCR_BUFFER */ 4513 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_BUFFER_BUFFER_ADDR_Pos 0UL 4514 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_BUFFER_BUFFER_ADDR_Msk 0x7FFFFFFFUL 4515 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_BUFFER_MARKER_Pos 31UL 4516 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_BUFFER_MARKER_Msk 0x80000000UL 4517 /* USB32DEV_ADAPTER_DMA_SCK.DSCR_SYNC */ 4518 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_CONS_SCK_Pos 0UL 4519 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_CONS_SCK_Msk 0xFFUL 4520 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_CONS_IP_Pos 8UL 4521 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_CONS_IP_Msk 0x3F00UL 4522 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_EN_CONS_EVENT_Pos 14UL 4523 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_EN_CONS_EVENT_Msk 0x4000UL 4524 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_EN_CONS_INT_Pos 15UL 4525 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_EN_CONS_INT_Msk 0x8000UL 4526 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_PROD_SCK_Pos 16UL 4527 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_PROD_SCK_Msk 0xFF0000UL 4528 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_PROD_IP_Pos 24UL 4529 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_PROD_IP_Msk 0x3F000000UL 4530 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_EN_PROD_EVENT_Pos 30UL 4531 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_EN_PROD_EVENT_Msk 0x40000000UL 4532 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_EN_PROD_INT_Pos 31UL 4533 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SYNC_EN_PROD_INT_Msk 0x80000000UL 4534 /* USB32DEV_ADAPTER_DMA_SCK.DSCR_CHAIN */ 4535 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_CHAIN_RD_NEXT_DSCR_Pos 0UL 4536 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_CHAIN_RD_NEXT_DSCR_Msk 0xFFFFUL 4537 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_CHAIN_WR_NEXT_DSCR_Pos 16UL 4538 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_CHAIN_WR_NEXT_DSCR_Msk 0xFFFF0000UL 4539 /* USB32DEV_ADAPTER_DMA_SCK.DSCR_SIZE */ 4540 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BYTE_COUNT_MSB_Pos 0UL 4541 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BYTE_COUNT_MSB_Msk 0x1UL 4542 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_EOP_Pos 1UL 4543 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_EOP_Msk 0x2UL 4544 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_ERROR_Pos 2UL 4545 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_ERROR_Msk 0x4UL 4546 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_OCCUPIED_Pos 3UL 4547 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_OCCUPIED_Msk 0x8UL 4548 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_SIZE_Pos 4UL 4549 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_SIZE_Msk 0xFFF0UL 4550 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BYTE_COUNT_Pos 16UL 4551 #define USB32DEV_ADAPTER_DMA_SCK_DSCR_SIZE_BYTE_COUNT_Msk 0xFFFF0000UL 4552 /* USB32DEV_ADAPTER_DMA_SCK.EVENT */ 4553 #define USB32DEV_ADAPTER_DMA_SCK_EVENT_ACTIVE_DSCR_Pos 0UL 4554 #define USB32DEV_ADAPTER_DMA_SCK_EVENT_ACTIVE_DSCR_Msk 0xFFFFUL 4555 #define USB32DEV_ADAPTER_DMA_SCK_EVENT_EVENT_TYPE_Pos 16UL 4556 #define USB32DEV_ADAPTER_DMA_SCK_EVENT_EVENT_TYPE_Msk 0x10000UL 4557 4558 4559 /* USB32DEV_ADAPTER_DMA_SCK_GBL.SCK_INTR */ 4560 #define USB32DEV_ADAPTER_DMA_SCK_GBL_SCK_INTR_SCKINTR_Pos 0UL 4561 #define USB32DEV_ADAPTER_DMA_SCK_GBL_SCK_INTR_SCKINTR_Msk 0xFFFFFFFFUL 4562 /* USB32DEV_ADAPTER_DMA_SCK_GBL.ADAPTER_CTRL */ 4563 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAPTER_EN_Pos 0UL 4564 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAPTER_EN_Msk 0x1UL 4565 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DATA_WR_PRIO_Pos 4UL 4566 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DATA_WR_PRIO_Msk 0x10UL 4567 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DATA_RD_PRIO_Pos 5UL 4568 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DATA_RD_PRIO_Msk 0x20UL 4569 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DESC_WR_PRIO_N_Pos 6UL 4570 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DESC_WR_PRIO_N_Msk 0x40UL 4571 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DESC_RD_PRIO_N_Pos 7UL 4572 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DESC_RD_PRIO_N_Msk 0x80UL 4573 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_SUSP_PARTIAL_NO_EVT_N_Pos 10UL 4574 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_SUSP_PARTIAL_NO_EVT_N_Msk 0x400UL 4575 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_FQ_DEPTH_CTRL_Pos 12UL 4576 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_FQ_DEPTH_CTRL_Msk 0x3F000UL 4577 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_DEBUG_CAPTURE_Pos 20UL 4578 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_DEBUG_CAPTURE_Msk 0x100000UL 4579 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_EN_UNALIGNED_READ_N_Pos 21UL 4580 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_EN_UNALIGNED_READ_N_Msk 0x200000UL 4581 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_TR_OUT_DELAY_Pos 24UL 4582 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_TR_OUT_DELAY_Msk 0x3F000000UL 4583 /* USB32DEV_ADAPTER_DMA_SCK_GBL.ADAPTER_DEBUG */ 4584 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_COUNT_Pos 0UL 4585 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_COUNT_Msk 0xFUL 4586 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_STATE_Pos 4UL 4587 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_STATE_Msk 0x70UL 4588 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_ID_Pos 7UL 4589 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_ID_Msk 0x1F80UL 4590 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_COUNT_Pos 13UL 4591 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_COUNT_Msk 0x3FE000UL 4592 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_STATE_Pos 22UL 4593 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_STATE_Msk 0x400000UL 4594 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_ID_Pos 23UL 4595 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_ID_Msk 0x1F800000UL 4596 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_ABORT_Pos 29UL 4597 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_ABORT_Msk 0x20000000UL 4598 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_BS_STATE_Pos 30UL 4599 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_BS_STATE_Msk 0xC0000000UL 4600 /* USB32DEV_ADAPTER_DMA_SCK_GBL.ADAPTER_CONF */ 4601 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_SOCKET_ACTIVE_THRSHLD_Pos 0UL 4602 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_SOCKET_ACTIVE_THRSHLD_Msk 0x3FUL 4603 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_STREAM_COUNT_Pos 6UL 4604 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_STREAM_COUNT_Msk 0x7FC0UL 4605 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_STREAMING_MODE_Pos 15UL 4606 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_STREAMING_MODE_Msk 0x8000UL 4607 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_TS_CYCLES_Pos 16UL 4608 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_TS_CYCLES_Msk 0xF0000UL 4609 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_ES_CYCLES_Pos 20UL 4610 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_ES_CYCLES_Msk 0xF00000UL 4611 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_GBL_CYCLES_Pos 24UL 4612 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_GBL_CYCLES_Msk 0xF000000UL 4613 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_MMIO_LOW_PRIORITY_Pos 28UL 4614 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_MMIO_LOW_PRIORITY_Msk 0x10000000UL 4615 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_SWITCH_HIGH_PRIORITY_Pos 29UL 4616 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_SWITCH_HIGH_PRIORITY_Msk 0x20000000UL 4617 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_TS_ABORT_EN_Pos 30UL 4618 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_TS_ABORT_EN_Msk 0x40000000UL 4619 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_DESCR_PF_EN_N_Pos 31UL 4620 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_DESCR_PF_EN_N_Msk 0x80000000UL 4621 /* USB32DEV_ADAPTER_DMA_SCK_GBL.ADAPTER_STATUS */ 4622 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_TTL_SOCKETS_Pos 0UL 4623 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_TTL_SOCKETS_Msk 0xFFUL 4624 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_IG_ONLY_Pos 8UL 4625 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_IG_ONLY_Msk 0xFF00UL 4626 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_FQ_SIZE_Pos 16UL 4627 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_FQ_SIZE_Msk 0x1FF0000UL 4628 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_WORD_SIZE_Pos 25UL 4629 #define USB32DEV_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_WORD_SIZE_Msk 0x6000000UL 4630 4631 4632 #endif /* _CYIP_USB32DEV_H_ */ 4633 4634 4635 /* [] END OF FILE */ 4636
