Home
last modified time | relevance | path

Searched refs:TCPWM_CNT_TR_CTRL2 (Results 1 – 7 of 7) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_tcpwm_pwm.c84 TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_PWM_MODE_PR; in Cy_TCPWM_PWM_Init()
91 TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_PWM_MODE_LEFT; in Cy_TCPWM_PWM_Init()
96 TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_PWM_MODE_RIGHT; in Cy_TCPWM_PWM_Init()
101 …TCPWM_CNT_TR_CTRL2(base, cntNum) = (config->swapOverflowUnderflow ? CY_TCPWM_PWM_MODE_CNTR_OR_ASYM… in Cy_TCPWM_PWM_Init()
371 TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_CNT_TR_CTRL2_DEFAULT; in Cy_TCPWM_PWM_DeInit()
Dcy_tcpwm_quaddec.c188 TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_CNT_TR_CTRL2_DEFAULT; in Cy_TCPWM_QuadDec_DeInit()
Dcy_tcpwm_counter.c243 TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_CNT_TR_CTRL2_DEFAULT; in Cy_TCPWM_Counter_DeInit()
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_pwm.c146 …bool is_center_aligned = (TCPWM_CNT_TR_CTRL2(obj->tcpwm.base, obj->tcpwm.resource.channel_num) == … in cyhal_pwm_set_period_and_compare()
147 …(TCPWM_CNT_TR_CTRL2(obj->tcpwm.base, obj->tcpwm.resource.channel_num) == _CYHAL_PWM_MODE_CNTR_OR_A… in cyhal_pwm_set_period_and_compare()
284 …TCPWM_CNT_TR_CTRL2(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource)) = _CYHAL_PWM_MOD… in _cyhal_pwm_init_hw()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h931 #define TCPWM_CNT_TR_CTRL2(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL2) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h602 #define TCPWM_CNT_TR_CTRL2(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL2) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h1645 #define TCPWM_CNT_TR_CTRL2(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL2) macro