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Searched refs:TCPWM_CNT_TR_CTRL0 (Results 1 – 8 of 8) sorted by relevance

/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_tcpwm_common.c785 TCPWM_CNT_TR_CTRL0(obj->base, chnl) &= ~TCPWM_CNT_TR_CTRL0_START_SEL_Msk; in _cyhal_tcpwm_irq_handler()
786TCPWM_CNT_TR_CTRL0(obj->base, chnl) |= _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, trigger_sig); in _cyhal_tcpwm_irq_handler()
791 TCPWM_CNT_TR_CTRL0(obj->base, chnl) &= ~TCPWM_CNT_TR_CTRL0_STOP_SEL_Msk; in _cyhal_tcpwm_irq_handler()
792TCPWM_CNT_TR_CTRL0(obj->base, chnl) |= _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, trigger_sig); in _cyhal_tcpwm_irq_handler()
797 TCPWM_CNT_TR_CTRL0(obj->base, chnl) &= ~TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Msk; in _cyhal_tcpwm_irq_handler()
798TCPWM_CNT_TR_CTRL0(obj->base, chnl) |= _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, trigger_sig); in _cyhal_tcpwm_irq_handler()
803 TCPWM_CNT_TR_CTRL0(obj->base, chnl) &= ~TCPWM_CNT_TR_CTRL0_COUNT_SEL_Msk; in _cyhal_tcpwm_irq_handler()
804TCPWM_CNT_TR_CTRL0(obj->base, chnl) |= _VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, trigger_sig); in _cyhal_tcpwm_irq_handler()
809 TCPWM_CNT_TR_CTRL0(obj->base, chnl) &= ~TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Msk; in _cyhal_tcpwm_irq_handler()
810TCPWM_CNT_TR_CTRL0(obj->base, chnl) |= _VAL2FLD(TCPWM_CNT_TR_CTRL0_CAPTURE_SEL, trigger_sig); in _cyhal_tcpwm_irq_handler()
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Dcyhal_quaddec.c174 TCPWM_CNT_TR_CTRL0(base, channel_num) &= ~TCPWM_CNT_TR_CTRL0_COUNT_SEL_Msk; in _cyhal_quaddec_connect_pin()
175 TCPWM_CNT_TR_CTRL0(base, channel_num) |= _VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, in _cyhal_quaddec_connect_pin()
183 TCPWM_CNT_TR_CTRL0(base, channel_num) &= ~TCPWM_CNT_TR_CTRL0_START_SEL_Msk; in _cyhal_quaddec_connect_pin()
184 TCPWM_CNT_TR_CTRL0(base, channel_num) |= _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, in _cyhal_quaddec_connect_pin()
192 TCPWM_CNT_TR_CTRL0(base, channel_num) &= ~TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Msk; in _cyhal_quaddec_connect_pin()
193 TCPWM_CNT_TR_CTRL0(base, channel_num) |= _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, in _cyhal_quaddec_connect_pin()
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_tcpwm_quaddec.c73TCPWM_CNT_TR_CTRL0(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->phiAInput) | in Cy_TCPWM_QuadDec_Init()
195 TCPWM_CNT_TR_CTRL0(base, cntNum) = CY_TCPWM_CNT_TR_CTRL0_DEFAULT; in Cy_TCPWM_QuadDec_DeInit()
Dcy_tcpwm_counter.c95TCPWM_CNT_TR_CTRL0(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_CAPTURE_SEL, config->captureInput)… in Cy_TCPWM_Counter_Init()
250 TCPWM_CNT_TR_CTRL0(base, cntNum) = CY_TCPWM_CNT_TR_CTRL0_DEFAULT; in Cy_TCPWM_Counter_DeInit()
Dcy_tcpwm_pwm.c117 TCPWM_CNT_TR_CTRL0(base, cntNum) = in Cy_TCPWM_PWM_Init()
378 TCPWM_CNT_TR_CTRL0(base, cntNum) = CY_TCPWM_CNT_TR_CTRL0_DEFAULT; in Cy_TCPWM_PWM_DeInit()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h929 #define TCPWM_CNT_TR_CTRL0(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL0) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h600 #define TCPWM_CNT_TR_CTRL0(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL0) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h1643 #define TCPWM_CNT_TR_CTRL0(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL0) macro