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Searched refs:SRSS_TRIM_RAM_CTL_WC_MASK (Results 1 – 1 of 1) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_syspm_v2.c99 #define SRSS_TRIM_RAM_CTL_WC_MASK (0x3UL << 10U) macro
2488 uint32_t trimRamCheckVal = (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_WC_MASK); in IsVoltageChangePossible()
2490 SRSS_TRIM_RAM_CTL &= ~SRSS_TRIM_RAM_CTL_WC_MASK; in IsVoltageChangePossible()
2491 SRSS_TRIM_RAM_CTL |= ((~trimRamCheckVal) & SRSS_TRIM_RAM_CTL_WC_MASK); in IsVoltageChangePossible()
2493 retVal = (trimRamCheckVal != (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_WC_MASK)); in IsVoltageChangePossible()