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Searched refs:SRSS_CLK_TIMER_CTL (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_sysclk.c450 CY_REG32_CLR_SET(SRSS_CLK_TIMER_CTL, CY_SRSS_CLK_TIMER_CTL_TIMER, source); in Cy_SysClk_ClkTimerSetSource()
458 …return ((cy_en_clktimer_in_sources_t)((uint32_t)(SRSS_CLK_TIMER_CTL & CY_SRSS_CLK_TIMER_CTL_TIMER_… in Cy_SysClk_ClkTimerGetSource()
474 CY_REG32_CLR_SET(SRSS_CLK_TIMER_CTL, SRSS_CLK_TIMER_CTL_TIMER_DIV, divider); in Cy_SysClk_ClkTimerSetDivider()
481 return ((uint8_t)_FLD2VAL(SRSS_CLK_TIMER_CTL_TIMER_DIV, SRSS_CLK_TIMER_CTL)); in Cy_SysClk_ClkTimerGetDivider()
497 SRSS_CLK_TIMER_CTL |= SRSS_CLK_TIMER_CTL_ENABLE_Msk; in Cy_SysClk_ClkTimerEnable()
504 return (_FLD2BOOL(SRSS_CLK_TIMER_CTL_ENABLE, SRSS_CLK_TIMER_CTL)); in Cy_SysClk_ClkTimerIsEnabled()
520 SRSS_CLK_TIMER_CTL &= ~SRSS_CLK_TIMER_CTL_ENABLE_Msk; in Cy_SysClk_ClkTimerDisable()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h408 #define SRSS_CLK_TIMER_CTL (((SRSS_Type *) SRSS)->CLK_TIMER_CTL) macro
510 #define SRSS_CLK_TIMER_CTL (((SRSS_V1_Type *) SRSS)->CLK_TIMER_CTL) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h214 #define SRSS_CLK_TIMER_CTL (((SRSS_Type *) SRSS)->CLK_TIMER_CTL) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h1028 #define SRSS_CLK_TIMER_CTL (((SRSS_Type *) SRSS)->CLK_TIMER_CTL) macro