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Searched refs:SRSS_CLK_PLL_CONFIG (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_sysclk.c1780 return (_FLD2BOOL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS_CLK_PLL_CONFIG[clkPath])); in Cy_SysClk_PllIsEnabled()
1820 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OU… in Cy_SysClk_PllDisable()
1824 SRSS_CLK_PLL_CONFIG[clkPath] &= ~SRSS_CLK_PLL_CONFIG_ENABLE_Msk; in Cy_SysClk_PllDisable()
1944 SRSS_CLK_PLL_CONFIG[clkPath] = in Cy_SysClk_PllManualConfigure()
1951 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, (uint32_t)config->o… in Cy_SysClk_PllManualConfigure()
1965 uint32_t tempReg = SRSS_CLK_PLL_CONFIG[clkPath]; in Cy_SysClk_PllGetConfiguration()
1991 SRSS_CLK_PLL_CONFIG[clkPath] |= SRSS_CLK_PLL_CONFIG_ENABLE_Msk; in Cy_SysClk_PllEnable()
2003 …L_OUTPUT_INPUT == (uint32_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[clkPath])) in Cy_SysClk_PllEnable()
2005 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OU… in Cy_SysClk_PllEnable()
2013 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OU… in Cy_SysClk_PllEnable()
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Dcy_sysclk_v2.c4255 return (_FLD2BOOL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS_CLK_PLL_CONFIG[pllNum])); in Cy_SysClk_Pll200MIsEnabled()
4283 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[pllNum], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUT… in Cy_SysClk_Pll200MDisable()
4287 SRSS_CLK_PLL_CONFIG[pllNum] &= ~SRSS_CLK_PLL_CONFIG_ENABLE_Msk; in Cy_SysClk_Pll200MDisable()
4397 SRSS_CLK_PLL_CONFIG[pllNum] = in Cy_SysClk_Pll200MManualConfigure()
4404 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[pllNum], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, (uint32_t)config->ou… in Cy_SysClk_Pll200MManualConfigure()
4420 uint32_t tempReg = SRSS_CLK_PLL_CONFIG[pllNum]; in Cy_SysClk_Pll200MGetConfiguration()
4439 SRSS_CLK_PLL_CONFIG[pllNum] |= SRSS_CLK_PLL_CONFIG_ENABLE_Msk; in Cy_SysClk_Pll200MEnable()
4452 …LL_OUTPUT_INPUT == (uint32_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[pllNum])) in Cy_SysClk_Pll200MEnable()
4454 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[pllNum], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUT… in Cy_SysClk_Pll200MEnable()
4462 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[pllNum], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUT… in Cy_SysClk_Pll200MEnable()
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Dcy_pra.c2966 …LK_FLLPLL_OUTPUT_AUTO == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[fllPll - 1U… in Cy_PRA_ClkDSBeforeTransition()
2967 …LK_FLLPLL_OUTPUT_AUTO1 == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[fllPll - 1U… in Cy_PRA_ClkDSBeforeTransition()
2972 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLP… in Cy_PRA_ClkDSBeforeTransition()
3060 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLP… in Cy_PRA_ClkDSAfterTransition()
3064 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLP… in Cy_PRA_ClkDSAfterTransition()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h440 #define SRSS_CLK_PLL_CONFIG (((SRSS_Type *) SRSS)->CLK_PLL_CONFIG) macro
527 #define SRSS_CLK_PLL_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_PLL_CONFIG) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h246 #define SRSS_CLK_PLL_CONFIG (((SRSS_Type *) SRSS)->CLK_PLL_CONFIG) macro