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Searched refs:SRSS_CLK_FLL_CONFIG3 (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_sysclk.c1459 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_SysClk_FllDisable()
1598 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_SysClk_FllConfigure()
1641 SRSS_CLK_FLL_CONFIG3 = _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, config->igain) | in Cy_SysClk_FllManualConfigure()
1674 tempReg = SRSS_CLK_FLL_CONFIG3; in Cy_SysClk_FllGetConfiguration()
1706 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_SysClk_FllEnable()
1724 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OU… in Cy_SysClk_FllEnable()
2563 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_SysClk_DeepSleepCallback()
2584 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_SysClk_DeepSleepCallback()
2652 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OU… in Cy_SysClk_DeepSleepCallback()
2683 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OU… in Cy_SysClk_DeepSleepCallback()
Dcy_pra.c2962 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_PRA_ClkDSBeforeTransition()
2983 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_PRA_ClkDSBeforeTransition()
3054 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OU… in Cy_PRA_ClkDSAfterTransition()
3085 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OU… in Cy_PRA_ClkDSAfterTransition()
Dcy_sysclk_v2.c3404 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_SysClk_FllDisable()
3407 …_SYSCLK_FLLPLL_OUTPUT_INPUT) != _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS_CLK_FLL_CONFIG3)) && in Cy_SysClk_FllDisable()
3568 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_SysClk_FllConfigure()
3613 SRSS_CLK_FLL_CONFIG3 = _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, config->igain) | in Cy_SysClk_FllManualConfigure()
3650 tempReg = SRSS_CLK_FLL_CONFIG3; in Cy_SysClk_FllGetConfiguration()
3687 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_SysClk_FllEnable()
3706 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OU… in Cy_SysClk_FllEnable()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h426 #define SRSS_CLK_FLL_CONFIG3 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG3) macro
524 #define SRSS_CLK_FLL_CONFIG3 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG3) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h232 #define SRSS_CLK_FLL_CONFIG3 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG3) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h1069 #define SRSS_CLK_FLL_CONFIG3 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG3) macro