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Searched refs:SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_syspm.c2229 …CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK… in SetReadMarginTrimUlp()
Dcy_syspm_v2.c2341 …SRSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP & ((uint32_t) ~SRSS_TRIM_RAM_CTL_RA_MASK))… in SetReadMarginTrimUlp()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h759 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_U… macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h440 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_U… macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h1530 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (((SFLASH_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_ULP) macro