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Searched refs:SCU_RESET (Results 1 – 10 of 10) sorted by relevance

/hal_infineon-latest/XMCLib/drivers/inc/
Dxmc_scu.h393 return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk); in XMC_SCU_RESET_GetDeviceResetReason()
409 SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk; in XMC_SCU_RESET_ClearDeviceResetReason()
Dxmc1_scu.h1071 SCU_RESET->RSTCON |= SCU_RESET_RSTCON_MRSTEN_Msk; in XMC_SCU_RESET_AssertMasterReset()
1095 SCU_RESET->RSTCON |= request; in XMC_SCU_RESET_EnableResetRequest()
Dxmc4_scu.h3212 return ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBWK_Msk) != 0U); in XMC_SCU_HIB_IsWakeupEventDetected()
3223 SCU_RESET->RSTCLR = SCU_RESET_RSTCLR_HIBWK_Msk; in XMC_SCU_HIB_ClearWakeupEventDetectionStatus()
/hal_infineon-latest/XMCLib/drivers/src/
Dxmc4_scu.c663 *(uint32_t *)(&(SCU_RESET->PRSET0) + (index * 3U)) = (uint32_t)mask; in XMC_SCU_RESET_AssertPeripheralReset()
672 *(uint32_t *)(&(SCU_RESET->PRCLR0) + (index * 3U)) = (uint32_t)mask; in XMC_SCU_RESET_DeassertPeripheralReset()
681 return ((*(uint32_t *)(&(SCU_RESET->PRSTAT0) + (index * 3U)) & mask) != 0U); in XMC_SCU_RESET_IsPeripheralResetAsserted()
1222 if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) in XMC_SCU_HIB_EnableHibernateDomain()
1224 SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_HIBRS_Msk; in XMC_SCU_HIB_EnableHibernateDomain()
1225 while((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk) != 0UL) in XMC_SCU_HIB_EnableHibernateDomain()
1238 SCU_RESET->RSTSET = (uint32_t)SCU_RESET_RSTSET_HIBRS_Msk; in XMC_SCU_HIB_DisableHibernateDomain()
1245 !(bool)(SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)); in XMC_SCU_HIB_IsHibernateDomainEnabled()
/hal_infineon-latest/XMCLib/devices/XMC4500/Source/
Dsystem_XMC4500.c385 if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) in SystemCoreClockSetup()
387 SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; in SystemCoreClockSetup()
/hal_infineon-latest/XMCLib/devices/XMC4700/Source/
Dsystem_XMC4700.c448 if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) in SystemCoreClockSetup()
450 SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; in SystemCoreClockSetup()
/hal_infineon-latest/XMCLib/devices/XMC4800/Source/
Dsystem_XMC4800.c501 if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) in SystemCoreClockSetup()
503 SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; in SystemCoreClockSetup()
/hal_infineon-latest/XMCLib/devices/XMC4500/Include/
DXMC4500.h16327 #define SCU_RESET ((SCU_RESET_TypeDef *) SCU_RESET_BASE) macro
/hal_infineon-latest/XMCLib/devices/XMC4700/Include/
DXMC4700.h17582 #define SCU_RESET ((SCU_RESET_TypeDef *) SCU_RESET_BASE) macro
/hal_infineon-latest/XMCLib/devices/XMC4800/Include/
DXMC4800.h18626 #define SCU_RESET ((SCU_RESET_TypeDef *) SCU_RESET_BASE) macro